1 //===- FunctionLoweringInfo.h - Lower functions from LLVM IR ---*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements routines for translating functions from LLVM IR into
10 // Machine IR.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
15 #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
16 
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/IndexedMap.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/ISDOpcodes.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/TargetRegisterInfo.h"
25 #include "llvm/IR/Instructions.h"
26 #include "llvm/IR/Type.h"
27 #include "llvm/IR/Value.h"
28 #include "llvm/Support/KnownBits.h"
29 #include <cassert>
30 #include <utility>
31 #include <vector>
32 
33 namespace llvm {
34 
35 class Argument;
36 class BasicBlock;
37 class BranchProbabilityInfo;
38 class DbgDeclareInst;
39 class Function;
40 class Instruction;
41 class MachineFunction;
42 class MachineInstr;
43 class MachineRegisterInfo;
44 class MVT;
45 class SelectionDAG;
46 class TargetLowering;
47 
48 template <typename T> class GenericSSAContext;
49 using SSAContext = GenericSSAContext<Function>;
50 template <typename T> class GenericUniformityInfo;
51 using UniformityInfo = GenericUniformityInfo<SSAContext>;
52 
53 //===--------------------------------------------------------------------===//
54 /// FunctionLoweringInfo - This contains information that is global to a
55 /// function that is used when lowering a region of the function.
56 ///
57 class FunctionLoweringInfo {
58 public:
59   const Function *Fn;
60   MachineFunction *MF;
61   const TargetLowering *TLI;
62   MachineRegisterInfo *RegInfo;
63   BranchProbabilityInfo *BPI;
64   const UniformityInfo *UA;
65   /// CanLowerReturn - true iff the function's return value can be lowered to
66   /// registers.
67   bool CanLowerReturn;
68 
69   /// True if part of the CSRs will be handled via explicit copies.
70   bool SplitCSR;
71 
72   /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
73   /// allocated to hold a pointer to the hidden sret parameter.
74   Register DemoteRegister;
75 
76   /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
77   DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
78 
79   /// ValueMap - Since we emit code for the function a basic block at a time,
80   /// we must remember which virtual registers hold the values for
81   /// cross-basic-block values.
82   DenseMap<const Value *, Register> ValueMap;
83 
84   /// VirtReg2Value map is needed by the Divergence Analysis driven
85   /// instruction selection. It is reverted ValueMap. It is computed
86   /// in lazy style - on demand. It is used to get the Value corresponding
87   /// to the live in virtual register and is called from the
88   /// TargetLowerinInfo::isSDNodeSourceOfDivergence.
89   DenseMap<Register, const Value*> VirtReg2Value;
90 
91   /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence
92   /// to get the Value corresponding to the live-in virtual register.
93   const Value *getValueFromVirtualReg(Register Vreg);
94 
95   /// Track virtual registers created for exception pointers.
96   DenseMap<const Value *, Register> CatchPadExceptionPointers;
97 
98   /// Helper object to track which of three possible relocation mechanisms are
99   /// used for a particular value being relocated over a statepoint.
100   struct StatepointRelocationRecord {
101     enum RelocType {
102       // Value did not need to be relocated and can be used directly.
103       NoRelocate,
104       // Value was spilled to stack and needs filled at the gc.relocate.
105       Spill,
106       // Value was lowered to tied def and gc.relocate should be replaced with
107       // copy from vreg.
108       VReg,
109       // Value was lowered to tied def and gc.relocate should be replaced with
110       // SDValue kept in StatepointLoweringInfo structure. This valid for local
111       // relocates only.
112       SDValueNode,
113     } type = NoRelocate;
114     // Payload contains either frame index of the stack slot in which the value
115     // was spilled, or virtual register which contains the re-definition.
116     union payload_t {
117       payload_t() : FI(-1) {}
118       int FI;
119       Register Reg;
120     } payload;
121   };
122 
123   /// Keep track of each value which was relocated and the strategy used to
124   /// relocate that value.  This information is required when visiting
125   /// gc.relocates which may appear in following blocks.
126   using StatepointSpillMapTy =
127     DenseMap<const Value *, StatepointRelocationRecord>;
128   DenseMap<const Instruction *, StatepointSpillMapTy> StatepointRelocationMaps;
129 
130   /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
131   /// the entry block.  This allows the allocas to be efficiently referenced
132   /// anywhere in the function.
133   DenseMap<const AllocaInst*, int> StaticAllocaMap;
134 
135   /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
136   DenseMap<const Argument*, int> ByValArgFrameIndexMap;
137 
138   /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
139   /// function arguments that are inserted after scheduling is completed.
140   SmallVector<MachineInstr*, 8> ArgDbgValues;
141 
142   /// Bitvector with a bit set if corresponding argument is described in
143   /// ArgDbgValues. Using arg numbers according to Argument numbering.
144   BitVector DescribedArgs;
145 
146   /// RegFixups - Registers which need to be replaced after isel is done.
147   DenseMap<Register, Register> RegFixups;
148 
149   DenseSet<Register> RegsWithFixups;
150 
151   /// StatepointStackSlots - A list of temporary stack slots (frame indices)
152   /// used to spill values at a statepoint.  We store them here to enable
153   /// reuse of the same stack slots across different statepoints in different
154   /// basic blocks.
155   SmallVector<unsigned, 50> StatepointStackSlots;
156 
157   /// MBB - The current block.
158   MachineBasicBlock *MBB;
159 
160   /// MBB - The current insert position inside the current block.
161   MachineBasicBlock::iterator InsertPt;
162 
163   struct LiveOutInfo {
164     unsigned NumSignBits : 31;
165     unsigned IsValid : 1;
166     KnownBits Known = 1;
167 
168     LiveOutInfo() : NumSignBits(0), IsValid(true) {}
169   };
170 
171   /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
172   /// for a value.
173   DenseMap<const Value *, ISD::NodeType> PreferredExtendType;
174 
175   /// VisitedBBs - The set of basic blocks visited thus far by instruction
176   /// selection.
177   SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
178 
179   /// PHINodesToUpdate - A list of phi instructions whose operand list will
180   /// be updated after processing the current basic block.
181   /// TODO: This isn't per-function state, it's per-basic-block state. But
182   /// there's no other convenient place for it to live right now.
183   std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
184   unsigned OrigNumPHINodesToUpdate;
185 
186   /// If the current MBB is a landing pad, the exception pointer and exception
187   /// selector registers are copied into these virtual registers by
188   /// SelectionDAGISel::PrepareEHLandingPad().
189   unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
190 
191   /// Collection of dbg.declare instructions handled after argument
192   /// lowering and before ISel proper.
193   SmallPtrSet<const DbgDeclareInst *, 8> PreprocessedDbgDeclares;
194 
195   /// set - Initialize this FunctionLoweringInfo with the given Function
196   /// and its associated MachineFunction.
197   ///
198   void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
199 
200   /// clear - Clear out all the function-specific state. This returns this
201   /// FunctionLoweringInfo to an empty state, ready to be used for a
202   /// different function.
203   void clear();
204 
205   /// isExportedInst - Return true if the specified value is an instruction
206   /// exported from its block.
207   bool isExportedInst(const Value *V) const {
208     return ValueMap.count(V);
209   }
210 
211   Register CreateReg(MVT VT, bool isDivergent = false);
212 
213   Register CreateRegs(const Value *V);
214 
215   Register CreateRegs(Type *Ty, bool isDivergent = false);
216 
217   Register InitializeRegForValue(const Value *V) {
218     // Tokens never live in vregs.
219     if (V->getType()->isTokenTy())
220       return 0;
221     Register &R = ValueMap[V];
222     assert(R == 0 && "Already initialized this value register!");
223     assert(VirtReg2Value.empty());
224     return R = CreateRegs(V);
225   }
226 
227   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
228   /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
229   const LiveOutInfo *GetLiveOutRegInfo(Register Reg) {
230     if (!LiveOutRegInfo.inBounds(Reg))
231       return nullptr;
232 
233     const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
234     if (!LOI->IsValid)
235       return nullptr;
236 
237     return LOI;
238   }
239 
240   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
241   /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
242   /// the register's LiveOutInfo is for a smaller bit width, it is extended to
243   /// the larger bit width by zero extension. The bit width must be no smaller
244   /// than the LiveOutInfo's existing bit width.
245   const LiveOutInfo *GetLiveOutRegInfo(Register Reg, unsigned BitWidth);
246 
247   /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
248   void AddLiveOutRegInfo(Register Reg, unsigned NumSignBits,
249                          const KnownBits &Known) {
250     // Only install this information if it tells us something.
251     if (NumSignBits == 1 && Known.isUnknown())
252       return;
253 
254     LiveOutRegInfo.grow(Reg);
255     LiveOutInfo &LOI = LiveOutRegInfo[Reg];
256     LOI.NumSignBits = NumSignBits;
257     LOI.Known.One = Known.One;
258     LOI.Known.Zero = Known.Zero;
259   }
260 
261   /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
262   /// register based on the LiveOutInfo of its operands.
263   void ComputePHILiveOutRegInfo(const PHINode*);
264 
265   /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
266   /// called when a block is visited before all of its predecessors.
267   void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
268     // PHIs with no uses have no ValueMap entry.
269     DenseMap<const Value*, Register>::const_iterator It = ValueMap.find(PN);
270     if (It == ValueMap.end())
271       return;
272 
273     Register Reg = It->second;
274     if (Reg == 0)
275       return;
276 
277     LiveOutRegInfo.grow(Reg);
278     LiveOutRegInfo[Reg].IsValid = false;
279   }
280 
281   /// setArgumentFrameIndex - Record frame index for the byval
282   /// argument.
283   void setArgumentFrameIndex(const Argument *A, int FI);
284 
285   /// getArgumentFrameIndex - Get frame index for the byval argument.
286   int getArgumentFrameIndex(const Argument *A);
287 
288   Register getCatchPadExceptionPointerVReg(const Value *CPI,
289                                            const TargetRegisterClass *RC);
290 
291 private:
292   /// LiveOutRegInfo - Information about live out vregs.
293   IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
294 };
295 
296 } // end namespace llvm
297 
298 #endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
299