1 //===- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the IRTranslator pass. 10 /// This pass is responsible for translating LLVM IR into MachineInstr. 11 /// It uses target hooks to lower the ABI but aside from that, the pass 12 /// generated code is generic. This is the default translator used for 13 /// GlobalISel. 14 /// 15 /// \todo Replace the comments with actual doxygen comments. 16 //===----------------------------------------------------------------------===// 17 18 #ifndef LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H 19 #define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H 20 21 #include "llvm/ADT/DenseMap.h" 22 #include "llvm/ADT/SmallVector.h" 23 #include "llvm/CodeGen/CodeGenCommonISel.h" 24 #include "llvm/CodeGen/FunctionLoweringInfo.h" 25 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 26 #include "llvm/CodeGen/MachineFunctionPass.h" 27 #include "llvm/CodeGen/SwiftErrorValueTracking.h" 28 #include "llvm/CodeGen/SwitchLoweringUtils.h" 29 #include "llvm/Support/Allocator.h" 30 #include "llvm/Support/CodeGen.h" 31 #include <memory> 32 #include <utility> 33 34 namespace llvm { 35 36 class AllocaInst; 37 class BasicBlock; 38 class CallInst; 39 class CallLowering; 40 class Constant; 41 class ConstrainedFPIntrinsic; 42 class DataLayout; 43 class Instruction; 44 class MachineBasicBlock; 45 class MachineFunction; 46 class MachineInstr; 47 class MachineRegisterInfo; 48 class OptimizationRemarkEmitter; 49 class PHINode; 50 class TargetPassConfig; 51 class User; 52 class Value; 53 54 // Technically the pass should run on an hypothetical MachineModule, 55 // since it should translate Global into some sort of MachineGlobal. 56 // The MachineGlobal should ultimately just be a transfer of ownership of 57 // the interesting bits that are relevant to represent a global value. 58 // That being said, we could investigate what would it cost to just duplicate 59 // the information from the LLVM IR. 60 // The idea is that ultimately we would be able to free up the memory used 61 // by the LLVM IR as soon as the translation is over. 62 class IRTranslator : public MachineFunctionPass { 63 public: 64 static char ID; 65 66 private: 67 /// Interface used to lower the everything related to calls. 68 const CallLowering *CLI; 69 70 /// This class contains the mapping between the Values to vreg related data. 71 class ValueToVRegInfo { 72 public: 73 ValueToVRegInfo() = default; 74 75 using VRegListT = SmallVector<Register, 1>; 76 using OffsetListT = SmallVector<uint64_t, 1>; 77 78 using const_vreg_iterator = 79 DenseMap<const Value *, VRegListT *>::const_iterator; 80 using const_offset_iterator = 81 DenseMap<const Value *, OffsetListT *>::const_iterator; 82 83 inline const_vreg_iterator vregs_end() const { return ValToVRegs.end(); } 84 85 VRegListT *getVRegs(const Value &V) { 86 auto It = ValToVRegs.find(&V); 87 if (It != ValToVRegs.end()) 88 return It->second; 89 90 return insertVRegs(V); 91 } 92 93 OffsetListT *getOffsets(const Value &V) { 94 auto It = TypeToOffsets.find(V.getType()); 95 if (It != TypeToOffsets.end()) 96 return It->second; 97 98 return insertOffsets(V); 99 } 100 101 const_vreg_iterator findVRegs(const Value &V) const { 102 return ValToVRegs.find(&V); 103 } 104 105 bool contains(const Value &V) const { 106 return ValToVRegs.find(&V) != ValToVRegs.end(); 107 } 108 109 void reset() { 110 ValToVRegs.clear(); 111 TypeToOffsets.clear(); 112 VRegAlloc.DestroyAll(); 113 OffsetAlloc.DestroyAll(); 114 } 115 116 private: 117 VRegListT *insertVRegs(const Value &V) { 118 assert(ValToVRegs.find(&V) == ValToVRegs.end() && "Value already exists"); 119 120 // We placement new using our fast allocator since we never try to free 121 // the vectors until translation is finished. 122 auto *VRegList = new (VRegAlloc.Allocate()) VRegListT(); 123 ValToVRegs[&V] = VRegList; 124 return VRegList; 125 } 126 127 OffsetListT *insertOffsets(const Value &V) { 128 assert(TypeToOffsets.find(V.getType()) == TypeToOffsets.end() && 129 "Type already exists"); 130 131 auto *OffsetList = new (OffsetAlloc.Allocate()) OffsetListT(); 132 TypeToOffsets[V.getType()] = OffsetList; 133 return OffsetList; 134 } 135 SpecificBumpPtrAllocator<VRegListT> VRegAlloc; 136 SpecificBumpPtrAllocator<OffsetListT> OffsetAlloc; 137 138 // We store pointers to vectors here since references may be invalidated 139 // while we hold them if we stored the vectors directly. 140 DenseMap<const Value *, VRegListT*> ValToVRegs; 141 DenseMap<const Type *, OffsetListT*> TypeToOffsets; 142 }; 143 144 /// Mapping of the values of the current LLVM IR function to the related 145 /// virtual registers and offsets. 146 ValueToVRegInfo VMap; 147 148 // N.b. it's not completely obvious that this will be sufficient for every 149 // LLVM IR construct (with "invoke" being the obvious candidate to mess up our 150 // lives. 151 DenseMap<const BasicBlock *, MachineBasicBlock *> BBToMBB; 152 153 // One BasicBlock can be translated to multiple MachineBasicBlocks. For such 154 // BasicBlocks translated to multiple MachineBasicBlocks, MachinePreds retains 155 // a mapping between the edges arriving at the BasicBlock to the corresponding 156 // created MachineBasicBlocks. Some BasicBlocks that get translated to a 157 // single MachineBasicBlock may also end up in this Map. 158 using CFGEdge = std::pair<const BasicBlock *, const BasicBlock *>; 159 DenseMap<CFGEdge, SmallVector<MachineBasicBlock *, 1>> MachinePreds; 160 161 // List of stubbed PHI instructions, for values and basic blocks to be filled 162 // in once all MachineBasicBlocks have been created. 163 SmallVector<std::pair<const PHINode *, SmallVector<MachineInstr *, 1>>, 4> 164 PendingPHIs; 165 166 /// Record of what frame index has been allocated to specified allocas for 167 /// this function. 168 DenseMap<const AllocaInst *, int> FrameIndices; 169 170 SwiftErrorValueTracking SwiftError; 171 172 /// \name Methods for translating form LLVM IR to MachineInstr. 173 /// \see ::translate for general information on the translate methods. 174 /// @{ 175 176 /// Translate \p Inst into its corresponding MachineInstr instruction(s). 177 /// Insert the newly translated instruction(s) right where the CurBuilder 178 /// is set. 179 /// 180 /// The general algorithm is: 181 /// 1. Look for a virtual register for each operand or 182 /// create one. 183 /// 2 Update the VMap accordingly. 184 /// 2.alt. For constant arguments, if they are compile time constants, 185 /// produce an immediate in the right operand and do not touch 186 /// ValToReg. Actually we will go with a virtual register for each 187 /// constants because it may be expensive to actually materialize the 188 /// constant. Moreover, if the constant spans on several instructions, 189 /// CSE may not catch them. 190 /// => Update ValToVReg and remember that we saw a constant in Constants. 191 /// We will materialize all the constants in finalize. 192 /// Note: we would need to do something so that we can recognize such operand 193 /// as constants. 194 /// 3. Create the generic instruction. 195 /// 196 /// \return true if the translation succeeded. 197 bool translate(const Instruction &Inst); 198 199 /// Materialize \p C into virtual-register \p Reg. The generic instructions 200 /// performing this materialization will be inserted into the entry block of 201 /// the function. 202 /// 203 /// \return true if the materialization succeeded. 204 bool translate(const Constant &C, Register Reg); 205 206 // Translate U as a copy of V. 207 bool translateCopy(const User &U, const Value &V, 208 MachineIRBuilder &MIRBuilder); 209 210 /// Translate an LLVM bitcast into generic IR. Either a COPY or a G_BITCAST is 211 /// emitted. 212 bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder); 213 214 /// Translate an LLVM load instruction into generic IR. 215 bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder); 216 217 /// Translate an LLVM store instruction into generic IR. 218 bool translateStore(const User &U, MachineIRBuilder &MIRBuilder); 219 220 /// Translate an LLVM string intrinsic (memcpy, memset, ...). 221 bool translateMemFunc(const CallInst &CI, MachineIRBuilder &MIRBuilder, 222 unsigned Opcode); 223 224 void getStackGuard(Register DstReg, MachineIRBuilder &MIRBuilder); 225 226 bool translateOverflowIntrinsic(const CallInst &CI, unsigned Op, 227 MachineIRBuilder &MIRBuilder); 228 bool translateFixedPointIntrinsic(unsigned Op, const CallInst &CI, 229 MachineIRBuilder &MIRBuilder); 230 231 /// Helper function for translateSimpleIntrinsic. 232 /// \return The generic opcode for \p IntrinsicID if \p IntrinsicID is a 233 /// simple intrinsic (ceil, fabs, etc.). Otherwise, returns 234 /// Intrinsic::not_intrinsic. 235 unsigned getSimpleIntrinsicOpcode(Intrinsic::ID ID); 236 237 /// Translates the intrinsics defined in getSimpleIntrinsicOpcode. 238 /// \return true if the translation succeeded. 239 bool translateSimpleIntrinsic(const CallInst &CI, Intrinsic::ID ID, 240 MachineIRBuilder &MIRBuilder); 241 242 bool translateConstrainedFPIntrinsic(const ConstrainedFPIntrinsic &FPI, 243 MachineIRBuilder &MIRBuilder); 244 245 bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, 246 MachineIRBuilder &MIRBuilder); 247 248 bool translateInlineAsm(const CallBase &CB, MachineIRBuilder &MIRBuilder); 249 250 /// Common code for translating normal calls or invokes. 251 bool translateCallBase(const CallBase &CB, MachineIRBuilder &MIRBuilder); 252 253 /// Translate call instruction. 254 /// \pre \p U is a call instruction. 255 bool translateCall(const User &U, MachineIRBuilder &MIRBuilder); 256 257 /// When an invoke or a cleanupret unwinds to the next EH pad, there are 258 /// many places it could ultimately go. In the IR, we have a single unwind 259 /// destination, but in the machine CFG, we enumerate all the possible blocks. 260 /// This function skips over imaginary basic blocks that hold catchswitch 261 /// instructions, and finds all the "real" machine 262 /// basic block destinations. As those destinations may not be successors of 263 /// EHPadBB, here we also calculate the edge probability to those 264 /// destinations. The passed-in Prob is the edge probability to EHPadBB. 265 bool findUnwindDestinations( 266 const BasicBlock *EHPadBB, BranchProbability Prob, 267 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>> 268 &UnwindDests); 269 270 bool translateInvoke(const User &U, MachineIRBuilder &MIRBuilder); 271 272 bool translateCallBr(const User &U, MachineIRBuilder &MIRBuilder); 273 274 bool translateLandingPad(const User &U, MachineIRBuilder &MIRBuilder); 275 276 /// Translate one of LLVM's cast instructions into MachineInstrs, with the 277 /// given generic Opcode. 278 bool translateCast(unsigned Opcode, const User &U, 279 MachineIRBuilder &MIRBuilder); 280 281 /// Translate a phi instruction. 282 bool translatePHI(const User &U, MachineIRBuilder &MIRBuilder); 283 284 /// Translate a comparison (icmp or fcmp) instruction or constant. 285 bool translateCompare(const User &U, MachineIRBuilder &MIRBuilder); 286 287 /// Translate an integer compare instruction (or constant). 288 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { 289 return translateCompare(U, MIRBuilder); 290 } 291 292 /// Translate a floating-point compare instruction (or constant). 293 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { 294 return translateCompare(U, MIRBuilder); 295 } 296 297 /// Add remaining operands onto phis we've translated. Executed after all 298 /// MachineBasicBlocks for the function have been created. 299 void finishPendingPhis(); 300 301 /// Translate \p Inst into a unary operation \p Opcode. 302 /// \pre \p U is a unary operation. 303 bool translateUnaryOp(unsigned Opcode, const User &U, 304 MachineIRBuilder &MIRBuilder); 305 306 /// Translate \p Inst into a binary operation \p Opcode. 307 /// \pre \p U is a binary operation. 308 bool translateBinaryOp(unsigned Opcode, const User &U, 309 MachineIRBuilder &MIRBuilder); 310 311 /// If the set of cases should be emitted as a series of branches, return 312 /// true. If we should emit this as a bunch of and/or'd together conditions, 313 /// return false. 314 bool shouldEmitAsBranches(const std::vector<SwitchCG::CaseBlock> &Cases); 315 /// Helper method for findMergedConditions. 316 /// This function emits a branch and is used at the leaves of an OR or an 317 /// AND operator tree. 318 void emitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, 319 MachineBasicBlock *FBB, 320 MachineBasicBlock *CurBB, 321 MachineBasicBlock *SwitchBB, 322 BranchProbability TProb, 323 BranchProbability FProb, bool InvertCond); 324 /// Used during condbr translation to find trees of conditions that can be 325 /// optimized. 326 void findMergedConditions(const Value *Cond, MachineBasicBlock *TBB, 327 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 328 MachineBasicBlock *SwitchBB, 329 Instruction::BinaryOps Opc, BranchProbability TProb, 330 BranchProbability FProb, bool InvertCond); 331 332 /// Translate branch (br) instruction. 333 /// \pre \p U is a branch instruction. 334 bool translateBr(const User &U, MachineIRBuilder &MIRBuilder); 335 336 // Begin switch lowering functions. 337 bool emitJumpTableHeader(SwitchCG::JumpTable &JT, 338 SwitchCG::JumpTableHeader &JTH, 339 MachineBasicBlock *HeaderBB); 340 void emitJumpTable(SwitchCG::JumpTable &JT, MachineBasicBlock *MBB); 341 342 void emitSwitchCase(SwitchCG::CaseBlock &CB, MachineBasicBlock *SwitchBB, 343 MachineIRBuilder &MIB); 344 345 /// Generate for for the BitTest header block, which precedes each sequence of 346 /// BitTestCases. 347 void emitBitTestHeader(SwitchCG::BitTestBlock &BTB, 348 MachineBasicBlock *SwitchMBB); 349 /// Generate code to produces one "bit test" for a given BitTestCase \p B. 350 void emitBitTestCase(SwitchCG::BitTestBlock &BB, MachineBasicBlock *NextMBB, 351 BranchProbability BranchProbToNext, Register Reg, 352 SwitchCG::BitTestCase &B, MachineBasicBlock *SwitchBB); 353 354 bool lowerJumpTableWorkItem( 355 SwitchCG::SwitchWorkListItem W, MachineBasicBlock *SwitchMBB, 356 MachineBasicBlock *CurMBB, MachineBasicBlock *DefaultMBB, 357 MachineIRBuilder &MIB, MachineFunction::iterator BBI, 358 BranchProbability UnhandledProbs, SwitchCG::CaseClusterIt I, 359 MachineBasicBlock *Fallthrough, bool FallthroughUnreachable); 360 361 bool lowerSwitchRangeWorkItem(SwitchCG::CaseClusterIt I, Value *Cond, 362 MachineBasicBlock *Fallthrough, 363 bool FallthroughUnreachable, 364 BranchProbability UnhandledProbs, 365 MachineBasicBlock *CurMBB, 366 MachineIRBuilder &MIB, 367 MachineBasicBlock *SwitchMBB); 368 369 bool lowerBitTestWorkItem( 370 SwitchCG::SwitchWorkListItem W, MachineBasicBlock *SwitchMBB, 371 MachineBasicBlock *CurMBB, MachineBasicBlock *DefaultMBB, 372 MachineIRBuilder &MIB, MachineFunction::iterator BBI, 373 BranchProbability DefaultProb, BranchProbability UnhandledProbs, 374 SwitchCG::CaseClusterIt I, MachineBasicBlock *Fallthrough, 375 bool FallthroughUnreachable); 376 377 bool lowerSwitchWorkItem(SwitchCG::SwitchWorkListItem W, Value *Cond, 378 MachineBasicBlock *SwitchMBB, 379 MachineBasicBlock *DefaultMBB, 380 MachineIRBuilder &MIB); 381 382 bool translateSwitch(const User &U, MachineIRBuilder &MIRBuilder); 383 // End switch lowering section. 384 385 bool translateIndirectBr(const User &U, MachineIRBuilder &MIRBuilder); 386 387 bool translateExtractValue(const User &U, MachineIRBuilder &MIRBuilder); 388 389 bool translateInsertValue(const User &U, MachineIRBuilder &MIRBuilder); 390 391 bool translateSelect(const User &U, MachineIRBuilder &MIRBuilder); 392 393 bool translateGetElementPtr(const User &U, MachineIRBuilder &MIRBuilder); 394 395 bool translateAlloca(const User &U, MachineIRBuilder &MIRBuilder); 396 397 /// Translate return (ret) instruction. 398 /// The target needs to implement CallLowering::lowerReturn for 399 /// this to succeed. 400 /// \pre \p U is a return instruction. 401 bool translateRet(const User &U, MachineIRBuilder &MIRBuilder); 402 403 bool translateFNeg(const User &U, MachineIRBuilder &MIRBuilder); 404 405 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { 406 return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder); 407 } 408 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { 409 return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder); 410 } 411 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { 412 return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder); 413 } 414 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { 415 return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder); 416 } 417 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { 418 return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder); 419 } 420 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { 421 return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder); 422 } 423 424 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { 425 return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder); 426 } 427 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { 428 return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder); 429 } 430 bool translateURem(const User &U, MachineIRBuilder &MIRBuilder) { 431 return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder); 432 } 433 bool translateSRem(const User &U, MachineIRBuilder &MIRBuilder) { 434 return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder); 435 } 436 bool translateIntToPtr(const User &U, MachineIRBuilder &MIRBuilder) { 437 return translateCast(TargetOpcode::G_INTTOPTR, U, MIRBuilder); 438 } 439 bool translatePtrToInt(const User &U, MachineIRBuilder &MIRBuilder) { 440 return translateCast(TargetOpcode::G_PTRTOINT, U, MIRBuilder); 441 } 442 bool translateTrunc(const User &U, MachineIRBuilder &MIRBuilder) { 443 return translateCast(TargetOpcode::G_TRUNC, U, MIRBuilder); 444 } 445 bool translateFPTrunc(const User &U, MachineIRBuilder &MIRBuilder) { 446 return translateCast(TargetOpcode::G_FPTRUNC, U, MIRBuilder); 447 } 448 bool translateFPExt(const User &U, MachineIRBuilder &MIRBuilder) { 449 return translateCast(TargetOpcode::G_FPEXT, U, MIRBuilder); 450 } 451 bool translateFPToUI(const User &U, MachineIRBuilder &MIRBuilder) { 452 return translateCast(TargetOpcode::G_FPTOUI, U, MIRBuilder); 453 } 454 bool translateFPToSI(const User &U, MachineIRBuilder &MIRBuilder) { 455 return translateCast(TargetOpcode::G_FPTOSI, U, MIRBuilder); 456 } 457 bool translateUIToFP(const User &U, MachineIRBuilder &MIRBuilder) { 458 return translateCast(TargetOpcode::G_UITOFP, U, MIRBuilder); 459 } 460 bool translateSIToFP(const User &U, MachineIRBuilder &MIRBuilder) { 461 return translateCast(TargetOpcode::G_SITOFP, U, MIRBuilder); 462 } 463 bool translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder); 464 465 bool translateSExt(const User &U, MachineIRBuilder &MIRBuilder) { 466 return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder); 467 } 468 469 bool translateZExt(const User &U, MachineIRBuilder &MIRBuilder) { 470 return translateCast(TargetOpcode::G_ZEXT, U, MIRBuilder); 471 } 472 473 bool translateShl(const User &U, MachineIRBuilder &MIRBuilder) { 474 return translateBinaryOp(TargetOpcode::G_SHL, U, MIRBuilder); 475 } 476 bool translateLShr(const User &U, MachineIRBuilder &MIRBuilder) { 477 return translateBinaryOp(TargetOpcode::G_LSHR, U, MIRBuilder); 478 } 479 bool translateAShr(const User &U, MachineIRBuilder &MIRBuilder) { 480 return translateBinaryOp(TargetOpcode::G_ASHR, U, MIRBuilder); 481 } 482 483 bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) { 484 return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder); 485 } 486 bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder) { 487 return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder); 488 } 489 bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) { 490 return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder); 491 } 492 bool translateFDiv(const User &U, MachineIRBuilder &MIRBuilder) { 493 return translateBinaryOp(TargetOpcode::G_FDIV, U, MIRBuilder); 494 } 495 bool translateFRem(const User &U, MachineIRBuilder &MIRBuilder) { 496 return translateBinaryOp(TargetOpcode::G_FREM, U, MIRBuilder); 497 } 498 499 bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder); 500 501 bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder); 502 503 bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder); 504 505 bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder); 506 507 bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder); 508 bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder); 509 bool translateFence(const User &U, MachineIRBuilder &MIRBuilder); 510 bool translateFreeze(const User &U, MachineIRBuilder &MIRBuilder); 511 512 // Stubs to keep the compiler happy while we implement the rest of the 513 // translation. 514 bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) { 515 return false; 516 } 517 bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) { 518 return false; 519 } 520 bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) { 521 return false; 522 } 523 bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) { 524 return false; 525 } 526 bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) { 527 return translateCast(TargetOpcode::G_ADDRSPACE_CAST, U, MIRBuilder); 528 } 529 bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) { 530 return false; 531 } 532 bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) { 533 return false; 534 } 535 bool translateUserOp1(const User &U, MachineIRBuilder &MIRBuilder) { 536 return false; 537 } 538 bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) { 539 return false; 540 } 541 542 /// @} 543 544 // Builder for machine instruction a la IRBuilder. 545 // I.e., compared to regular MIBuilder, this one also inserts the instruction 546 // in the current block, it can creates block, etc., basically a kind of 547 // IRBuilder, but for Machine IR. 548 // CSEMIRBuilder CurBuilder; 549 std::unique_ptr<MachineIRBuilder> CurBuilder; 550 551 // Builder set to the entry block (just after ABI lowering instructions). Used 552 // as a convenient location for Constants. 553 // CSEMIRBuilder EntryBuilder; 554 std::unique_ptr<MachineIRBuilder> EntryBuilder; 555 556 // The MachineFunction currently being translated. 557 MachineFunction *MF; 558 559 /// MachineRegisterInfo used to create virtual registers. 560 MachineRegisterInfo *MRI = nullptr; 561 562 const DataLayout *DL; 563 564 /// Current target configuration. Controls how the pass handles errors. 565 const TargetPassConfig *TPC; 566 567 CodeGenOpt::Level OptLevel; 568 569 /// Current optimization remark emitter. Used to report failures. 570 std::unique_ptr<OptimizationRemarkEmitter> ORE; 571 572 AAResults *AA; 573 FunctionLoweringInfo FuncInfo; 574 575 // True when either the Target Machine specifies no optimizations or the 576 // function has the optnone attribute. 577 bool EnableOpts = false; 578 579 /// True when the block contains a tail call. This allows the IRTranslator to 580 /// stop translating such blocks early. 581 bool HasTailCall = false; 582 583 StackProtectorDescriptor SPDescriptor; 584 585 /// Switch analysis and optimization. 586 class GISelSwitchLowering : public SwitchCG::SwitchLowering { 587 public: 588 GISelSwitchLowering(IRTranslator *irt, FunctionLoweringInfo &funcinfo) 589 : SwitchLowering(funcinfo), IRT(irt) { 590 assert(irt && "irt is null!"); 591 } 592 593 void addSuccessorWithProb( 594 MachineBasicBlock *Src, MachineBasicBlock *Dst, 595 BranchProbability Prob = BranchProbability::getUnknown()) override { 596 IRT->addSuccessorWithProb(Src, Dst, Prob); 597 } 598 599 virtual ~GISelSwitchLowering() = default; 600 601 private: 602 IRTranslator *IRT; 603 }; 604 605 std::unique_ptr<GISelSwitchLowering> SL; 606 607 // * Insert all the code needed to materialize the constants 608 // at the proper place. E.g., Entry block or dominator block 609 // of each constant depending on how fancy we want to be. 610 // * Clear the different maps. 611 void finalizeFunction(); 612 613 // Processing steps done per block. E.g. emitting jump tables, stack 614 // protectors etc. Returns true if no errors, false if there was a problem 615 // that caused an abort. 616 bool finalizeBasicBlock(const BasicBlock &BB, MachineBasicBlock &MBB); 617 618 /// Codegen a new tail for a stack protector check ParentMBB which has had its 619 /// tail spliced into a stack protector check success bb. 620 /// 621 /// For a high level explanation of how this fits into the stack protector 622 /// generation see the comment on the declaration of class 623 /// StackProtectorDescriptor. 624 /// 625 /// \return true if there were no problems. 626 bool emitSPDescriptorParent(StackProtectorDescriptor &SPD, 627 MachineBasicBlock *ParentBB); 628 629 /// Codegen the failure basic block for a stack protector check. 630 /// 631 /// A failure stack protector machine basic block consists simply of a call to 632 /// __stack_chk_fail(). 633 /// 634 /// For a high level explanation of how this fits into the stack protector 635 /// generation see the comment on the declaration of class 636 /// StackProtectorDescriptor. 637 /// 638 /// \return true if there were no problems. 639 bool emitSPDescriptorFailure(StackProtectorDescriptor &SPD, 640 MachineBasicBlock *FailureBB); 641 642 /// Get the VRegs that represent \p Val. 643 /// Non-aggregate types have just one corresponding VReg and the list can be 644 /// used as a single "unsigned". Aggregates get flattened. If such VRegs do 645 /// not exist, they are created. 646 ArrayRef<Register> getOrCreateVRegs(const Value &Val); 647 648 Register getOrCreateVReg(const Value &Val) { 649 auto Regs = getOrCreateVRegs(Val); 650 if (Regs.empty()) 651 return 0; 652 assert(Regs.size() == 1 && 653 "attempt to get single VReg for aggregate or void"); 654 return Regs[0]; 655 } 656 657 /// Allocate some vregs and offsets in the VMap. Then populate just the 658 /// offsets while leaving the vregs empty. 659 ValueToVRegInfo::VRegListT &allocateVRegs(const Value &Val); 660 661 /// Get the frame index that represents \p Val. 662 /// If such VReg does not exist, it is created. 663 int getOrCreateFrameIndex(const AllocaInst &AI); 664 665 /// Get the alignment of the given memory operation instruction. This will 666 /// either be the explicitly specified value or the ABI-required alignment for 667 /// the type being accessed (according to the Module's DataLayout). 668 Align getMemOpAlign(const Instruction &I); 669 670 /// Get the MachineBasicBlock that represents \p BB. Specifically, the block 671 /// returned will be the head of the translated block (suitable for branch 672 /// destinations). 673 MachineBasicBlock &getMBB(const BasicBlock &BB); 674 675 /// Record \p NewPred as a Machine predecessor to `Edge.second`, corresponding 676 /// to `Edge.first` at the IR level. This is used when IRTranslation creates 677 /// multiple MachineBasicBlocks for a given IR block and the CFG is no longer 678 /// represented simply by the IR-level CFG. 679 void addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred); 680 681 /// Returns the Machine IR predecessors for the given IR CFG edge. Usually 682 /// this is just the single MachineBasicBlock corresponding to the predecessor 683 /// in the IR. More complex lowering can result in multiple MachineBasicBlocks 684 /// preceding the original though (e.g. switch instructions). 685 SmallVector<MachineBasicBlock *, 1> getMachinePredBBs(CFGEdge Edge) { 686 auto RemappedEdge = MachinePreds.find(Edge); 687 if (RemappedEdge != MachinePreds.end()) 688 return RemappedEdge->second; 689 return SmallVector<MachineBasicBlock *, 4>(1, &getMBB(*Edge.first)); 690 } 691 692 /// Return branch probability calculated by BranchProbabilityInfo for IR 693 /// blocks. 694 BranchProbability getEdgeProbability(const MachineBasicBlock *Src, 695 const MachineBasicBlock *Dst) const; 696 697 void addSuccessorWithProb( 698 MachineBasicBlock *Src, MachineBasicBlock *Dst, 699 BranchProbability Prob = BranchProbability::getUnknown()); 700 701 public: 702 IRTranslator(CodeGenOpt::Level OptLevel = CodeGenOpt::None); 703 704 StringRef getPassName() const override { return "IRTranslator"; } 705 706 void getAnalysisUsage(AnalysisUsage &AU) const override; 707 708 // Algo: 709 // CallLowering = MF.subtarget.getCallLowering() 710 // F = MF.getParent() 711 // MIRBuilder.reset(MF) 712 // getMBB(F.getEntryBB()) 713 // CallLowering->translateArguments(MIRBuilder, F, ValToVReg) 714 // for each bb in F 715 // getMBB(bb) 716 // for each inst in bb 717 // if (!translate(MIRBuilder, inst, ValToVReg, ConstantToSequence)) 718 // report_fatal_error("Don't know how to translate input"); 719 // finalize() 720 bool runOnMachineFunction(MachineFunction &MF) override; 721 }; 722 723 } // end namespace llvm 724 725 #endif // LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H 726