1 //== llvm/CodeGen/GlobalISel/LoadStoreOpt.h - LoadStoreOpt -------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// This is an optimization pass for GlobalISel generic memory operations. 10 /// Specifically, it focuses on merging stores and loads to consecutive 11 /// addresses. 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_GLOBALISEL_LOADSTOREOPT_H 15 #define LLVM_CODEGEN_GLOBALISEL_LOADSTOREOPT_H 16 17 #include "llvm/ADT/BitVector.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/Analysis/AliasAnalysis.h" 20 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineFunctionPass.h" 23 24 namespace llvm { 25 // Forward declarations. 26 class AnalysisUsage; 27 class GStore; 28 class LegalizerInfo; 29 class MachineBasicBlock; 30 class MachineInstr; 31 class TargetLowering; 32 struct LegalityQuery; 33 class MachineRegisterInfo; 34 namespace GISelAddressing { 35 /// Helper struct to store a base, index and offset that forms an address 36 struct BaseIndexOffset { 37 Register BaseReg; 38 Register IndexReg; 39 int64_t Offset = 0; 40 bool IsIndexSignExt = false; 41 }; 42 43 /// Returns a BaseIndexOffset which describes the pointer in \p Ptr. 44 BaseIndexOffset getPointerInfo(Register Ptr, MachineRegisterInfo &MRI); 45 46 /// Compute whether or not a memory access at \p MI1 aliases with an access at 47 /// \p MI2 \returns true if either alias/no-alias is known. Sets \p IsAlias 48 /// accordingly. 49 bool aliasIsKnownForLoadStore(const MachineInstr &MI1, const MachineInstr &MI2, 50 bool &IsAlias, MachineRegisterInfo &MRI); 51 52 /// Returns true if the instruction \p MI may alias \p Other. 53 /// This function uses multiple strategies to detect aliasing, whereas 54 /// aliasIsKnownForLoadStore just looks at the addresses of load/stores and is 55 /// tries to reason about base/index/offsets. 56 bool instMayAlias(const MachineInstr &MI, const MachineInstr &Other, 57 MachineRegisterInfo &MRI, AliasAnalysis *AA); 58 } // namespace GISelAddressing 59 60 using namespace GISelAddressing; 61 62 class LoadStoreOpt : public MachineFunctionPass { 63 public: 64 static char ID; 65 66 private: 67 /// An input function to decide if the pass should run or not 68 /// on the given MachineFunction. 69 std::function<bool(const MachineFunction &)> DoNotRunPass; 70 71 MachineRegisterInfo *MRI; 72 const TargetLowering *TLI; 73 MachineFunction *MF; 74 AliasAnalysis *AA; 75 const LegalizerInfo *LI; 76 77 MachineIRBuilder Builder; 78 79 /// Initialize the field members using \p MF. 80 void init(MachineFunction &MF); 81 82 class StoreMergeCandidate { 83 public: 84 // The base pointer used as the base for all stores in this candidate. 85 Register BasePtr; 86 // Our algorithm is very simple at the moment. We assume that in instruction 87 // order stores are writing to incremeneting consecutive addresses. So when 88 // we walk the block in reverse order, the next eligible store must write to 89 // an offset one store width lower than CurrentLowestOffset. 90 uint64_t CurrentLowestOffset; 91 SmallVector<GStore *> Stores; 92 // A vector of MachineInstr/unsigned pairs to denote potential aliases that 93 // need to be checked before the candidate is considered safe to merge. The 94 // unsigned value is an index into the Stores vector. The indexed store is 95 // the highest-indexed store that has already been checked to not have an 96 // alias with the instruction. We record this so we don't have to repeat 97 // alias checks that have been already done, only those with stores added 98 // after the potential alias is recorded. 99 SmallVector<std::pair<MachineInstr *, unsigned>> PotentialAliases; 100 101 void addPotentialAlias(MachineInstr &MI); 102 103 /// Reset this candidate back to an empty one. 104 void reset() { 105 Stores.clear(); 106 PotentialAliases.clear(); 107 CurrentLowestOffset = 0; 108 BasePtr = Register(); 109 } 110 }; 111 112 bool isLegalOrBeforeLegalizer(const LegalityQuery &Query, 113 MachineFunction &MF) const; 114 /// If the given store is valid to be a member of the candidate, add it and 115 /// return true. Otherwise, returns false. 116 bool addStoreToCandidate(GStore &MI, StoreMergeCandidate &C); 117 /// Returns true if the instruction \p MI would potentially alias with any 118 /// stores in the candidate \p C. 119 bool operationAliasesWithCandidate(MachineInstr &MI, StoreMergeCandidate &C); 120 /// Merges the stores in the given vector into a wide store. 121 /// \p returns true if at least some of the stores were merged. 122 /// This may decide not to merge stores if heuristics predict it will not be 123 /// worth it. 124 bool mergeStores(SmallVectorImpl<GStore *> &StoresToMerge); 125 /// Perform a merge of all the stores in \p Stores into a single store. 126 /// Erases the old stores from the block when finished. 127 /// \returns true if merging was done. It may fail to perform a merge if 128 /// there are issues with materializing legal wide values. 129 bool doSingleStoreMerge(SmallVectorImpl<GStore *> &Stores); 130 bool processMergeCandidate(StoreMergeCandidate &C); 131 bool mergeBlockStores(MachineBasicBlock &MBB); 132 bool mergeFunctionStores(MachineFunction &MF); 133 134 /// Initialize some target-specific data structures for the store merging 135 /// optimization. \p AddrSpace indicates which address space to use when 136 /// probing the legalizer info for legal stores. 137 void initializeStoreMergeTargetInfo(unsigned AddrSpace = 0); 138 /// A map between address space numbers and a bitvector of supported stores 139 /// sizes. Each bit in the bitvector represents whether a store size of 140 /// that bit's value is legal. E.g. if bit 64 is set, then 64 bit scalar 141 /// stores are legal. 142 DenseMap<unsigned, BitVector> LegalStoreSizes; 143 bool IsPreLegalizer; 144 /// Contains instructions to be erased at the end of a block scan. 145 SmallSet<MachineInstr *, 16> InstsToErase; 146 147 public: 148 LoadStoreOpt(); 149 LoadStoreOpt(std::function<bool(const MachineFunction &)>); 150 151 StringRef getPassName() const override { return "LoadStoreOpt"; } 152 153 MachineFunctionProperties getRequiredProperties() const override { 154 return MachineFunctionProperties() 155 .set(MachineFunctionProperties::Property::IsSSA); 156 } 157 158 void getAnalysisUsage(AnalysisUsage &AU) const override; 159 160 bool runOnMachineFunction(MachineFunction &MF) override; 161 }; 162 163 } // End namespace llvm. 164 165 #endif 166