1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the MachineIRBuilder class. 10 /// This is a helper class to build MachineInstr. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H 14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H 15 16 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/TargetOpcodes.h" 21 #include "llvm/IR/DebugLoc.h" 22 #include "llvm/IR/Module.h" 23 24 namespace llvm { 25 26 // Forward declarations. 27 class APInt; 28 class BlockAddress; 29 class Constant; 30 class ConstantFP; 31 class ConstantInt; 32 class DataLayout; 33 class GISelCSEInfo; 34 class GlobalValue; 35 class TargetRegisterClass; 36 class MachineFunction; 37 class MachineInstr; 38 class TargetInstrInfo; 39 class GISelChangeObserver; 40 41 /// Class which stores all the state required in a MachineIRBuilder. 42 /// Since MachineIRBuilders will only store state in this object, it allows 43 /// to transfer BuilderState between different kinds of MachineIRBuilders. 44 struct MachineIRBuilderState { 45 /// MachineFunction under construction. 46 MachineFunction *MF = nullptr; 47 /// Information used to access the description of the opcodes. 48 const TargetInstrInfo *TII = nullptr; 49 /// Information used to verify types are consistent and to create virtual registers. 50 MachineRegisterInfo *MRI = nullptr; 51 /// Debug location to be set to any instruction we create. 52 DebugLoc DL; 53 54 /// \name Fields describing the insertion point. 55 /// @{ 56 MachineBasicBlock *MBB = nullptr; 57 MachineBasicBlock::iterator II; 58 /// @} 59 60 GISelChangeObserver *Observer = nullptr; 61 62 GISelCSEInfo *CSEInfo = nullptr; 63 }; 64 65 class DstOp { 66 union { 67 LLT LLTTy; 68 Register Reg; 69 const TargetRegisterClass *RC; 70 }; 71 72 public: 73 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC }; 74 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} 75 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} 76 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {} 77 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {} 78 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} 79 80 void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const { 81 switch (Ty) { 82 case DstType::Ty_Reg: 83 MIB.addDef(Reg); 84 break; 85 case DstType::Ty_LLT: 86 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy)); 87 break; 88 case DstType::Ty_RC: 89 MIB.addDef(MRI.createVirtualRegister(RC)); 90 break; 91 } 92 } 93 94 LLT getLLTTy(const MachineRegisterInfo &MRI) const { 95 switch (Ty) { 96 case DstType::Ty_RC: 97 return LLT{}; 98 case DstType::Ty_LLT: 99 return LLTTy; 100 case DstType::Ty_Reg: 101 return MRI.getType(Reg); 102 } 103 llvm_unreachable("Unrecognised DstOp::DstType enum"); 104 } 105 106 Register getReg() const { 107 assert(Ty == DstType::Ty_Reg && "Not a register"); 108 return Reg; 109 } 110 111 const TargetRegisterClass *getRegClass() const { 112 switch (Ty) { 113 case DstType::Ty_RC: 114 return RC; 115 default: 116 llvm_unreachable("Not a RC Operand"); 117 } 118 } 119 120 DstType getDstOpKind() const { return Ty; } 121 122 private: 123 DstType Ty; 124 }; 125 126 class SrcOp { 127 union { 128 MachineInstrBuilder SrcMIB; 129 Register Reg; 130 CmpInst::Predicate Pred; 131 int64_t Imm; 132 }; 133 134 public: 135 enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate, Ty_Imm }; 136 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} 137 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} 138 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} 139 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} 140 /// Use of registers held in unsigned integer variables (or more rarely signed 141 /// integers) is no longer permitted to avoid ambiguity with upcoming support 142 /// for immediates. 143 SrcOp(unsigned) = delete; 144 SrcOp(int) = delete; 145 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} 146 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} 147 148 void addSrcToMIB(MachineInstrBuilder &MIB) const { 149 switch (Ty) { 150 case SrcType::Ty_Predicate: 151 MIB.addPredicate(Pred); 152 break; 153 case SrcType::Ty_Reg: 154 MIB.addUse(Reg); 155 break; 156 case SrcType::Ty_MIB: 157 MIB.addUse(SrcMIB->getOperand(0).getReg()); 158 break; 159 case SrcType::Ty_Imm: 160 MIB.addImm(Imm); 161 break; 162 } 163 } 164 165 LLT getLLTTy(const MachineRegisterInfo &MRI) const { 166 switch (Ty) { 167 case SrcType::Ty_Predicate: 168 case SrcType::Ty_Imm: 169 llvm_unreachable("Not a register operand"); 170 case SrcType::Ty_Reg: 171 return MRI.getType(Reg); 172 case SrcType::Ty_MIB: 173 return MRI.getType(SrcMIB->getOperand(0).getReg()); 174 } 175 llvm_unreachable("Unrecognised SrcOp::SrcType enum"); 176 } 177 178 Register getReg() const { 179 switch (Ty) { 180 case SrcType::Ty_Predicate: 181 case SrcType::Ty_Imm: 182 llvm_unreachable("Not a register operand"); 183 case SrcType::Ty_Reg: 184 return Reg; 185 case SrcType::Ty_MIB: 186 return SrcMIB->getOperand(0).getReg(); 187 } 188 llvm_unreachable("Unrecognised SrcOp::SrcType enum"); 189 } 190 191 CmpInst::Predicate getPredicate() const { 192 switch (Ty) { 193 case SrcType::Ty_Predicate: 194 return Pred; 195 default: 196 llvm_unreachable("Not a register operand"); 197 } 198 } 199 200 int64_t getImm() const { 201 switch (Ty) { 202 case SrcType::Ty_Imm: 203 return Imm; 204 default: 205 llvm_unreachable("Not an immediate"); 206 } 207 } 208 209 SrcType getSrcOpKind() const { return Ty; } 210 211 private: 212 SrcType Ty; 213 }; 214 215 /// Helper class to build MachineInstr. 216 /// It keeps internally the insertion point and debug location for all 217 /// the new instructions we want to create. 218 /// This information can be modify via the related setters. 219 class MachineIRBuilder { 220 221 MachineIRBuilderState State; 222 223 protected: 224 void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend); 225 226 void validateUnaryOp(const LLT Res, const LLT Op0); 227 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1); 228 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1); 229 230 void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, 231 const LLT Op1Ty); 232 233 void recordInsertion(MachineInstr *InsertedInstr) const { 234 if (State.Observer) 235 State.Observer->createdInstr(*InsertedInstr); 236 } 237 238 public: 239 /// Some constructors for easy use. 240 MachineIRBuilder() = default; 241 MachineIRBuilder(MachineFunction &MF) { setMF(MF); } 242 243 MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt) { 244 setMF(*MBB.getParent()); 245 setInsertPt(MBB, InsPt); 246 } 247 248 MachineIRBuilder(MachineInstr &MI) : 249 MachineIRBuilder(*MI.getParent(), MI.getIterator()) { 250 setInstr(MI); 251 setDebugLoc(MI.getDebugLoc()); 252 } 253 254 MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer) : 255 MachineIRBuilder(MI) { 256 setChangeObserver(Observer); 257 } 258 259 virtual ~MachineIRBuilder() = default; 260 261 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {} 262 263 const TargetInstrInfo &getTII() { 264 assert(State.TII && "TargetInstrInfo is not set"); 265 return *State.TII; 266 } 267 268 /// Getter for the function we currently build. 269 MachineFunction &getMF() { 270 assert(State.MF && "MachineFunction is not set"); 271 return *State.MF; 272 } 273 274 const MachineFunction &getMF() const { 275 assert(State.MF && "MachineFunction is not set"); 276 return *State.MF; 277 } 278 279 const DataLayout &getDataLayout() const { 280 return getMF().getFunction().getParent()->getDataLayout(); 281 } 282 283 /// Getter for DebugLoc 284 const DebugLoc &getDL() { return State.DL; } 285 286 /// Getter for MRI 287 MachineRegisterInfo *getMRI() { return State.MRI; } 288 const MachineRegisterInfo *getMRI() const { return State.MRI; } 289 290 /// Getter for the State 291 MachineIRBuilderState &getState() { return State; } 292 293 /// Getter for the basic block we currently build. 294 const MachineBasicBlock &getMBB() const { 295 assert(State.MBB && "MachineBasicBlock is not set"); 296 return *State.MBB; 297 } 298 299 MachineBasicBlock &getMBB() { 300 return const_cast<MachineBasicBlock &>( 301 const_cast<const MachineIRBuilder *>(this)->getMBB()); 302 } 303 304 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; } 305 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; } 306 307 /// Current insertion point for new instructions. 308 MachineBasicBlock::iterator getInsertPt() { return State.II; } 309 310 /// Set the insertion point before the specified position. 311 /// \pre MBB must be in getMF(). 312 /// \pre II must be a valid iterator in MBB. 313 void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II) { 314 assert(MBB.getParent() == &getMF() && 315 "Basic block is in a different function"); 316 State.MBB = &MBB; 317 State.II = II; 318 } 319 320 /// @} 321 322 void setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; } 323 324 /// \name Setters for the insertion point. 325 /// @{ 326 /// Set the MachineFunction where to build instructions. 327 void setMF(MachineFunction &MF); 328 329 /// Set the insertion point to the end of \p MBB. 330 /// \pre \p MBB must be contained by getMF(). 331 void setMBB(MachineBasicBlock &MBB) { 332 State.MBB = &MBB; 333 State.II = MBB.end(); 334 assert(&getMF() == MBB.getParent() && 335 "Basic block is in a different function"); 336 } 337 338 /// Set the insertion point to before MI. 339 /// \pre MI must be in getMF(). 340 void setInstr(MachineInstr &MI) { 341 assert(MI.getParent() && "Instruction is not part of a basic block"); 342 setMBB(*MI.getParent()); 343 State.II = MI.getIterator(); 344 } 345 /// @} 346 347 /// Set the insertion point to before MI, and set the debug loc to MI's loc. 348 /// \pre MI must be in getMF(). 349 void setInstrAndDebugLoc(MachineInstr &MI) { 350 setInstr(MI); 351 setDebugLoc(MI.getDebugLoc()); 352 } 353 354 void setChangeObserver(GISelChangeObserver &Observer) { 355 State.Observer = &Observer; 356 } 357 358 void stopObservingChanges() { State.Observer = nullptr; } 359 /// @} 360 361 /// Set the debug location to \p DL for all the next build instructions. 362 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; } 363 364 /// Get the current instruction's debug location. 365 const DebugLoc &getDebugLoc() { return State.DL; } 366 367 /// Build and insert <empty> = \p Opcode <empty>. 368 /// The insertion point is the one set by the last call of either 369 /// setBasicBlock or setMI. 370 /// 371 /// \pre setBasicBlock or setMI must have been called. 372 /// 373 /// \return a MachineInstrBuilder for the newly created instruction. 374 MachineInstrBuilder buildInstr(unsigned Opcode) { 375 return insertInstr(buildInstrNoInsert(Opcode)); 376 } 377 378 /// Build but don't insert <empty> = \p Opcode <empty>. 379 /// 380 /// \pre setMF, setBasicBlock or setMI must have been called. 381 /// 382 /// \return a MachineInstrBuilder for the newly created instruction. 383 MachineInstrBuilder buildInstrNoInsert(unsigned Opcode); 384 385 /// Insert an existing instruction at the insertion point. 386 MachineInstrBuilder insertInstr(MachineInstrBuilder MIB); 387 388 /// Build and insert a DBG_VALUE instruction expressing the fact that the 389 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr). 390 MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, 391 const MDNode *Expr); 392 393 /// Build and insert a DBG_VALUE instruction expressing the fact that the 394 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p 395 /// Expr). 396 MachineInstrBuilder buildIndirectDbgValue(Register Reg, 397 const MDNode *Variable, 398 const MDNode *Expr); 399 400 /// Build and insert a DBG_VALUE instruction expressing the fact that the 401 /// associated \p Variable lives in the stack slot specified by \p FI 402 /// (suitably modified by \p Expr). 403 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, 404 const MDNode *Expr); 405 406 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is 407 /// given by \p C (suitably modified by \p Expr). 408 MachineInstrBuilder buildConstDbgValue(const Constant &C, 409 const MDNode *Variable, 410 const MDNode *Expr); 411 412 /// Build and insert a DBG_LABEL instructions specifying that \p Label is 413 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label". 414 MachineInstrBuilder buildDbgLabel(const MDNode *Label); 415 416 /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align 417 /// 418 /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of 419 /// the allocated memory into \p Res. 420 /// \pre setBasicBlock or setMI must have been called. 421 /// \pre \p Res must be a generic virtual register with pointer type. 422 /// 423 /// \return a MachineInstrBuilder for the newly created instruction. 424 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, 425 Align Alignment); 426 427 /// Build and insert \p Res = G_FRAME_INDEX \p Idx 428 /// 429 /// G_FRAME_INDEX materializes the address of an alloca value or other 430 /// stack-based object. 431 /// 432 /// \pre setBasicBlock or setMI must have been called. 433 /// \pre \p Res must be a generic virtual register with pointer type. 434 /// 435 /// \return a MachineInstrBuilder for the newly created instruction. 436 MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx); 437 438 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV 439 /// 440 /// G_GLOBAL_VALUE materializes the address of the specified global 441 /// into \p Res. 442 /// 443 /// \pre setBasicBlock or setMI must have been called. 444 /// \pre \p Res must be a generic virtual register with pointer type 445 /// in the same address space as \p GV. 446 /// 447 /// \return a MachineInstrBuilder for the newly created instruction. 448 MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV); 449 450 /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1 451 /// 452 /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0, 453 /// storing the resulting pointer in \p Res. Addressible units are typically 454 /// bytes but this can vary between targets. 455 /// 456 /// \pre setBasicBlock or setMI must have been called. 457 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer 458 /// type. 459 /// \pre \p Op1 must be a generic virtual register with scalar type. 460 /// 461 /// \return a MachineInstrBuilder for the newly created instruction. 462 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, 463 const SrcOp &Op1); 464 465 /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value) 466 /// 467 /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0, 468 /// storing the resulting pointer in \p Res. If \p Value is zero then no 469 /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to 470 /// \p Res. 471 /// 472 /// \pre setBasicBlock or setMI must have been called. 473 /// \pre \p Op0 must be a generic virtual register with pointer type. 474 /// \pre \p ValueTy must be a scalar type. 475 /// \pre \p Res must be 0. This is to detect confusion between 476 /// materializePtrAdd() and buildPtrAdd(). 477 /// \post \p Res will either be a new generic virtual register of the same 478 /// type as \p Op0 or \p Op0 itself. 479 /// 480 /// \return a MachineInstrBuilder for the newly created instruction. 481 Optional<MachineInstrBuilder> materializePtrAdd(Register &Res, Register Op0, 482 const LLT ValueTy, 483 uint64_t Value); 484 485 /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1 486 MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, 487 const SrcOp &Op1) { 488 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1}); 489 } 490 491 /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1 492 /// 493 /// This clears the low bits of a pointer operand without destroying its 494 /// pointer properties. This has the effect of rounding the address *down* to 495 /// a specified alignment in bits. 496 /// 497 /// \pre setBasicBlock or setMI must have been called. 498 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer 499 /// type. 500 /// \pre \p NumBits must be an integer representing the number of low bits to 501 /// be cleared in \p Op0. 502 /// 503 /// \return a MachineInstrBuilder for the newly created instruction. 504 MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, 505 uint32_t NumBits); 506 507 /// Build and insert 508 /// a, b, ..., x = G_UNMERGE_VALUES \p Op0 509 /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef 510 /// 511 /// Pad \p Op0 with undef elements to match number of elements in \p Res. 512 /// 513 /// \pre setBasicBlock or setMI must have been called. 514 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type, 515 /// same vector element type and Op0 must have fewer elements then Res. 516 /// 517 /// \return a MachineInstrBuilder for the newly created build vector instr. 518 MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, 519 const SrcOp &Op0); 520 521 /// Build and insert 522 /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0 523 /// \p Res = G_BUILD_VECTOR a, b, ..., x 524 /// 525 /// Delete trailing elements in \p Op0 to match number of elements in \p Res. 526 /// 527 /// \pre setBasicBlock or setMI must have been called. 528 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type, 529 /// same vector element type and Op0 must have more elements then Res. 530 /// 531 /// \return a MachineInstrBuilder for the newly created build vector instr. 532 MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, 533 const SrcOp &Op0); 534 535 /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1 536 /// 537 /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and 538 /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic. 539 /// 540 /// \pre setBasicBlock or setMI must have been called. 541 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the 542 /// same scalar type. 543 ////\pre \p CarryOut must be generic virtual register with scalar type 544 ///(typically s1) 545 /// 546 /// \return The newly created instruction. 547 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, 548 const SrcOp &Op0, const SrcOp &Op1) { 549 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1}); 550 } 551 552 /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1 553 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, 554 const SrcOp &Op0, const SrcOp &Op1) { 555 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1}); 556 } 557 558 /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1 559 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, 560 const SrcOp &Op0, const SrcOp &Op1) { 561 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1}); 562 } 563 564 /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1 565 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, 566 const SrcOp &Op0, const SrcOp &Op1) { 567 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1}); 568 } 569 570 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0, 571 /// \p Op1, \p CarryIn 572 /// 573 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit 574 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned 575 /// arithmetic. 576 /// 577 /// \pre setBasicBlock or setMI must have been called. 578 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 579 /// with the same scalar type. 580 /// \pre \p CarryOut and \p CarryIn must be generic virtual 581 /// registers with the same scalar type (typically s1) 582 /// 583 /// \return The newly created instruction. 584 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, 585 const SrcOp &Op0, const SrcOp &Op1, 586 const SrcOp &CarryIn) { 587 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, 588 {Op0, Op1, CarryIn}); 589 } 590 591 /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp 592 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, 593 const SrcOp &Op0, const SrcOp &Op1, 594 const SrcOp &CarryIn) { 595 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut}, 596 {Op0, Op1, CarryIn}); 597 } 598 599 /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp 600 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, 601 const SrcOp &Op0, const SrcOp &Op1, 602 const SrcOp &CarryIn) { 603 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut}, 604 {Op0, Op1, CarryIn}); 605 } 606 607 /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp 608 MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, 609 const SrcOp &Op0, const SrcOp &Op1, 610 const SrcOp &CarryIn) { 611 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut}, 612 {Op0, Op1, CarryIn}); 613 } 614 615 /// Build and insert \p Res = G_ANYEXT \p Op0 616 /// 617 /// G_ANYEXT produces a register of the specified width, with bits 0 to 618 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified 619 /// (i.e. this is neither zero nor sign-extension). For a vector register, 620 /// each element is extended individually. 621 /// 622 /// \pre setBasicBlock or setMI must have been called. 623 /// \pre \p Res must be a generic virtual register with scalar or vector type. 624 /// \pre \p Op must be a generic virtual register with scalar or vector type. 625 /// \pre \p Op must be smaller than \p Res 626 /// 627 /// \return The newly created instruction. 628 629 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op); 630 631 /// Build and insert \p Res = G_SEXT \p Op 632 /// 633 /// G_SEXT produces a register of the specified width, with bits 0 to 634 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the 635 /// high bit of \p Op (i.e. 2s-complement sign extended). 636 /// 637 /// \pre setBasicBlock or setMI must have been called. 638 /// \pre \p Res must be a generic virtual register with scalar or vector type. 639 /// \pre \p Op must be a generic virtual register with scalar or vector type. 640 /// \pre \p Op must be smaller than \p Res 641 /// 642 /// \return The newly created instruction. 643 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op); 644 645 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp 646 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) { 647 return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)}); 648 } 649 650 /// Build and insert \p Res = G_FPEXT \p Op 651 MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, 652 Optional<unsigned> Flags = None) { 653 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags); 654 } 655 656 657 /// Build and insert a G_PTRTOINT instruction. 658 MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) { 659 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src}); 660 } 661 662 /// Build and insert a G_INTTOPTR instruction. 663 MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) { 664 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src}); 665 } 666 667 /// Build and insert \p Dst = G_BITCAST \p Src 668 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) { 669 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src}); 670 } 671 672 /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src 673 MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src) { 674 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src}); 675 } 676 677 /// \return The opcode of the extension the target wants to use for boolean 678 /// values. 679 unsigned getBoolExtOp(bool IsVec, bool IsFP) const; 680 681 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res 682 // = G_ZEXT \p Op depending on how the target wants to extend boolean values. 683 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, 684 bool IsFP); 685 686 /// Build and insert \p Res = G_ZEXT \p Op 687 /// 688 /// G_ZEXT produces a register of the specified width, with bits 0 to 689 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector 690 /// register, each element is extended individually. 691 /// 692 /// \pre setBasicBlock or setMI must have been called. 693 /// \pre \p Res must be a generic virtual register with scalar or vector type. 694 /// \pre \p Op must be a generic virtual register with scalar or vector type. 695 /// \pre \p Op must be smaller than \p Res 696 /// 697 /// \return The newly created instruction. 698 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op); 699 700 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or 701 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. 702 /// /// 703 /// \pre setBasicBlock or setMI must have been called. 704 /// \pre \p Res must be a generic virtual register with scalar or vector type. 705 /// \pre \p Op must be a generic virtual register with scalar or vector type. 706 /// 707 /// \return The newly created instruction. 708 MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op); 709 710 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or 711 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. 712 /// /// 713 /// \pre setBasicBlock or setMI must have been called. 714 /// \pre \p Res must be a generic virtual register with scalar or vector type. 715 /// \pre \p Op must be a generic virtual register with scalar or vector type. 716 /// 717 /// \return The newly created instruction. 718 MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op); 719 720 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or 721 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. 722 /// /// 723 /// \pre setBasicBlock or setMI must have been called. 724 /// \pre \p Res must be a generic virtual register with scalar or vector type. 725 /// \pre \p Op must be a generic virtual register with scalar or vector type. 726 /// 727 /// \return The newly created instruction. 728 MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op); 729 730 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p 731 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and 732 /// \p Op. 733 /// /// 734 /// \pre setBasicBlock or setMI must have been called. 735 /// \pre \p Res must be a generic virtual register with scalar or vector type. 736 /// \pre \p Op must be a generic virtual register with scalar or vector type. 737 /// 738 /// \return The newly created instruction. 739 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, 740 const SrcOp &Op); 741 742 /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp) 743 /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is 744 /// emulated using G_AND. 745 MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, 746 int64_t ImmOp); 747 748 /// Build and insert an appropriate cast between two registers of equal size. 749 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src); 750 751 /// Build and insert G_BR \p Dest 752 /// 753 /// G_BR is an unconditional branch to \p Dest. 754 /// 755 /// \pre setBasicBlock or setMI must have been called. 756 /// 757 /// \return a MachineInstrBuilder for the newly created instruction. 758 MachineInstrBuilder buildBr(MachineBasicBlock &Dest); 759 760 /// Build and insert G_BRCOND \p Tst, \p Dest 761 /// 762 /// G_BRCOND is a conditional branch to \p Dest. 763 /// 764 /// \pre setBasicBlock or setMI must have been called. 765 /// \pre \p Tst must be a generic virtual register with scalar 766 /// type. At the beginning of legalization, this will be a single 767 /// bit (s1). Targets with interesting flags registers may change 768 /// this. For a wider type, whether the branch is taken must only 769 /// depend on bit 0 (for now). 770 /// 771 /// \return The newly created instruction. 772 MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest); 773 774 /// Build and insert G_BRINDIRECT \p Tgt 775 /// 776 /// G_BRINDIRECT is an indirect branch to \p Tgt. 777 /// 778 /// \pre setBasicBlock or setMI must have been called. 779 /// \pre \p Tgt must be a generic virtual register with pointer type. 780 /// 781 /// \return a MachineInstrBuilder for the newly created instruction. 782 MachineInstrBuilder buildBrIndirect(Register Tgt); 783 784 /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg 785 /// 786 /// G_BRJT is a jump table branch using a table base pointer \p TablePtr, 787 /// jump table index \p JTI and index \p IndexReg 788 /// 789 /// \pre setBasicBlock or setMI must have been called. 790 /// \pre \p TablePtr must be a generic virtual register with pointer type. 791 /// \pre \p JTI must be be a jump table index. 792 /// \pre \p IndexReg must be a generic virtual register with pointer type. 793 /// 794 /// \return a MachineInstrBuilder for the newly created instruction. 795 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, 796 Register IndexReg); 797 798 /// Build and insert \p Res = G_CONSTANT \p Val 799 /// 800 /// G_CONSTANT is an integer constant with the specified size and value. \p 801 /// Val will be extended or truncated to the size of \p Reg. 802 /// 803 /// \pre setBasicBlock or setMI must have been called. 804 /// \pre \p Res must be a generic virtual register with scalar or pointer 805 /// type. 806 /// 807 /// \return The newly created instruction. 808 virtual MachineInstrBuilder buildConstant(const DstOp &Res, 809 const ConstantInt &Val); 810 811 /// Build and insert \p Res = G_CONSTANT \p Val 812 /// 813 /// G_CONSTANT is an integer constant with the specified size and value. 814 /// 815 /// \pre setBasicBlock or setMI must have been called. 816 /// \pre \p Res must be a generic virtual register with scalar type. 817 /// 818 /// \return The newly created instruction. 819 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val); 820 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val); 821 822 /// Build and insert \p Res = G_FCONSTANT \p Val 823 /// 824 /// G_FCONSTANT is a floating-point constant with the specified size and 825 /// value. 826 /// 827 /// \pre setBasicBlock or setMI must have been called. 828 /// \pre \p Res must be a generic virtual register with scalar type. 829 /// 830 /// \return The newly created instruction. 831 virtual MachineInstrBuilder buildFConstant(const DstOp &Res, 832 const ConstantFP &Val); 833 834 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val); 835 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val); 836 837 /// Build and insert \p Res = COPY Op 838 /// 839 /// Register-to-register COPY sets \p Res to \p Op. 840 /// 841 /// \pre setBasicBlock or setMI must have been called. 842 /// 843 /// \return a MachineInstrBuilder for the newly created instruction. 844 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op); 845 846 847 /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN 848 /// 849 /// \return a MachineInstrBuilder for the newly created instruction. 850 MachineInstrBuilder buildAssertOp(unsigned Opc, const DstOp &Res, const SrcOp &Op, 851 unsigned Val) { 852 return buildInstr(Opc, Res, Op).addImm(Val); 853 } 854 855 /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size 856 /// 857 /// \return a MachineInstrBuilder for the newly created instruction. 858 MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, 859 unsigned Size) { 860 return buildAssertOp(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size); 861 } 862 863 /// Build and insert \p Res = G_ASSERT_SEXT Op, Size 864 /// 865 /// \return a MachineInstrBuilder for the newly created instruction. 866 MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, 867 unsigned Size) { 868 return buildAssertOp(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size); 869 } 870 871 /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal 872 /// 873 /// \return a MachineInstrBuilder for the newly created instruction. 874 MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, 875 Align AlignVal) { 876 return buildAssertOp(TargetOpcode::G_ASSERT_ALIGN, Res, Op, AlignVal.value()); 877 } 878 879 /// Build and insert `Res = G_LOAD Addr, MMO`. 880 /// 881 /// Loads the value stored at \p Addr. Puts the result in \p Res. 882 /// 883 /// \pre setBasicBlock or setMI must have been called. 884 /// \pre \p Res must be a generic virtual register. 885 /// \pre \p Addr must be a generic virtual register with pointer type. 886 /// 887 /// \return a MachineInstrBuilder for the newly created instruction. 888 MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, 889 MachineMemOperand &MMO) { 890 return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO); 891 } 892 893 /// Build and insert a G_LOAD instruction, while constructing the 894 /// MachineMemOperand. 895 MachineInstrBuilder 896 buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo, 897 Align Alignment, 898 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, 899 const AAMDNodes &AAInfo = AAMDNodes()); 900 901 /// Build and insert `Res = <opcode> Addr, MMO`. 902 /// 903 /// Loads the value stored at \p Addr. Puts the result in \p Res. 904 /// 905 /// \pre setBasicBlock or setMI must have been called. 906 /// \pre \p Res must be a generic virtual register. 907 /// \pre \p Addr must be a generic virtual register with pointer type. 908 /// 909 /// \return a MachineInstrBuilder for the newly created instruction. 910 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, 911 const SrcOp &Addr, MachineMemOperand &MMO); 912 913 /// Helper to create a load from a constant offset given a base address. Load 914 /// the type of \p Dst from \p Offset from the given base address and memory 915 /// operand. 916 MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, 917 const SrcOp &BasePtr, 918 MachineMemOperand &BaseMMO, 919 int64_t Offset); 920 921 /// Build and insert `G_STORE Val, Addr, MMO`. 922 /// 923 /// Stores the value \p Val to \p Addr. 924 /// 925 /// \pre setBasicBlock or setMI must have been called. 926 /// \pre \p Val must be a generic virtual register. 927 /// \pre \p Addr must be a generic virtual register with pointer type. 928 /// 929 /// \return a MachineInstrBuilder for the newly created instruction. 930 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, 931 MachineMemOperand &MMO); 932 933 /// Build and insert a G_STORE instruction, while constructing the 934 /// MachineMemOperand. 935 MachineInstrBuilder 936 buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo, 937 Align Alignment, 938 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, 939 const AAMDNodes &AAInfo = AAMDNodes()); 940 941 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`. 942 /// 943 /// \pre setBasicBlock or setMI must have been called. 944 /// \pre \p Res and \p Src must be generic virtual registers. 945 /// 946 /// \return a MachineInstrBuilder for the newly created instruction. 947 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index); 948 949 /// Build and insert \p Res = IMPLICIT_DEF. 950 MachineInstrBuilder buildUndef(const DstOp &Res); 951 952 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ... 953 /// 954 /// G_MERGE_VALUES combines the input elements contiguously into a larger 955 /// register. 956 /// 957 /// \pre setBasicBlock or setMI must have been called. 958 /// \pre The entire register \p Res (and no more) must be covered by the input 959 /// registers. 960 /// \pre The type of all \p Ops registers must be identical. 961 /// 962 /// \return a MachineInstrBuilder for the newly created instruction. 963 MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops); 964 MachineInstrBuilder buildMerge(const DstOp &Res, 965 std::initializer_list<SrcOp> Ops); 966 967 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op 968 /// 969 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple 970 /// 971 /// \pre setBasicBlock or setMI must have been called. 972 /// \pre The entire register \p Res (and no more) must be covered by the input 973 /// registers. 974 /// \pre The type of all \p Res registers must be identical. 975 /// 976 /// \return a MachineInstrBuilder for the newly created instruction. 977 MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op); 978 MachineInstrBuilder buildUnmerge(ArrayRef<Register> Res, const SrcOp &Op); 979 980 /// Build and insert an unmerge of \p Res sized pieces to cover \p Op 981 MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op); 982 983 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... 984 /// 985 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers. 986 /// \pre setBasicBlock or setMI must have been called. 987 /// \pre The entire register \p Res (and no more) must be covered by the 988 /// input scalar registers. 989 /// \pre The type of all \p Ops registers must be identical. 990 /// 991 /// \return a MachineInstrBuilder for the newly created instruction. 992 MachineInstrBuilder buildBuildVector(const DstOp &Res, 993 ArrayRef<Register> Ops); 994 995 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is 996 /// built with G_CONSTANT. 997 MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, 998 ArrayRef<APInt> Ops); 999 1000 /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill 1001 /// the number of elements 1002 MachineInstrBuilder buildSplatVector(const DstOp &Res, 1003 const SrcOp &Src); 1004 1005 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ... 1006 /// 1007 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers 1008 /// which have types larger than the destination vector element type, and 1009 /// truncates the values to fit. 1010 /// 1011 /// If the operands given are already the same size as the vector elt type, 1012 /// then this method will instead create a G_BUILD_VECTOR instruction. 1013 /// 1014 /// \pre setBasicBlock or setMI must have been called. 1015 /// \pre The type of all \p Ops registers must be identical. 1016 /// 1017 /// \return a MachineInstrBuilder for the newly created instruction. 1018 MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, 1019 ArrayRef<Register> Ops); 1020 1021 /// Build and insert a vector splat of a scalar \p Src using a 1022 /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom. 1023 /// 1024 /// \pre setBasicBlock or setMI must have been called. 1025 /// \pre \p Src must have the same type as the element type of \p Dst 1026 /// 1027 /// \return a MachineInstrBuilder for the newly created instruction. 1028 MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src); 1029 1030 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask 1031 /// 1032 /// \pre setBasicBlock or setMI must have been called. 1033 /// 1034 /// \return a MachineInstrBuilder for the newly created instruction. 1035 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, 1036 const SrcOp &Src2, ArrayRef<int> Mask); 1037 1038 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ... 1039 /// 1040 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more 1041 /// vectors. 1042 /// 1043 /// \pre setBasicBlock or setMI must have been called. 1044 /// \pre The entire register \p Res (and no more) must be covered by the input 1045 /// registers. 1046 /// \pre The type of all source operands must be identical. 1047 /// 1048 /// \return a MachineInstrBuilder for the newly created instruction. 1049 MachineInstrBuilder buildConcatVectors(const DstOp &Res, 1050 ArrayRef<Register> Ops); 1051 1052 MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, 1053 const SrcOp &Op, unsigned Index); 1054 1055 /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or 1056 /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the 1057 /// result register definition unless \p Reg is NoReg (== 0). The second 1058 /// operand will be the intrinsic's ID. 1059 /// 1060 /// Callers are expected to add the required definitions and uses afterwards. 1061 /// 1062 /// \pre setBasicBlock or setMI must have been called. 1063 /// 1064 /// \return a MachineInstrBuilder for the newly created instruction. 1065 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<Register> Res, 1066 bool HasSideEffects); 1067 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res, 1068 bool HasSideEffects); 1069 1070 /// Build and insert \p Res = G_FPTRUNC \p Op 1071 /// 1072 /// G_FPTRUNC converts a floating-point value into one with a smaller type. 1073 /// 1074 /// \pre setBasicBlock or setMI must have been called. 1075 /// \pre \p Res must be a generic virtual register with scalar or vector type. 1076 /// \pre \p Op must be a generic virtual register with scalar or vector type. 1077 /// \pre \p Res must be smaller than \p Op 1078 /// 1079 /// \return The newly created instruction. 1080 MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, 1081 Optional<unsigned> Flags = None); 1082 1083 /// Build and insert \p Res = G_TRUNC \p Op 1084 /// 1085 /// G_TRUNC extracts the low bits of a type. For a vector type each element is 1086 /// truncated independently before being packed into the destination. 1087 /// 1088 /// \pre setBasicBlock or setMI must have been called. 1089 /// \pre \p Res must be a generic virtual register with scalar or vector type. 1090 /// \pre \p Op must be a generic virtual register with scalar or vector type. 1091 /// \pre \p Res must be smaller than \p Op 1092 /// 1093 /// \return The newly created instruction. 1094 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op); 1095 1096 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1 1097 /// 1098 /// \pre setBasicBlock or setMI must have been called. 1099 1100 /// \pre \p Res must be a generic virtual register with scalar or 1101 /// vector type. Typically this starts as s1 or <N x s1>. 1102 /// \pre \p Op0 and Op1 must be generic virtual registers with the 1103 /// same number of elements as \p Res. If \p Res is a scalar, 1104 /// \p Op0 must be either a scalar or pointer. 1105 /// \pre \p Pred must be an integer predicate. 1106 /// 1107 /// \return a MachineInstrBuilder for the newly created instruction. 1108 MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, 1109 const SrcOp &Op0, const SrcOp &Op1); 1110 1111 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1 1112 /// 1113 /// \pre setBasicBlock or setMI must have been called. 1114 1115 /// \pre \p Res must be a generic virtual register with scalar or 1116 /// vector type. Typically this starts as s1 or <N x s1>. 1117 /// \pre \p Op0 and Op1 must be generic virtual registers with the 1118 /// same number of elements as \p Res (or scalar, if \p Res is 1119 /// scalar). 1120 /// \pre \p Pred must be a floating-point predicate. 1121 /// 1122 /// \return a MachineInstrBuilder for the newly created instruction. 1123 MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, 1124 const SrcOp &Op0, const SrcOp &Op1, 1125 Optional<unsigned> Flags = None); 1126 1127 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1 1128 /// 1129 /// \pre setBasicBlock or setMI must have been called. 1130 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1131 /// with the same type. 1132 /// \pre \p Tst must be a generic virtual register with scalar, pointer or 1133 /// vector type. If vector then it must have the same number of 1134 /// elements as the other parameters. 1135 /// 1136 /// \return a MachineInstrBuilder for the newly created instruction. 1137 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, 1138 const SrcOp &Op0, const SrcOp &Op1, 1139 Optional<unsigned> Flags = None); 1140 1141 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val, 1142 /// \p Elt, \p Idx 1143 /// 1144 /// \pre setBasicBlock or setMI must have been called. 1145 /// \pre \p Res and \p Val must be a generic virtual register 1146 // with the same vector type. 1147 /// \pre \p Elt and \p Idx must be a generic virtual register 1148 /// with scalar type. 1149 /// 1150 /// \return The newly created instruction. 1151 MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, 1152 const SrcOp &Val, 1153 const SrcOp &Elt, 1154 const SrcOp &Idx); 1155 1156 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx 1157 /// 1158 /// \pre setBasicBlock or setMI must have been called. 1159 /// \pre \p Res must be a generic virtual register with scalar type. 1160 /// \pre \p Val must be a generic virtual register with vector type. 1161 /// \pre \p Idx must be a generic virtual register with scalar type. 1162 /// 1163 /// \return The newly created instruction. 1164 MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, 1165 const SrcOp &Val, 1166 const SrcOp &Idx); 1167 1168 /// Build and insert `OldValRes<def>, SuccessRes<def> = 1169 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`. 1170 /// 1171 /// Atomically replace the value at \p Addr with \p NewVal if it is currently 1172 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p 1173 /// Addr in \p Res, along with an s1 indicating whether it was replaced. 1174 /// 1175 /// \pre setBasicBlock or setMI must have been called. 1176 /// \pre \p OldValRes must be a generic virtual register of scalar type. 1177 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It 1178 /// will be assigned 0 on failure and 1 on success. 1179 /// \pre \p Addr must be a generic virtual register with pointer type. 1180 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual 1181 /// registers of the same type. 1182 /// 1183 /// \return a MachineInstrBuilder for the newly created instruction. 1184 MachineInstrBuilder 1185 buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, 1186 Register Addr, Register CmpVal, Register NewVal, 1187 MachineMemOperand &MMO); 1188 1189 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, 1190 /// MMO`. 1191 /// 1192 /// Atomically replace the value at \p Addr with \p NewVal if it is currently 1193 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p 1194 /// Addr in \p Res. 1195 /// 1196 /// \pre setBasicBlock or setMI must have been called. 1197 /// \pre \p OldValRes must be a generic virtual register of scalar type. 1198 /// \pre \p Addr must be a generic virtual register with pointer type. 1199 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual 1200 /// registers of the same type. 1201 /// 1202 /// \return a MachineInstrBuilder for the newly created instruction. 1203 MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, 1204 Register CmpVal, Register NewVal, 1205 MachineMemOperand &MMO); 1206 1207 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`. 1208 /// 1209 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the 1210 /// original value from \p Addr in \p OldValRes. The modification is 1211 /// determined by the opcode. 1212 /// 1213 /// \pre setBasicBlock or setMI must have been called. 1214 /// \pre \p OldValRes must be a generic virtual register. 1215 /// \pre \p Addr must be a generic virtual register with pointer type. 1216 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1217 /// same type. 1218 /// 1219 /// \return a MachineInstrBuilder for the newly created instruction. 1220 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, 1221 const SrcOp &Addr, const SrcOp &Val, 1222 MachineMemOperand &MMO); 1223 1224 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`. 1225 /// 1226 /// Atomically replace the value at \p Addr with \p Val. Puts the original 1227 /// value from \p Addr in \p OldValRes. 1228 /// 1229 /// \pre setBasicBlock or setMI must have been called. 1230 /// \pre \p OldValRes must be a generic virtual register. 1231 /// \pre \p Addr must be a generic virtual register with pointer type. 1232 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1233 /// same type. 1234 /// 1235 /// \return a MachineInstrBuilder for the newly created instruction. 1236 MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, 1237 Register Val, MachineMemOperand &MMO); 1238 1239 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`. 1240 /// 1241 /// Atomically replace the value at \p Addr with the addition of \p Val and 1242 /// the original value. Puts the original value from \p Addr in \p OldValRes. 1243 /// 1244 /// \pre setBasicBlock or setMI must have been called. 1245 /// \pre \p OldValRes must be a generic virtual register. 1246 /// \pre \p Addr must be a generic virtual register with pointer type. 1247 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1248 /// same type. 1249 /// 1250 /// \return a MachineInstrBuilder for the newly created instruction. 1251 MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, 1252 Register Val, MachineMemOperand &MMO); 1253 1254 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`. 1255 /// 1256 /// Atomically replace the value at \p Addr with the subtraction of \p Val and 1257 /// the original value. Puts the original value from \p Addr in \p OldValRes. 1258 /// 1259 /// \pre setBasicBlock or setMI must have been called. 1260 /// \pre \p OldValRes must be a generic virtual register. 1261 /// \pre \p Addr must be a generic virtual register with pointer type. 1262 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1263 /// same type. 1264 /// 1265 /// \return a MachineInstrBuilder for the newly created instruction. 1266 MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, 1267 Register Val, MachineMemOperand &MMO); 1268 1269 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`. 1270 /// 1271 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and 1272 /// the original value. Puts the original value from \p Addr in \p OldValRes. 1273 /// 1274 /// \pre setBasicBlock or setMI must have been called. 1275 /// \pre \p OldValRes must be a generic virtual register. 1276 /// \pre \p Addr must be a generic virtual register with pointer type. 1277 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1278 /// same type. 1279 /// 1280 /// \return a MachineInstrBuilder for the newly created instruction. 1281 MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, 1282 Register Val, MachineMemOperand &MMO); 1283 1284 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`. 1285 /// 1286 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val 1287 /// and the original value. Puts the original value from \p Addr in \p 1288 /// OldValRes. 1289 /// 1290 /// \pre setBasicBlock or setMI must have been called. 1291 /// \pre \p OldValRes must be a generic virtual register. 1292 /// \pre \p Addr must be a generic virtual register with pointer type. 1293 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1294 /// same type. 1295 /// 1296 /// \return a MachineInstrBuilder for the newly created instruction. 1297 MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, 1298 Register Val, MachineMemOperand &MMO); 1299 1300 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`. 1301 /// 1302 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and 1303 /// the original value. Puts the original value from \p Addr in \p OldValRes. 1304 /// 1305 /// \pre setBasicBlock or setMI must have been called. 1306 /// \pre \p OldValRes must be a generic virtual register. 1307 /// \pre \p Addr must be a generic virtual register with pointer type. 1308 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1309 /// same type. 1310 /// 1311 /// \return a MachineInstrBuilder for the newly created instruction. 1312 MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, 1313 Register Val, MachineMemOperand &MMO); 1314 1315 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`. 1316 /// 1317 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and 1318 /// the original value. Puts the original value from \p Addr in \p OldValRes. 1319 /// 1320 /// \pre setBasicBlock or setMI must have been called. 1321 /// \pre \p OldValRes must be a generic virtual register. 1322 /// \pre \p Addr must be a generic virtual register with pointer type. 1323 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1324 /// same type. 1325 /// 1326 /// \return a MachineInstrBuilder for the newly created instruction. 1327 MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, 1328 Register Val, MachineMemOperand &MMO); 1329 1330 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`. 1331 /// 1332 /// Atomically replace the value at \p Addr with the signed maximum of \p 1333 /// Val and the original value. Puts the original value from \p Addr in \p 1334 /// OldValRes. 1335 /// 1336 /// \pre setBasicBlock or setMI must have been called. 1337 /// \pre \p OldValRes must be a generic virtual register. 1338 /// \pre \p Addr must be a generic virtual register with pointer type. 1339 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1340 /// same type. 1341 /// 1342 /// \return a MachineInstrBuilder for the newly created instruction. 1343 MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, 1344 Register Val, MachineMemOperand &MMO); 1345 1346 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`. 1347 /// 1348 /// Atomically replace the value at \p Addr with the signed minimum of \p 1349 /// Val and the original value. Puts the original value from \p Addr in \p 1350 /// OldValRes. 1351 /// 1352 /// \pre setBasicBlock or setMI must have been called. 1353 /// \pre \p OldValRes must be a generic virtual register. 1354 /// \pre \p Addr must be a generic virtual register with pointer type. 1355 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1356 /// same type. 1357 /// 1358 /// \return a MachineInstrBuilder for the newly created instruction. 1359 MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, 1360 Register Val, MachineMemOperand &MMO); 1361 1362 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`. 1363 /// 1364 /// Atomically replace the value at \p Addr with the unsigned maximum of \p 1365 /// Val and the original value. Puts the original value from \p Addr in \p 1366 /// OldValRes. 1367 /// 1368 /// \pre setBasicBlock or setMI must have been called. 1369 /// \pre \p OldValRes must be a generic virtual register. 1370 /// \pre \p Addr must be a generic virtual register with pointer type. 1371 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1372 /// same type. 1373 /// 1374 /// \return a MachineInstrBuilder for the newly created instruction. 1375 MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, 1376 Register Val, MachineMemOperand &MMO); 1377 1378 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`. 1379 /// 1380 /// Atomically replace the value at \p Addr with the unsigned minimum of \p 1381 /// Val and the original value. Puts the original value from \p Addr in \p 1382 /// OldValRes. 1383 /// 1384 /// \pre setBasicBlock or setMI must have been called. 1385 /// \pre \p OldValRes must be a generic virtual register. 1386 /// \pre \p Addr must be a generic virtual register with pointer type. 1387 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1388 /// same type. 1389 /// 1390 /// \return a MachineInstrBuilder for the newly created instruction. 1391 MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, 1392 Register Val, MachineMemOperand &MMO); 1393 1394 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`. 1395 MachineInstrBuilder buildAtomicRMWFAdd( 1396 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, 1397 MachineMemOperand &MMO); 1398 1399 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`. 1400 MachineInstrBuilder buildAtomicRMWFSub( 1401 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, 1402 MachineMemOperand &MMO); 1403 1404 /// Build and insert `G_FENCE Ordering, Scope`. 1405 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope); 1406 1407 /// Build and insert \p Dst = G_FREEZE \p Src 1408 MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) { 1409 return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src}); 1410 } 1411 1412 /// Build and insert \p Res = G_BLOCK_ADDR \p BA 1413 /// 1414 /// G_BLOCK_ADDR computes the address of a basic block. 1415 /// 1416 /// \pre setBasicBlock or setMI must have been called. 1417 /// \pre \p Res must be a generic virtual register of a pointer type. 1418 /// 1419 /// \return The newly created instruction. 1420 MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA); 1421 1422 /// Build and insert \p Res = G_ADD \p Op0, \p Op1 1423 /// 1424 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1, 1425 /// truncated to their width. 1426 /// 1427 /// \pre setBasicBlock or setMI must have been called. 1428 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1429 /// with the same (scalar or vector) type). 1430 /// 1431 /// \return a MachineInstrBuilder for the newly created instruction. 1432 1433 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, 1434 const SrcOp &Src1, 1435 Optional<unsigned> Flags = None) { 1436 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags); 1437 } 1438 1439 /// Build and insert \p Res = G_SUB \p Op0, \p Op1 1440 /// 1441 /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and 1442 /// \p Op1, truncated to their width. 1443 /// 1444 /// \pre setBasicBlock or setMI must have been called. 1445 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1446 /// with the same (scalar or vector) type). 1447 /// 1448 /// \return a MachineInstrBuilder for the newly created instruction. 1449 1450 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, 1451 const SrcOp &Src1, 1452 Optional<unsigned> Flags = None) { 1453 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags); 1454 } 1455 1456 /// Build and insert \p Res = G_MUL \p Op0, \p Op1 1457 /// 1458 /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1, 1459 /// truncated to their width. 1460 /// 1461 /// \pre setBasicBlock or setMI must have been called. 1462 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1463 /// with the same (scalar or vector) type). 1464 /// 1465 /// \return a MachineInstrBuilder for the newly created instruction. 1466 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, 1467 const SrcOp &Src1, 1468 Optional<unsigned> Flags = None) { 1469 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags); 1470 } 1471 1472 MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, 1473 const SrcOp &Src1, 1474 Optional<unsigned> Flags = None) { 1475 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags); 1476 } 1477 1478 MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, 1479 const SrcOp &Src1, 1480 Optional<unsigned> Flags = None) { 1481 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags); 1482 } 1483 1484 /// Build and insert \p Res = G_UREM \p Op0, \p Op1 1485 MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, 1486 const SrcOp &Src1, 1487 Optional<unsigned> Flags = None) { 1488 return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags); 1489 } 1490 1491 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, 1492 const SrcOp &Src1, 1493 Optional<unsigned> Flags = None) { 1494 return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags); 1495 } 1496 1497 MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0, 1498 const SrcOp &Src1, 1499 Optional<unsigned> Flags = None) { 1500 return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags); 1501 } 1502 1503 MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, 1504 const SrcOp &Src1, 1505 Optional<unsigned> Flags = None) { 1506 return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags); 1507 } 1508 1509 MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, 1510 const SrcOp &Src1, 1511 Optional<unsigned> Flags = None) { 1512 return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags); 1513 } 1514 1515 MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, 1516 const SrcOp &Src1, 1517 Optional<unsigned> Flags = None) { 1518 return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags); 1519 } 1520 1521 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, 1522 const SrcOp &Src1, 1523 Optional<unsigned> Flags = None) { 1524 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags); 1525 } 1526 1527 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, 1528 const SrcOp &Src1, 1529 Optional<unsigned> Flags = None) { 1530 return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags); 1531 } 1532 1533 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, 1534 const SrcOp &Src1, 1535 Optional<unsigned> Flags = None) { 1536 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags); 1537 } 1538 1539 /// Build and insert \p Res = G_AND \p Op0, \p Op1 1540 /// 1541 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p 1542 /// Op1. 1543 /// 1544 /// \pre setBasicBlock or setMI must have been called. 1545 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1546 /// with the same (scalar or vector) type). 1547 /// 1548 /// \return a MachineInstrBuilder for the newly created instruction. 1549 1550 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, 1551 const SrcOp &Src1) { 1552 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1}); 1553 } 1554 1555 /// Build and insert \p Res = G_OR \p Op0, \p Op1 1556 /// 1557 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p 1558 /// Op1. 1559 /// 1560 /// \pre setBasicBlock or setMI must have been called. 1561 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1562 /// with the same (scalar or vector) type). 1563 /// 1564 /// \return a MachineInstrBuilder for the newly created instruction. 1565 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, 1566 const SrcOp &Src1, 1567 Optional<unsigned> Flags = None) { 1568 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags); 1569 } 1570 1571 /// Build and insert \p Res = G_XOR \p Op0, \p Op1 1572 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, 1573 const SrcOp &Src1) { 1574 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1}); 1575 } 1576 1577 /// Build and insert a bitwise not, 1578 /// \p NegOne = G_CONSTANT -1 1579 /// \p Res = G_OR \p Op0, NegOne 1580 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) { 1581 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1); 1582 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne}); 1583 } 1584 1585 /// Build and insert integer negation 1586 /// \p Zero = G_CONSTANT 0 1587 /// \p Res = G_SUB Zero, \p Op0 1588 MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) { 1589 auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0); 1590 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Zero, Src0}); 1591 } 1592 1593 /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0 1594 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) { 1595 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0}); 1596 } 1597 1598 /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0 1599 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) { 1600 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0}); 1601 } 1602 1603 /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0 1604 MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { 1605 return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0}); 1606 } 1607 1608 /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0 1609 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) { 1610 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0}); 1611 } 1612 1613 /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0 1614 MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { 1615 return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0}); 1616 } 1617 1618 /// Build and insert \p Dst = G_BSWAP \p Src0 1619 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) { 1620 return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0}); 1621 } 1622 1623 /// Build and insert \p Res = G_FADD \p Op0, \p Op1 1624 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, 1625 const SrcOp &Src1, 1626 Optional<unsigned> Flags = None) { 1627 return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags); 1628 } 1629 1630 /// Build and insert \p Res = G_FSUB \p Op0, \p Op1 1631 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, 1632 const SrcOp &Src1, 1633 Optional<unsigned> Flags = None) { 1634 return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags); 1635 } 1636 1637 /// Build and insert \p Res = G_FDIV \p Op0, \p Op1 1638 MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, 1639 const SrcOp &Src1, 1640 Optional<unsigned> Flags = None) { 1641 return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags); 1642 } 1643 1644 /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2 1645 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, 1646 const SrcOp &Src1, const SrcOp &Src2, 1647 Optional<unsigned> Flags = None) { 1648 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags); 1649 } 1650 1651 /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2 1652 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, 1653 const SrcOp &Src1, const SrcOp &Src2, 1654 Optional<unsigned> Flags = None) { 1655 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags); 1656 } 1657 1658 /// Build and insert \p Res = G_FNEG \p Op0 1659 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, 1660 Optional<unsigned> Flags = None) { 1661 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags); 1662 } 1663 1664 /// Build and insert \p Res = G_FABS \p Op0 1665 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, 1666 Optional<unsigned> Flags = None) { 1667 return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags); 1668 } 1669 1670 /// Build and insert \p Dst = G_FCANONICALIZE \p Src0 1671 MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, 1672 Optional<unsigned> Flags = None) { 1673 return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags); 1674 } 1675 1676 /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0 1677 MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, 1678 Optional<unsigned> Flags = None) { 1679 return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags); 1680 } 1681 1682 /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1 1683 MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0, 1684 Optional<unsigned> Flags = None) { 1685 return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags); 1686 } 1687 1688 /// Build and insert \p Dst = G_FLOG \p Src 1689 MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, 1690 Optional<unsigned> Flags = None) { 1691 return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags); 1692 } 1693 1694 /// Build and insert \p Dst = G_FLOG2 \p Src 1695 MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, 1696 Optional<unsigned> Flags = None) { 1697 return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags); 1698 } 1699 1700 /// Build and insert \p Dst = G_FEXP2 \p Src 1701 MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, 1702 Optional<unsigned> Flags = None) { 1703 return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags); 1704 } 1705 1706 /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1 1707 MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, 1708 const SrcOp &Src1, 1709 Optional<unsigned> Flags = None) { 1710 return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags); 1711 } 1712 1713 /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1 1714 MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, 1715 const SrcOp &Src1) { 1716 return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1}); 1717 } 1718 1719 /// Build and insert \p Res = G_UITOFP \p Src0 1720 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) { 1721 return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0}); 1722 } 1723 1724 /// Build and insert \p Res = G_SITOFP \p Src0 1725 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) { 1726 return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0}); 1727 } 1728 1729 /// Build and insert \p Res = G_FPTOUI \p Src0 1730 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) { 1731 return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0}); 1732 } 1733 1734 /// Build and insert \p Res = G_FPTOSI \p Src0 1735 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) { 1736 return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0}); 1737 } 1738 1739 /// Build and insert \p Res = G_SMIN \p Op0, \p Op1 1740 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, 1741 const SrcOp &Src1) { 1742 return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1}); 1743 } 1744 1745 /// Build and insert \p Res = G_SMAX \p Op0, \p Op1 1746 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, 1747 const SrcOp &Src1) { 1748 return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1}); 1749 } 1750 1751 /// Build and insert \p Res = G_UMIN \p Op0, \p Op1 1752 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, 1753 const SrcOp &Src1) { 1754 return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1}); 1755 } 1756 1757 /// Build and insert \p Res = G_UMAX \p Op0, \p Op1 1758 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, 1759 const SrcOp &Src1) { 1760 return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1}); 1761 } 1762 1763 /// Build and insert \p Dst = G_ABS \p Src 1764 MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) { 1765 return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src}); 1766 } 1767 1768 /// Build and insert \p Res = G_JUMP_TABLE \p JTI 1769 /// 1770 /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by 1771 /// the jump table index \p JTI. 1772 /// 1773 /// \return a MachineInstrBuilder for the newly created instruction. 1774 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI); 1775 1776 /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn 1777 /// 1778 /// \p ScalarIn is the scalar accumulator input to start the sequential 1779 /// reduction operation of \p VecIn. 1780 MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, 1781 const SrcOp &ScalarIn, 1782 const SrcOp &VecIn) { 1783 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst}, 1784 {ScalarIn, {VecIn}}); 1785 } 1786 1787 /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn 1788 /// 1789 /// \p ScalarIn is the scalar accumulator input to start the sequential 1790 /// reduction operation of \p VecIn. 1791 MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, 1792 const SrcOp &ScalarIn, 1793 const SrcOp &VecIn) { 1794 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst}, 1795 {ScalarIn, {VecIn}}); 1796 } 1797 1798 /// Build and insert \p Res = G_VECREDUCE_FADD \p Src 1799 /// 1800 /// \p ScalarIn is the scalar accumulator input to the reduction operation of 1801 /// \p VecIn. 1802 MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, 1803 const SrcOp &ScalarIn, 1804 const SrcOp &VecIn) { 1805 return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn}); 1806 } 1807 1808 /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src 1809 /// 1810 /// \p ScalarIn is the scalar accumulator input to the reduction operation of 1811 /// \p VecIn. 1812 MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, 1813 const SrcOp &ScalarIn, 1814 const SrcOp &VecIn) { 1815 return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn}); 1816 } 1817 1818 /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src 1819 MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src) { 1820 return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src}); 1821 } 1822 1823 /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src 1824 MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src) { 1825 return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src}); 1826 } 1827 /// Build and insert \p Res = G_VECREDUCE_ADD \p Src 1828 MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src) { 1829 return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src}); 1830 } 1831 1832 /// Build and insert \p Res = G_VECREDUCE_MUL \p Src 1833 MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src) { 1834 return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src}); 1835 } 1836 1837 /// Build and insert \p Res = G_VECREDUCE_AND \p Src 1838 MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src) { 1839 return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src}); 1840 } 1841 1842 /// Build and insert \p Res = G_VECREDUCE_OR \p Src 1843 MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src) { 1844 return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src}); 1845 } 1846 1847 /// Build and insert \p Res = G_VECREDUCE_XOR \p Src 1848 MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src) { 1849 return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src}); 1850 } 1851 1852 /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src 1853 MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src) { 1854 return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src}); 1855 } 1856 1857 /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src 1858 MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src) { 1859 return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src}); 1860 } 1861 1862 /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src 1863 MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src) { 1864 return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src}); 1865 } 1866 1867 /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src 1868 MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src) { 1869 return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src}); 1870 } 1871 1872 /// Build and insert G_MEMCPY or G_MEMMOVE 1873 MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, 1874 const SrcOp &SrcPtr, 1875 const SrcOp &Size, 1876 MachineMemOperand &DstMMO, 1877 MachineMemOperand &SrcMMO) { 1878 auto MIB = buildInstr( 1879 Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)}); 1880 MIB.addMemOperand(&DstMMO); 1881 MIB.addMemOperand(&SrcMMO); 1882 return MIB; 1883 } 1884 1885 MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, 1886 const SrcOp &Size, MachineMemOperand &DstMMO, 1887 MachineMemOperand &SrcMMO) { 1888 return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size, 1889 DstMMO, SrcMMO); 1890 } 1891 1892 /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width. 1893 MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, 1894 const SrcOp &LSB, const SrcOp &Width) { 1895 return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width}); 1896 } 1897 1898 /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width. 1899 MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, 1900 const SrcOp &LSB, const SrcOp &Width) { 1901 return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width}); 1902 } 1903 1904 /// Build and insert \p Dst = G_ROTR \p Src, \p Amt 1905 MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, 1906 const SrcOp &Amt) { 1907 return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt}); 1908 } 1909 1910 /// Build and insert \p Dst = G_ROTL \p Src, \p Amt 1911 MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, 1912 const SrcOp &Amt) { 1913 return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt}); 1914 } 1915 1916 /// Build and insert \p Dst = G_BITREVERSE \p Src 1917 MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src) { 1918 return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src}); 1919 } 1920 1921 virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, 1922 ArrayRef<SrcOp> SrcOps, 1923 Optional<unsigned> Flags = None); 1924 }; 1925 1926 } // End namespace llvm. 1927 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H 1928