1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the MachineIRBuilder class. 10 /// This is a helper class to build MachineInstr. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H 14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H 15 16 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/TargetOpcodes.h" 21 #include "llvm/IR/DebugLoc.h" 22 #include "llvm/IR/Module.h" 23 24 namespace llvm { 25 26 // Forward declarations. 27 class APInt; 28 class BlockAddress; 29 class Constant; 30 class ConstantFP; 31 class ConstantInt; 32 class DataLayout; 33 class GISelCSEInfo; 34 class GlobalValue; 35 class TargetRegisterClass; 36 class MachineFunction; 37 class MachineInstr; 38 class TargetInstrInfo; 39 class GISelChangeObserver; 40 41 /// Class which stores all the state required in a MachineIRBuilder. 42 /// Since MachineIRBuilders will only store state in this object, it allows 43 /// to transfer BuilderState between different kinds of MachineIRBuilders. 44 struct MachineIRBuilderState { 45 /// MachineFunction under construction. 46 MachineFunction *MF = nullptr; 47 /// Information used to access the description of the opcodes. 48 const TargetInstrInfo *TII = nullptr; 49 /// Information used to verify types are consistent and to create virtual registers. 50 MachineRegisterInfo *MRI = nullptr; 51 /// Debug location to be set to any instruction we create. 52 DebugLoc DL; 53 /// PC sections metadata to be set to any instruction we create. 54 MDNode *PCSections = nullptr; 55 56 /// \name Fields describing the insertion point. 57 /// @{ 58 MachineBasicBlock *MBB = nullptr; 59 MachineBasicBlock::iterator II; 60 /// @} 61 62 GISelChangeObserver *Observer = nullptr; 63 64 GISelCSEInfo *CSEInfo = nullptr; 65 }; 66 67 class DstOp { 68 union { 69 LLT LLTTy; 70 Register Reg; 71 const TargetRegisterClass *RC; 72 }; 73 74 public: 75 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC }; 76 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} 77 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} 78 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {} 79 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {} 80 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} 81 82 void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const { 83 switch (Ty) { 84 case DstType::Ty_Reg: 85 MIB.addDef(Reg); 86 break; 87 case DstType::Ty_LLT: 88 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy)); 89 break; 90 case DstType::Ty_RC: 91 MIB.addDef(MRI.createVirtualRegister(RC)); 92 break; 93 } 94 } 95 96 LLT getLLTTy(const MachineRegisterInfo &MRI) const { 97 switch (Ty) { 98 case DstType::Ty_RC: 99 return LLT{}; 100 case DstType::Ty_LLT: 101 return LLTTy; 102 case DstType::Ty_Reg: 103 return MRI.getType(Reg); 104 } 105 llvm_unreachable("Unrecognised DstOp::DstType enum"); 106 } 107 108 Register getReg() const { 109 assert(Ty == DstType::Ty_Reg && "Not a register"); 110 return Reg; 111 } 112 113 const TargetRegisterClass *getRegClass() const { 114 switch (Ty) { 115 case DstType::Ty_RC: 116 return RC; 117 default: 118 llvm_unreachable("Not a RC Operand"); 119 } 120 } 121 122 DstType getDstOpKind() const { return Ty; } 123 124 private: 125 DstType Ty; 126 }; 127 128 class SrcOp { 129 union { 130 MachineInstrBuilder SrcMIB; 131 Register Reg; 132 CmpInst::Predicate Pred; 133 int64_t Imm; 134 }; 135 136 public: 137 enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate, Ty_Imm }; 138 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} 139 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} 140 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} 141 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} 142 /// Use of registers held in unsigned integer variables (or more rarely signed 143 /// integers) is no longer permitted to avoid ambiguity with upcoming support 144 /// for immediates. 145 SrcOp(unsigned) = delete; 146 SrcOp(int) = delete; 147 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} 148 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} 149 150 void addSrcToMIB(MachineInstrBuilder &MIB) const { 151 switch (Ty) { 152 case SrcType::Ty_Predicate: 153 MIB.addPredicate(Pred); 154 break; 155 case SrcType::Ty_Reg: 156 MIB.addUse(Reg); 157 break; 158 case SrcType::Ty_MIB: 159 MIB.addUse(SrcMIB->getOperand(0).getReg()); 160 break; 161 case SrcType::Ty_Imm: 162 MIB.addImm(Imm); 163 break; 164 } 165 } 166 167 LLT getLLTTy(const MachineRegisterInfo &MRI) const { 168 switch (Ty) { 169 case SrcType::Ty_Predicate: 170 case SrcType::Ty_Imm: 171 llvm_unreachable("Not a register operand"); 172 case SrcType::Ty_Reg: 173 return MRI.getType(Reg); 174 case SrcType::Ty_MIB: 175 return MRI.getType(SrcMIB->getOperand(0).getReg()); 176 } 177 llvm_unreachable("Unrecognised SrcOp::SrcType enum"); 178 } 179 180 Register getReg() const { 181 switch (Ty) { 182 case SrcType::Ty_Predicate: 183 case SrcType::Ty_Imm: 184 llvm_unreachable("Not a register operand"); 185 case SrcType::Ty_Reg: 186 return Reg; 187 case SrcType::Ty_MIB: 188 return SrcMIB->getOperand(0).getReg(); 189 } 190 llvm_unreachable("Unrecognised SrcOp::SrcType enum"); 191 } 192 193 CmpInst::Predicate getPredicate() const { 194 switch (Ty) { 195 case SrcType::Ty_Predicate: 196 return Pred; 197 default: 198 llvm_unreachable("Not a register operand"); 199 } 200 } 201 202 int64_t getImm() const { 203 switch (Ty) { 204 case SrcType::Ty_Imm: 205 return Imm; 206 default: 207 llvm_unreachable("Not an immediate"); 208 } 209 } 210 211 SrcType getSrcOpKind() const { return Ty; } 212 213 private: 214 SrcType Ty; 215 }; 216 217 /// Helper class to build MachineInstr. 218 /// It keeps internally the insertion point and debug location for all 219 /// the new instructions we want to create. 220 /// This information can be modified via the related setters. 221 class MachineIRBuilder { 222 223 MachineIRBuilderState State; 224 225 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const; 226 227 protected: 228 void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend); 229 230 void validateUnaryOp(const LLT Res, const LLT Op0); 231 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1); 232 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1); 233 234 void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, 235 const LLT Op1Ty); 236 237 void recordInsertion(MachineInstr *InsertedInstr) const { 238 if (State.Observer) 239 State.Observer->createdInstr(*InsertedInstr); 240 } 241 242 public: 243 /// Some constructors for easy use. 244 MachineIRBuilder() = default; 245 MachineIRBuilder(MachineFunction &MF) { setMF(MF); } 246 247 MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt) { 248 setMF(*MBB.getParent()); 249 setInsertPt(MBB, InsPt); 250 } 251 252 MachineIRBuilder(MachineInstr &MI) : 253 MachineIRBuilder(*MI.getParent(), MI.getIterator()) { 254 setInstr(MI); 255 setDebugLoc(MI.getDebugLoc()); 256 } 257 258 MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer) : 259 MachineIRBuilder(MI) { 260 setChangeObserver(Observer); 261 } 262 263 virtual ~MachineIRBuilder() = default; 264 265 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {} 266 267 const TargetInstrInfo &getTII() { 268 assert(State.TII && "TargetInstrInfo is not set"); 269 return *State.TII; 270 } 271 272 /// Getter for the function we currently build. 273 MachineFunction &getMF() { 274 assert(State.MF && "MachineFunction is not set"); 275 return *State.MF; 276 } 277 278 const MachineFunction &getMF() const { 279 assert(State.MF && "MachineFunction is not set"); 280 return *State.MF; 281 } 282 283 const DataLayout &getDataLayout() const { 284 return getMF().getFunction().getParent()->getDataLayout(); 285 } 286 287 LLVMContext &getContext() const { 288 return getMF().getFunction().getContext(); 289 } 290 291 /// Getter for DebugLoc 292 const DebugLoc &getDL() { return State.DL; } 293 294 /// Getter for MRI 295 MachineRegisterInfo *getMRI() { return State.MRI; } 296 const MachineRegisterInfo *getMRI() const { return State.MRI; } 297 298 /// Getter for the State 299 MachineIRBuilderState &getState() { return State; } 300 301 /// Getter for the basic block we currently build. 302 const MachineBasicBlock &getMBB() const { 303 assert(State.MBB && "MachineBasicBlock is not set"); 304 return *State.MBB; 305 } 306 307 MachineBasicBlock &getMBB() { 308 return const_cast<MachineBasicBlock &>( 309 const_cast<const MachineIRBuilder *>(this)->getMBB()); 310 } 311 312 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; } 313 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; } 314 315 /// Current insertion point for new instructions. 316 MachineBasicBlock::iterator getInsertPt() { return State.II; } 317 318 /// Set the insertion point before the specified position. 319 /// \pre MBB must be in getMF(). 320 /// \pre II must be a valid iterator in MBB. 321 void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II) { 322 assert(MBB.getParent() == &getMF() && 323 "Basic block is in a different function"); 324 State.MBB = &MBB; 325 State.II = II; 326 } 327 328 /// @} 329 330 void setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; } 331 332 /// \name Setters for the insertion point. 333 /// @{ 334 /// Set the MachineFunction where to build instructions. 335 void setMF(MachineFunction &MF); 336 337 /// Set the insertion point to the end of \p MBB. 338 /// \pre \p MBB must be contained by getMF(). 339 void setMBB(MachineBasicBlock &MBB) { 340 State.MBB = &MBB; 341 State.II = MBB.end(); 342 assert(&getMF() == MBB.getParent() && 343 "Basic block is in a different function"); 344 } 345 346 /// Set the insertion point to before MI. 347 /// \pre MI must be in getMF(). 348 void setInstr(MachineInstr &MI) { 349 assert(MI.getParent() && "Instruction is not part of a basic block"); 350 setMBB(*MI.getParent()); 351 State.II = MI.getIterator(); 352 setPCSections(MI.getPCSections()); 353 } 354 /// @} 355 356 /// Set the insertion point to before MI, and set the debug loc to MI's loc. 357 /// \pre MI must be in getMF(). 358 void setInstrAndDebugLoc(MachineInstr &MI) { 359 setInstr(MI); 360 setDebugLoc(MI.getDebugLoc()); 361 } 362 363 void setChangeObserver(GISelChangeObserver &Observer) { 364 State.Observer = &Observer; 365 } 366 367 void stopObservingChanges() { State.Observer = nullptr; } 368 /// @} 369 370 /// Set the debug location to \p DL for all the next build instructions. 371 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; } 372 373 /// Get the current instruction's debug location. 374 const DebugLoc &getDebugLoc() { return State.DL; } 375 376 /// Set the PC sections metadata to \p MD for all the next build instructions. 377 void setPCSections(MDNode *MD) { State.PCSections = MD; } 378 379 /// Get the current instruction's PC sections metadata. 380 MDNode *getPCSections() { return State.PCSections; } 381 382 /// Build and insert <empty> = \p Opcode <empty>. 383 /// The insertion point is the one set by the last call of either 384 /// setBasicBlock or setMI. 385 /// 386 /// \pre setBasicBlock or setMI must have been called. 387 /// 388 /// \return a MachineInstrBuilder for the newly created instruction. 389 MachineInstrBuilder buildInstr(unsigned Opcode) { 390 return insertInstr(buildInstrNoInsert(Opcode)); 391 } 392 393 /// Build but don't insert <empty> = \p Opcode <empty>. 394 /// 395 /// \pre setMF, setBasicBlock or setMI must have been called. 396 /// 397 /// \return a MachineInstrBuilder for the newly created instruction. 398 MachineInstrBuilder buildInstrNoInsert(unsigned Opcode); 399 400 /// Insert an existing instruction at the insertion point. 401 MachineInstrBuilder insertInstr(MachineInstrBuilder MIB); 402 403 /// Build and insert a DBG_VALUE instruction expressing the fact that the 404 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr). 405 MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, 406 const MDNode *Expr); 407 408 /// Build and insert a DBG_VALUE instruction expressing the fact that the 409 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p 410 /// Expr). 411 MachineInstrBuilder buildIndirectDbgValue(Register Reg, 412 const MDNode *Variable, 413 const MDNode *Expr); 414 415 /// Build and insert a DBG_VALUE instruction expressing the fact that the 416 /// associated \p Variable lives in the stack slot specified by \p FI 417 /// (suitably modified by \p Expr). 418 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, 419 const MDNode *Expr); 420 421 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is 422 /// given by \p C (suitably modified by \p Expr). 423 MachineInstrBuilder buildConstDbgValue(const Constant &C, 424 const MDNode *Variable, 425 const MDNode *Expr); 426 427 /// Build and insert a DBG_LABEL instructions specifying that \p Label is 428 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label". 429 MachineInstrBuilder buildDbgLabel(const MDNode *Label); 430 431 /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align 432 /// 433 /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of 434 /// the allocated memory into \p Res. 435 /// \pre setBasicBlock or setMI must have been called. 436 /// \pre \p Res must be a generic virtual register with pointer type. 437 /// 438 /// \return a MachineInstrBuilder for the newly created instruction. 439 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, 440 Align Alignment); 441 442 /// Build and insert \p Res = G_FRAME_INDEX \p Idx 443 /// 444 /// G_FRAME_INDEX materializes the address of an alloca value or other 445 /// stack-based object. 446 /// 447 /// \pre setBasicBlock or setMI must have been called. 448 /// \pre \p Res must be a generic virtual register with pointer type. 449 /// 450 /// \return a MachineInstrBuilder for the newly created instruction. 451 MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx); 452 453 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV 454 /// 455 /// G_GLOBAL_VALUE materializes the address of the specified global 456 /// into \p Res. 457 /// 458 /// \pre setBasicBlock or setMI must have been called. 459 /// \pre \p Res must be a generic virtual register with pointer type 460 /// in the same address space as \p GV. 461 /// 462 /// \return a MachineInstrBuilder for the newly created instruction. 463 MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV); 464 465 /// Build and insert \p Res = G_CONSTANT_POOL \p Idx 466 /// 467 /// G_CONSTANT_POOL materializes the address of an object in the constant 468 /// pool. 469 /// 470 /// \pre setBasicBlock or setMI must have been called. 471 /// \pre \p Res must be a generic virtual register with pointer type. 472 /// 473 /// \return a MachineInstrBuilder for the newly created instruction. 474 MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx); 475 476 /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1 477 /// 478 /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0, 479 /// storing the resulting pointer in \p Res. Addressible units are typically 480 /// bytes but this can vary between targets. 481 /// 482 /// \pre setBasicBlock or setMI must have been called. 483 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer 484 /// type. 485 /// \pre \p Op1 must be a generic virtual register with scalar type. 486 /// 487 /// \return a MachineInstrBuilder for the newly created instruction. 488 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, 489 const SrcOp &Op1); 490 491 /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value) 492 /// 493 /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0, 494 /// storing the resulting pointer in \p Res. If \p Value is zero then no 495 /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to 496 /// \p Res. 497 /// 498 /// \pre setBasicBlock or setMI must have been called. 499 /// \pre \p Op0 must be a generic virtual register with pointer type. 500 /// \pre \p ValueTy must be a scalar type. 501 /// \pre \p Res must be 0. This is to detect confusion between 502 /// materializePtrAdd() and buildPtrAdd(). 503 /// \post \p Res will either be a new generic virtual register of the same 504 /// type as \p Op0 or \p Op0 itself. 505 /// 506 /// \return a MachineInstrBuilder for the newly created instruction. 507 std::optional<MachineInstrBuilder> materializePtrAdd(Register &Res, 508 Register Op0, 509 const LLT ValueTy, 510 uint64_t Value); 511 512 /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1 513 MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, 514 const SrcOp &Op1) { 515 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1}); 516 } 517 518 /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1 519 /// 520 /// This clears the low bits of a pointer operand without destroying its 521 /// pointer properties. This has the effect of rounding the address *down* to 522 /// a specified alignment in bits. 523 /// 524 /// \pre setBasicBlock or setMI must have been called. 525 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer 526 /// type. 527 /// \pre \p NumBits must be an integer representing the number of low bits to 528 /// be cleared in \p Op0. 529 /// 530 /// \return a MachineInstrBuilder for the newly created instruction. 531 MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, 532 uint32_t NumBits); 533 534 /// Build and insert 535 /// a, b, ..., x = G_UNMERGE_VALUES \p Op0 536 /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef 537 /// 538 /// Pad \p Op0 with undef elements to match number of elements in \p Res. 539 /// 540 /// \pre setBasicBlock or setMI must have been called. 541 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type, 542 /// same vector element type and Op0 must have fewer elements then Res. 543 /// 544 /// \return a MachineInstrBuilder for the newly created build vector instr. 545 MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, 546 const SrcOp &Op0); 547 548 /// Build and insert 549 /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0 550 /// \p Res = G_BUILD_VECTOR a, b, ..., x 551 /// 552 /// Delete trailing elements in \p Op0 to match number of elements in \p Res. 553 /// 554 /// \pre setBasicBlock or setMI must have been called. 555 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type, 556 /// same vector element type and Op0 must have more elements then Res. 557 /// 558 /// \return a MachineInstrBuilder for the newly created build vector instr. 559 MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, 560 const SrcOp &Op0); 561 562 /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1 563 /// 564 /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and 565 /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic. 566 /// 567 /// \pre setBasicBlock or setMI must have been called. 568 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the 569 /// same scalar type. 570 ////\pre \p CarryOut must be generic virtual register with scalar type 571 ///(typically s1) 572 /// 573 /// \return The newly created instruction. 574 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, 575 const SrcOp &Op0, const SrcOp &Op1) { 576 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1}); 577 } 578 579 /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1 580 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, 581 const SrcOp &Op0, const SrcOp &Op1) { 582 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1}); 583 } 584 585 /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1 586 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, 587 const SrcOp &Op0, const SrcOp &Op1) { 588 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1}); 589 } 590 591 /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1 592 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, 593 const SrcOp &Op0, const SrcOp &Op1) { 594 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1}); 595 } 596 597 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0, 598 /// \p Op1, \p CarryIn 599 /// 600 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit 601 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned 602 /// arithmetic. 603 /// 604 /// \pre setBasicBlock or setMI must have been called. 605 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 606 /// with the same scalar type. 607 /// \pre \p CarryOut and \p CarryIn must be generic virtual 608 /// registers with the same scalar type (typically s1) 609 /// 610 /// \return The newly created instruction. 611 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, 612 const SrcOp &Op0, const SrcOp &Op1, 613 const SrcOp &CarryIn) { 614 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, 615 {Op0, Op1, CarryIn}); 616 } 617 618 /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp 619 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, 620 const SrcOp &Op0, const SrcOp &Op1, 621 const SrcOp &CarryIn) { 622 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut}, 623 {Op0, Op1, CarryIn}); 624 } 625 626 /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp 627 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, 628 const SrcOp &Op0, const SrcOp &Op1, 629 const SrcOp &CarryIn) { 630 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut}, 631 {Op0, Op1, CarryIn}); 632 } 633 634 /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp 635 MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, 636 const SrcOp &Op0, const SrcOp &Op1, 637 const SrcOp &CarryIn) { 638 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut}, 639 {Op0, Op1, CarryIn}); 640 } 641 642 /// Build and insert \p Res = G_ANYEXT \p Op0 643 /// 644 /// G_ANYEXT produces a register of the specified width, with bits 0 to 645 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified 646 /// (i.e. this is neither zero nor sign-extension). For a vector register, 647 /// each element is extended individually. 648 /// 649 /// \pre setBasicBlock or setMI must have been called. 650 /// \pre \p Res must be a generic virtual register with scalar or vector type. 651 /// \pre \p Op must be a generic virtual register with scalar or vector type. 652 /// \pre \p Op must be smaller than \p Res 653 /// 654 /// \return The newly created instruction. 655 656 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op); 657 658 /// Build and insert \p Res = G_SEXT \p Op 659 /// 660 /// G_SEXT produces a register of the specified width, with bits 0 to 661 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the 662 /// high bit of \p Op (i.e. 2s-complement sign extended). 663 /// 664 /// \pre setBasicBlock or setMI must have been called. 665 /// \pre \p Res must be a generic virtual register with scalar or vector type. 666 /// \pre \p Op must be a generic virtual register with scalar or vector type. 667 /// \pre \p Op must be smaller than \p Res 668 /// 669 /// \return The newly created instruction. 670 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op); 671 672 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp 673 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) { 674 return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)}); 675 } 676 677 /// Build and insert \p Res = G_FPEXT \p Op 678 MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, 679 std::optional<unsigned> Flags = std::nullopt) { 680 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags); 681 } 682 683 /// Build and insert a G_PTRTOINT instruction. 684 MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) { 685 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src}); 686 } 687 688 /// Build and insert a G_INTTOPTR instruction. 689 MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) { 690 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src}); 691 } 692 693 /// Build and insert \p Dst = G_BITCAST \p Src 694 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) { 695 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src}); 696 } 697 698 /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src 699 MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src) { 700 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src}); 701 } 702 703 /// \return The opcode of the extension the target wants to use for boolean 704 /// values. 705 unsigned getBoolExtOp(bool IsVec, bool IsFP) const; 706 707 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res 708 // = G_ZEXT \p Op depending on how the target wants to extend boolean values. 709 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, 710 bool IsFP); 711 712 // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1, 713 // or COPY depending on how the target wants to extend boolean values, using 714 // the original register size. 715 MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, 716 bool IsVector, 717 bool IsFP); 718 719 /// Build and insert \p Res = G_ZEXT \p Op 720 /// 721 /// G_ZEXT produces a register of the specified width, with bits 0 to 722 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector 723 /// register, each element is extended individually. 724 /// 725 /// \pre setBasicBlock or setMI must have been called. 726 /// \pre \p Res must be a generic virtual register with scalar or vector type. 727 /// \pre \p Op must be a generic virtual register with scalar or vector type. 728 /// \pre \p Op must be smaller than \p Res 729 /// 730 /// \return The newly created instruction. 731 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op); 732 733 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or 734 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. 735 /// /// 736 /// \pre setBasicBlock or setMI must have been called. 737 /// \pre \p Res must be a generic virtual register with scalar or vector type. 738 /// \pre \p Op must be a generic virtual register with scalar or vector type. 739 /// 740 /// \return The newly created instruction. 741 MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op); 742 743 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or 744 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. 745 /// /// 746 /// \pre setBasicBlock or setMI must have been called. 747 /// \pre \p Res must be a generic virtual register with scalar or vector type. 748 /// \pre \p Op must be a generic virtual register with scalar or vector type. 749 /// 750 /// \return The newly created instruction. 751 MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op); 752 753 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or 754 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. 755 /// /// 756 /// \pre setBasicBlock or setMI must have been called. 757 /// \pre \p Res must be a generic virtual register with scalar or vector type. 758 /// \pre \p Op must be a generic virtual register with scalar or vector type. 759 /// 760 /// \return The newly created instruction. 761 MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op); 762 763 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p 764 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and 765 /// \p Op. 766 /// /// 767 /// \pre setBasicBlock or setMI must have been called. 768 /// \pre \p Res must be a generic virtual register with scalar or vector type. 769 /// \pre \p Op must be a generic virtual register with scalar or vector type. 770 /// 771 /// \return The newly created instruction. 772 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, 773 const SrcOp &Op); 774 775 /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp) 776 /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is 777 /// emulated using G_AND. 778 MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, 779 int64_t ImmOp); 780 781 /// Build and insert an appropriate cast between two registers of equal size. 782 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src); 783 784 /// Build and insert G_BR \p Dest 785 /// 786 /// G_BR is an unconditional branch to \p Dest. 787 /// 788 /// \pre setBasicBlock or setMI must have been called. 789 /// 790 /// \return a MachineInstrBuilder for the newly created instruction. 791 MachineInstrBuilder buildBr(MachineBasicBlock &Dest); 792 793 /// Build and insert G_BRCOND \p Tst, \p Dest 794 /// 795 /// G_BRCOND is a conditional branch to \p Dest. 796 /// 797 /// \pre setBasicBlock or setMI must have been called. 798 /// \pre \p Tst must be a generic virtual register with scalar 799 /// type. At the beginning of legalization, this will be a single 800 /// bit (s1). Targets with interesting flags registers may change 801 /// this. For a wider type, whether the branch is taken must only 802 /// depend on bit 0 (for now). 803 /// 804 /// \return The newly created instruction. 805 MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest); 806 807 /// Build and insert G_BRINDIRECT \p Tgt 808 /// 809 /// G_BRINDIRECT is an indirect branch to \p Tgt. 810 /// 811 /// \pre setBasicBlock or setMI must have been called. 812 /// \pre \p Tgt must be a generic virtual register with pointer type. 813 /// 814 /// \return a MachineInstrBuilder for the newly created instruction. 815 MachineInstrBuilder buildBrIndirect(Register Tgt); 816 817 /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg 818 /// 819 /// G_BRJT is a jump table branch using a table base pointer \p TablePtr, 820 /// jump table index \p JTI and index \p IndexReg 821 /// 822 /// \pre setBasicBlock or setMI must have been called. 823 /// \pre \p TablePtr must be a generic virtual register with pointer type. 824 /// \pre \p JTI must be be a jump table index. 825 /// \pre \p IndexReg must be a generic virtual register with pointer type. 826 /// 827 /// \return a MachineInstrBuilder for the newly created instruction. 828 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, 829 Register IndexReg); 830 831 /// Build and insert \p Res = G_CONSTANT \p Val 832 /// 833 /// G_CONSTANT is an integer constant with the specified size and value. \p 834 /// Val will be extended or truncated to the size of \p Reg. 835 /// 836 /// \pre setBasicBlock or setMI must have been called. 837 /// \pre \p Res must be a generic virtual register with scalar or pointer 838 /// type. 839 /// 840 /// \return The newly created instruction. 841 virtual MachineInstrBuilder buildConstant(const DstOp &Res, 842 const ConstantInt &Val); 843 844 /// Build and insert \p Res = G_CONSTANT \p Val 845 /// 846 /// G_CONSTANT is an integer constant with the specified size and value. 847 /// 848 /// \pre setBasicBlock or setMI must have been called. 849 /// \pre \p Res must be a generic virtual register with scalar type. 850 /// 851 /// \return The newly created instruction. 852 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val); 853 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val); 854 855 /// Build and insert \p Res = G_FCONSTANT \p Val 856 /// 857 /// G_FCONSTANT is a floating-point constant with the specified size and 858 /// value. 859 /// 860 /// \pre setBasicBlock or setMI must have been called. 861 /// \pre \p Res must be a generic virtual register with scalar type. 862 /// 863 /// \return The newly created instruction. 864 virtual MachineInstrBuilder buildFConstant(const DstOp &Res, 865 const ConstantFP &Val); 866 867 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val); 868 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val); 869 870 /// Build and insert \p Res = COPY Op 871 /// 872 /// Register-to-register COPY sets \p Res to \p Op. 873 /// 874 /// \pre setBasicBlock or setMI must have been called. 875 /// 876 /// \return a MachineInstrBuilder for the newly created instruction. 877 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op); 878 879 880 /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN 881 /// 882 /// \return a MachineInstrBuilder for the newly created instruction. 883 MachineInstrBuilder buildAssertInstr(unsigned Opc, const DstOp &Res, 884 const SrcOp &Op, unsigned Val) { 885 return buildInstr(Opc, Res, Op).addImm(Val); 886 } 887 888 /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size 889 /// 890 /// \return a MachineInstrBuilder for the newly created instruction. 891 MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, 892 unsigned Size) { 893 return buildAssertInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size); 894 } 895 896 /// Build and insert \p Res = G_ASSERT_SEXT Op, Size 897 /// 898 /// \return a MachineInstrBuilder for the newly created instruction. 899 MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, 900 unsigned Size) { 901 return buildAssertInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size); 902 } 903 904 /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal 905 /// 906 /// \return a MachineInstrBuilder for the newly created instruction. 907 MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, 908 Align AlignVal) { 909 return buildAssertInstr(TargetOpcode::G_ASSERT_ALIGN, Res, Op, 910 AlignVal.value()); 911 } 912 913 /// Build and insert `Res = G_LOAD Addr, MMO`. 914 /// 915 /// Loads the value stored at \p Addr. Puts the result in \p Res. 916 /// 917 /// \pre setBasicBlock or setMI must have been called. 918 /// \pre \p Res must be a generic virtual register. 919 /// \pre \p Addr must be a generic virtual register with pointer type. 920 /// 921 /// \return a MachineInstrBuilder for the newly created instruction. 922 MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, 923 MachineMemOperand &MMO) { 924 return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO); 925 } 926 927 /// Build and insert a G_LOAD instruction, while constructing the 928 /// MachineMemOperand. 929 MachineInstrBuilder 930 buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo, 931 Align Alignment, 932 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, 933 const AAMDNodes &AAInfo = AAMDNodes()); 934 935 /// Build and insert `Res = <opcode> Addr, MMO`. 936 /// 937 /// Loads the value stored at \p Addr. Puts the result in \p Res. 938 /// 939 /// \pre setBasicBlock or setMI must have been called. 940 /// \pre \p Res must be a generic virtual register. 941 /// \pre \p Addr must be a generic virtual register with pointer type. 942 /// 943 /// \return a MachineInstrBuilder for the newly created instruction. 944 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, 945 const SrcOp &Addr, MachineMemOperand &MMO); 946 947 /// Helper to create a load from a constant offset given a base address. Load 948 /// the type of \p Dst from \p Offset from the given base address and memory 949 /// operand. 950 MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, 951 const SrcOp &BasePtr, 952 MachineMemOperand &BaseMMO, 953 int64_t Offset); 954 955 /// Build and insert `G_STORE Val, Addr, MMO`. 956 /// 957 /// Stores the value \p Val to \p Addr. 958 /// 959 /// \pre setBasicBlock or setMI must have been called. 960 /// \pre \p Val must be a generic virtual register. 961 /// \pre \p Addr must be a generic virtual register with pointer type. 962 /// 963 /// \return a MachineInstrBuilder for the newly created instruction. 964 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, 965 MachineMemOperand &MMO); 966 967 /// Build and insert a G_STORE instruction, while constructing the 968 /// MachineMemOperand. 969 MachineInstrBuilder 970 buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo, 971 Align Alignment, 972 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, 973 const AAMDNodes &AAInfo = AAMDNodes()); 974 975 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`. 976 /// 977 /// \pre setBasicBlock or setMI must have been called. 978 /// \pre \p Res and \p Src must be generic virtual registers. 979 /// 980 /// \return a MachineInstrBuilder for the newly created instruction. 981 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index); 982 983 /// Build and insert \p Res = IMPLICIT_DEF. 984 MachineInstrBuilder buildUndef(const DstOp &Res); 985 986 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ... 987 /// 988 /// G_MERGE_VALUES combines the input elements contiguously into a larger 989 /// register. It should only be used when the destination register is not a 990 /// vector. 991 /// 992 /// \pre setBasicBlock or setMI must have been called. 993 /// \pre The entire register \p Res (and no more) must be covered by the input 994 /// registers. 995 /// \pre The type of all \p Ops registers must be identical. 996 /// 997 /// \return a MachineInstrBuilder for the newly created instruction. 998 MachineInstrBuilder buildMergeValues(const DstOp &Res, 999 ArrayRef<Register> Ops); 1000 1001 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ... 1002 /// or \p Res = G_BUILD_VECTOR \p Op0, ... 1003 /// or \p Res = G_CONCAT_VECTORS \p Op0, ... 1004 /// 1005 /// G_MERGE_VALUES combines the input elements contiguously into a larger 1006 /// register. It is used when the destination register is not a vector. 1007 /// G_BUILD_VECTOR combines scalar inputs into a vector register. 1008 /// G_CONCAT_VECTORS combines vector inputs into a vector register. 1009 /// 1010 /// \pre setBasicBlock or setMI must have been called. 1011 /// \pre The entire register \p Res (and no more) must be covered by the input 1012 /// registers. 1013 /// \pre The type of all \p Ops registers must be identical. 1014 /// 1015 /// \return a MachineInstrBuilder for the newly created instruction. The 1016 /// opcode of the new instruction will depend on the types of both 1017 /// the destination and the sources. 1018 MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, 1019 ArrayRef<Register> Ops); 1020 MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, 1021 std::initializer_list<SrcOp> Ops); 1022 1023 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op 1024 /// 1025 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple 1026 /// 1027 /// \pre setBasicBlock or setMI must have been called. 1028 /// \pre The entire register \p Res (and no more) must be covered by the input 1029 /// registers. 1030 /// \pre The type of all \p Res registers must be identical. 1031 /// 1032 /// \return a MachineInstrBuilder for the newly created instruction. 1033 MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op); 1034 MachineInstrBuilder buildUnmerge(ArrayRef<Register> Res, const SrcOp &Op); 1035 1036 /// Build and insert an unmerge of \p Res sized pieces to cover \p Op 1037 MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op); 1038 1039 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... 1040 /// 1041 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers. 1042 /// \pre setBasicBlock or setMI must have been called. 1043 /// \pre The entire register \p Res (and no more) must be covered by the 1044 /// input scalar registers. 1045 /// \pre The type of all \p Ops registers must be identical. 1046 /// 1047 /// \return a MachineInstrBuilder for the newly created instruction. 1048 MachineInstrBuilder buildBuildVector(const DstOp &Res, 1049 ArrayRef<Register> Ops); 1050 1051 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is 1052 /// built with G_CONSTANT. 1053 MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, 1054 ArrayRef<APInt> Ops); 1055 1056 /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill 1057 /// the number of elements 1058 MachineInstrBuilder buildSplatVector(const DstOp &Res, 1059 const SrcOp &Src); 1060 1061 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ... 1062 /// 1063 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers 1064 /// which have types larger than the destination vector element type, and 1065 /// truncates the values to fit. 1066 /// 1067 /// If the operands given are already the same size as the vector elt type, 1068 /// then this method will instead create a G_BUILD_VECTOR instruction. 1069 /// 1070 /// \pre setBasicBlock or setMI must have been called. 1071 /// \pre The type of all \p Ops registers must be identical. 1072 /// 1073 /// \return a MachineInstrBuilder for the newly created instruction. 1074 MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, 1075 ArrayRef<Register> Ops); 1076 1077 /// Build and insert a vector splat of a scalar \p Src using a 1078 /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom. 1079 /// 1080 /// \pre setBasicBlock or setMI must have been called. 1081 /// \pre \p Src must have the same type as the element type of \p Dst 1082 /// 1083 /// \return a MachineInstrBuilder for the newly created instruction. 1084 MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src); 1085 1086 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask 1087 /// 1088 /// \pre setBasicBlock or setMI must have been called. 1089 /// 1090 /// \return a MachineInstrBuilder for the newly created instruction. 1091 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, 1092 const SrcOp &Src2, ArrayRef<int> Mask); 1093 1094 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ... 1095 /// 1096 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more 1097 /// vectors. 1098 /// 1099 /// \pre setBasicBlock or setMI must have been called. 1100 /// \pre The entire register \p Res (and no more) must be covered by the input 1101 /// registers. 1102 /// \pre The type of all source operands must be identical. 1103 /// 1104 /// \return a MachineInstrBuilder for the newly created instruction. 1105 MachineInstrBuilder buildConcatVectors(const DstOp &Res, 1106 ArrayRef<Register> Ops); 1107 1108 MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, 1109 const SrcOp &Op, unsigned Index); 1110 1111 /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or 1112 /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the 1113 /// result register definition unless \p Reg is NoReg (== 0). The second 1114 /// operand will be the intrinsic's ID. 1115 /// 1116 /// Callers are expected to add the required definitions and uses afterwards. 1117 /// 1118 /// \pre setBasicBlock or setMI must have been called. 1119 /// 1120 /// \return a MachineInstrBuilder for the newly created instruction. 1121 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<Register> Res, 1122 bool HasSideEffects); 1123 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res, 1124 bool HasSideEffects); 1125 1126 /// Build and insert \p Res = G_FPTRUNC \p Op 1127 /// 1128 /// G_FPTRUNC converts a floating-point value into one with a smaller type. 1129 /// 1130 /// \pre setBasicBlock or setMI must have been called. 1131 /// \pre \p Res must be a generic virtual register with scalar or vector type. 1132 /// \pre \p Op must be a generic virtual register with scalar or vector type. 1133 /// \pre \p Res must be smaller than \p Op 1134 /// 1135 /// \return The newly created instruction. 1136 MachineInstrBuilder 1137 buildFPTrunc(const DstOp &Res, const SrcOp &Op, 1138 std::optional<unsigned> Flags = std::nullopt); 1139 1140 /// Build and insert \p Res = G_TRUNC \p Op 1141 /// 1142 /// G_TRUNC extracts the low bits of a type. For a vector type each element is 1143 /// truncated independently before being packed into the destination. 1144 /// 1145 /// \pre setBasicBlock or setMI must have been called. 1146 /// \pre \p Res must be a generic virtual register with scalar or vector type. 1147 /// \pre \p Op must be a generic virtual register with scalar or vector type. 1148 /// \pre \p Res must be smaller than \p Op 1149 /// 1150 /// \return The newly created instruction. 1151 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op); 1152 1153 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1 1154 /// 1155 /// \pre setBasicBlock or setMI must have been called. 1156 1157 /// \pre \p Res must be a generic virtual register with scalar or 1158 /// vector type. Typically this starts as s1 or <N x s1>. 1159 /// \pre \p Op0 and Op1 must be generic virtual registers with the 1160 /// same number of elements as \p Res. If \p Res is a scalar, 1161 /// \p Op0 must be either a scalar or pointer. 1162 /// \pre \p Pred must be an integer predicate. 1163 /// 1164 /// \return a MachineInstrBuilder for the newly created instruction. 1165 MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, 1166 const SrcOp &Op0, const SrcOp &Op1); 1167 1168 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1 1169 /// 1170 /// \pre setBasicBlock or setMI must have been called. 1171 1172 /// \pre \p Res must be a generic virtual register with scalar or 1173 /// vector type. Typically this starts as s1 or <N x s1>. 1174 /// \pre \p Op0 and Op1 must be generic virtual registers with the 1175 /// same number of elements as \p Res (or scalar, if \p Res is 1176 /// scalar). 1177 /// \pre \p Pred must be a floating-point predicate. 1178 /// 1179 /// \return a MachineInstrBuilder for the newly created instruction. 1180 MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, 1181 const SrcOp &Op0, const SrcOp &Op1, 1182 std::optional<unsigned> Flags = std::nullopt); 1183 1184 /// Build and insert a \p Res = G_IS_FPCLASS \p Pred\p Src, \p Mask 1185 MachineInstrBuilder buildIsFPClass(const DstOp &Res, const SrcOp &Src, 1186 unsigned Mask) { 1187 return buildInstr(TargetOpcode::G_IS_FPCLASS, {Res}, 1188 {Src, SrcOp(static_cast<int64_t>(Mask))}); 1189 } 1190 1191 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1 1192 /// 1193 /// \pre setBasicBlock or setMI must have been called. 1194 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1195 /// with the same type. 1196 /// \pre \p Tst must be a generic virtual register with scalar, pointer or 1197 /// vector type. If vector then it must have the same number of 1198 /// elements as the other parameters. 1199 /// 1200 /// \return a MachineInstrBuilder for the newly created instruction. 1201 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, 1202 const SrcOp &Op0, const SrcOp &Op1, 1203 std::optional<unsigned> Flags = std::nullopt); 1204 1205 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val, 1206 /// \p Elt, \p Idx 1207 /// 1208 /// \pre setBasicBlock or setMI must have been called. 1209 /// \pre \p Res and \p Val must be a generic virtual register 1210 // with the same vector type. 1211 /// \pre \p Elt and \p Idx must be a generic virtual register 1212 /// with scalar type. 1213 /// 1214 /// \return The newly created instruction. 1215 MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, 1216 const SrcOp &Val, 1217 const SrcOp &Elt, 1218 const SrcOp &Idx); 1219 1220 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx 1221 /// 1222 /// \pre setBasicBlock or setMI must have been called. 1223 /// \pre \p Res must be a generic virtual register with scalar type. 1224 /// \pre \p Val must be a generic virtual register with vector type. 1225 /// 1226 /// \return The newly created instruction. 1227 MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res, 1228 const SrcOp &Val, 1229 const int Idx) { 1230 return buildExtractVectorElement(Res, Val, 1231 buildConstant(LLT::scalar(64), Idx)); 1232 } 1233 1234 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx 1235 /// 1236 /// \pre setBasicBlock or setMI must have been called. 1237 /// \pre \p Res must be a generic virtual register with scalar type. 1238 /// \pre \p Val must be a generic virtual register with vector type. 1239 /// \pre \p Idx must be a generic virtual register with scalar type. 1240 /// 1241 /// \return The newly created instruction. 1242 MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, 1243 const SrcOp &Val, 1244 const SrcOp &Idx); 1245 1246 /// Build and insert `OldValRes<def>, SuccessRes<def> = 1247 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`. 1248 /// 1249 /// Atomically replace the value at \p Addr with \p NewVal if it is currently 1250 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p 1251 /// Addr in \p Res, along with an s1 indicating whether it was replaced. 1252 /// 1253 /// \pre setBasicBlock or setMI must have been called. 1254 /// \pre \p OldValRes must be a generic virtual register of scalar type. 1255 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It 1256 /// will be assigned 0 on failure and 1 on success. 1257 /// \pre \p Addr must be a generic virtual register with pointer type. 1258 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual 1259 /// registers of the same type. 1260 /// 1261 /// \return a MachineInstrBuilder for the newly created instruction. 1262 MachineInstrBuilder 1263 buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, 1264 Register Addr, Register CmpVal, Register NewVal, 1265 MachineMemOperand &MMO); 1266 1267 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, 1268 /// MMO`. 1269 /// 1270 /// Atomically replace the value at \p Addr with \p NewVal if it is currently 1271 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p 1272 /// Addr in \p Res. 1273 /// 1274 /// \pre setBasicBlock or setMI must have been called. 1275 /// \pre \p OldValRes must be a generic virtual register of scalar type. 1276 /// \pre \p Addr must be a generic virtual register with pointer type. 1277 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual 1278 /// registers of the same type. 1279 /// 1280 /// \return a MachineInstrBuilder for the newly created instruction. 1281 MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, 1282 Register CmpVal, Register NewVal, 1283 MachineMemOperand &MMO); 1284 1285 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`. 1286 /// 1287 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the 1288 /// original value from \p Addr in \p OldValRes. The modification is 1289 /// determined by the opcode. 1290 /// 1291 /// \pre setBasicBlock or setMI must have been called. 1292 /// \pre \p OldValRes must be a generic virtual register. 1293 /// \pre \p Addr must be a generic virtual register with pointer type. 1294 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1295 /// same type. 1296 /// 1297 /// \return a MachineInstrBuilder for the newly created instruction. 1298 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, 1299 const SrcOp &Addr, const SrcOp &Val, 1300 MachineMemOperand &MMO); 1301 1302 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`. 1303 /// 1304 /// Atomically replace the value at \p Addr with \p Val. Puts the original 1305 /// value from \p Addr in \p OldValRes. 1306 /// 1307 /// \pre setBasicBlock or setMI must have been called. 1308 /// \pre \p OldValRes must be a generic virtual register. 1309 /// \pre \p Addr must be a generic virtual register with pointer type. 1310 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1311 /// same type. 1312 /// 1313 /// \return a MachineInstrBuilder for the newly created instruction. 1314 MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, 1315 Register Val, MachineMemOperand &MMO); 1316 1317 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`. 1318 /// 1319 /// Atomically replace the value at \p Addr with the addition of \p Val and 1320 /// the original value. Puts the original value from \p Addr in \p OldValRes. 1321 /// 1322 /// \pre setBasicBlock or setMI must have been called. 1323 /// \pre \p OldValRes must be a generic virtual register. 1324 /// \pre \p Addr must be a generic virtual register with pointer type. 1325 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1326 /// same type. 1327 /// 1328 /// \return a MachineInstrBuilder for the newly created instruction. 1329 MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, 1330 Register Val, MachineMemOperand &MMO); 1331 1332 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`. 1333 /// 1334 /// Atomically replace the value at \p Addr with the subtraction of \p Val and 1335 /// the original value. Puts the original value from \p Addr in \p OldValRes. 1336 /// 1337 /// \pre setBasicBlock or setMI must have been called. 1338 /// \pre \p OldValRes must be a generic virtual register. 1339 /// \pre \p Addr must be a generic virtual register with pointer type. 1340 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1341 /// same type. 1342 /// 1343 /// \return a MachineInstrBuilder for the newly created instruction. 1344 MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, 1345 Register Val, MachineMemOperand &MMO); 1346 1347 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`. 1348 /// 1349 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and 1350 /// the original value. Puts the original value from \p Addr in \p OldValRes. 1351 /// 1352 /// \pre setBasicBlock or setMI must have been called. 1353 /// \pre \p OldValRes must be a generic virtual register. 1354 /// \pre \p Addr must be a generic virtual register with pointer type. 1355 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1356 /// same type. 1357 /// 1358 /// \return a MachineInstrBuilder for the newly created instruction. 1359 MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, 1360 Register Val, MachineMemOperand &MMO); 1361 1362 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`. 1363 /// 1364 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val 1365 /// and the original value. Puts the original value from \p Addr in \p 1366 /// OldValRes. 1367 /// 1368 /// \pre setBasicBlock or setMI must have been called. 1369 /// \pre \p OldValRes must be a generic virtual register. 1370 /// \pre \p Addr must be a generic virtual register with pointer type. 1371 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1372 /// same type. 1373 /// 1374 /// \return a MachineInstrBuilder for the newly created instruction. 1375 MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, 1376 Register Val, MachineMemOperand &MMO); 1377 1378 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`. 1379 /// 1380 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and 1381 /// the original value. Puts the original value from \p Addr in \p OldValRes. 1382 /// 1383 /// \pre setBasicBlock or setMI must have been called. 1384 /// \pre \p OldValRes must be a generic virtual register. 1385 /// \pre \p Addr must be a generic virtual register with pointer type. 1386 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1387 /// same type. 1388 /// 1389 /// \return a MachineInstrBuilder for the newly created instruction. 1390 MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, 1391 Register Val, MachineMemOperand &MMO); 1392 1393 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`. 1394 /// 1395 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and 1396 /// the original value. Puts the original value from \p Addr in \p OldValRes. 1397 /// 1398 /// \pre setBasicBlock or setMI must have been called. 1399 /// \pre \p OldValRes must be a generic virtual register. 1400 /// \pre \p Addr must be a generic virtual register with pointer type. 1401 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1402 /// same type. 1403 /// 1404 /// \return a MachineInstrBuilder for the newly created instruction. 1405 MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, 1406 Register Val, MachineMemOperand &MMO); 1407 1408 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`. 1409 /// 1410 /// Atomically replace the value at \p Addr with the signed maximum of \p 1411 /// Val and the original value. Puts the original value from \p Addr in \p 1412 /// OldValRes. 1413 /// 1414 /// \pre setBasicBlock or setMI must have been called. 1415 /// \pre \p OldValRes must be a generic virtual register. 1416 /// \pre \p Addr must be a generic virtual register with pointer type. 1417 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1418 /// same type. 1419 /// 1420 /// \return a MachineInstrBuilder for the newly created instruction. 1421 MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, 1422 Register Val, MachineMemOperand &MMO); 1423 1424 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`. 1425 /// 1426 /// Atomically replace the value at \p Addr with the signed minimum of \p 1427 /// Val and the original value. Puts the original value from \p Addr in \p 1428 /// OldValRes. 1429 /// 1430 /// \pre setBasicBlock or setMI must have been called. 1431 /// \pre \p OldValRes must be a generic virtual register. 1432 /// \pre \p Addr must be a generic virtual register with pointer type. 1433 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1434 /// same type. 1435 /// 1436 /// \return a MachineInstrBuilder for the newly created instruction. 1437 MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, 1438 Register Val, MachineMemOperand &MMO); 1439 1440 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`. 1441 /// 1442 /// Atomically replace the value at \p Addr with the unsigned maximum of \p 1443 /// Val and the original value. Puts the original value from \p Addr in \p 1444 /// OldValRes. 1445 /// 1446 /// \pre setBasicBlock or setMI must have been called. 1447 /// \pre \p OldValRes must be a generic virtual register. 1448 /// \pre \p Addr must be a generic virtual register with pointer type. 1449 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1450 /// same type. 1451 /// 1452 /// \return a MachineInstrBuilder for the newly created instruction. 1453 MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, 1454 Register Val, MachineMemOperand &MMO); 1455 1456 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`. 1457 /// 1458 /// Atomically replace the value at \p Addr with the unsigned minimum of \p 1459 /// Val and the original value. Puts the original value from \p Addr in \p 1460 /// OldValRes. 1461 /// 1462 /// \pre setBasicBlock or setMI must have been called. 1463 /// \pre \p OldValRes must be a generic virtual register. 1464 /// \pre \p Addr must be a generic virtual register with pointer type. 1465 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1466 /// same type. 1467 /// 1468 /// \return a MachineInstrBuilder for the newly created instruction. 1469 MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, 1470 Register Val, MachineMemOperand &MMO); 1471 1472 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`. 1473 MachineInstrBuilder buildAtomicRMWFAdd( 1474 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, 1475 MachineMemOperand &MMO); 1476 1477 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`. 1478 MachineInstrBuilder buildAtomicRMWFSub( 1479 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, 1480 MachineMemOperand &MMO); 1481 1482 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO`. 1483 /// 1484 /// Atomically replace the value at \p Addr with the floating point maximum of 1485 /// \p Val and the original value. Puts the original value from \p Addr in \p 1486 /// OldValRes. 1487 /// 1488 /// \pre setBasicBlock or setMI must have been called. 1489 /// \pre \p OldValRes must be a generic virtual register. 1490 /// \pre \p Addr must be a generic virtual register with pointer type. 1491 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1492 /// same type. 1493 /// 1494 /// \return a MachineInstrBuilder for the newly created instruction. 1495 MachineInstrBuilder buildAtomicRMWFMax( 1496 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, 1497 MachineMemOperand &MMO); 1498 1499 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO`. 1500 /// 1501 /// Atomically replace the value at \p Addr with the floating point minimum of 1502 /// \p Val and the original value. Puts the original value from \p Addr in \p 1503 /// OldValRes. 1504 /// 1505 /// \pre setBasicBlock or setMI must have been called. 1506 /// \pre \p OldValRes must be a generic virtual register. 1507 /// \pre \p Addr must be a generic virtual register with pointer type. 1508 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the 1509 /// same type. 1510 /// 1511 /// \return a MachineInstrBuilder for the newly created instruction. 1512 MachineInstrBuilder buildAtomicRMWFMin( 1513 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, 1514 MachineMemOperand &MMO); 1515 1516 /// Build and insert `G_FENCE Ordering, Scope`. 1517 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope); 1518 1519 /// Build and insert \p Dst = G_FREEZE \p Src 1520 MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) { 1521 return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src}); 1522 } 1523 1524 /// Build and insert \p Res = G_BLOCK_ADDR \p BA 1525 /// 1526 /// G_BLOCK_ADDR computes the address of a basic block. 1527 /// 1528 /// \pre setBasicBlock or setMI must have been called. 1529 /// \pre \p Res must be a generic virtual register of a pointer type. 1530 /// 1531 /// \return The newly created instruction. 1532 MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA); 1533 1534 /// Build and insert \p Res = G_ADD \p Op0, \p Op1 1535 /// 1536 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1, 1537 /// truncated to their width. 1538 /// 1539 /// \pre setBasicBlock or setMI must have been called. 1540 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1541 /// with the same (scalar or vector) type). 1542 /// 1543 /// \return a MachineInstrBuilder for the newly created instruction. 1544 1545 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, 1546 const SrcOp &Src1, 1547 std::optional<unsigned> Flags = std::nullopt) { 1548 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags); 1549 } 1550 1551 /// Build and insert \p Res = G_SUB \p Op0, \p Op1 1552 /// 1553 /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and 1554 /// \p Op1, truncated to their width. 1555 /// 1556 /// \pre setBasicBlock or setMI must have been called. 1557 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1558 /// with the same (scalar or vector) type). 1559 /// 1560 /// \return a MachineInstrBuilder for the newly created instruction. 1561 1562 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, 1563 const SrcOp &Src1, 1564 std::optional<unsigned> Flags = std::nullopt) { 1565 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags); 1566 } 1567 1568 /// Build and insert \p Res = G_MUL \p Op0, \p Op1 1569 /// 1570 /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1, 1571 /// truncated to their width. 1572 /// 1573 /// \pre setBasicBlock or setMI must have been called. 1574 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1575 /// with the same (scalar or vector) type). 1576 /// 1577 /// \return a MachineInstrBuilder for the newly created instruction. 1578 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, 1579 const SrcOp &Src1, 1580 std::optional<unsigned> Flags = std::nullopt) { 1581 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags); 1582 } 1583 1584 MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, 1585 const SrcOp &Src1, 1586 std::optional<unsigned> Flags = std::nullopt) { 1587 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags); 1588 } 1589 1590 MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, 1591 const SrcOp &Src1, 1592 std::optional<unsigned> Flags = std::nullopt) { 1593 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags); 1594 } 1595 1596 /// Build and insert \p Res = G_UREM \p Op0, \p Op1 1597 MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, 1598 const SrcOp &Src1, 1599 std::optional<unsigned> Flags = std::nullopt) { 1600 return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags); 1601 } 1602 1603 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, 1604 const SrcOp &Src1, 1605 std::optional<unsigned> Flags = std::nullopt) { 1606 return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags); 1607 } 1608 1609 MachineInstrBuilder 1610 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, 1611 std::optional<unsigned> Flags = std::nullopt) { 1612 return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags); 1613 } 1614 1615 MachineInstrBuilder 1616 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, 1617 std::optional<unsigned> Flags = std::nullopt) { 1618 return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags); 1619 } 1620 1621 MachineInstrBuilder 1622 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, 1623 std::optional<unsigned> Flags = std::nullopt) { 1624 return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags); 1625 } 1626 1627 MachineInstrBuilder 1628 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, 1629 std::optional<unsigned> Flags = std::nullopt) { 1630 return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags); 1631 } 1632 1633 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, 1634 const SrcOp &Src1, 1635 std::optional<unsigned> Flags = std::nullopt) { 1636 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags); 1637 } 1638 1639 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, 1640 const SrcOp &Src1, 1641 std::optional<unsigned> Flags = std::nullopt) { 1642 return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags); 1643 } 1644 1645 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, 1646 const SrcOp &Src1, 1647 std::optional<unsigned> Flags = std::nullopt) { 1648 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags); 1649 } 1650 1651 /// Build and insert \p Res = G_AND \p Op0, \p Op1 1652 /// 1653 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p 1654 /// Op1. 1655 /// 1656 /// \pre setBasicBlock or setMI must have been called. 1657 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1658 /// with the same (scalar or vector) type). 1659 /// 1660 /// \return a MachineInstrBuilder for the newly created instruction. 1661 1662 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, 1663 const SrcOp &Src1) { 1664 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1}); 1665 } 1666 1667 /// Build and insert \p Res = G_OR \p Op0, \p Op1 1668 /// 1669 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p 1670 /// Op1. 1671 /// 1672 /// \pre setBasicBlock or setMI must have been called. 1673 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers 1674 /// with the same (scalar or vector) type). 1675 /// 1676 /// \return a MachineInstrBuilder for the newly created instruction. 1677 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, 1678 const SrcOp &Src1, 1679 std::optional<unsigned> Flags = std::nullopt) { 1680 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags); 1681 } 1682 1683 /// Build and insert \p Res = G_XOR \p Op0, \p Op1 1684 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, 1685 const SrcOp &Src1) { 1686 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1}); 1687 } 1688 1689 /// Build and insert a bitwise not, 1690 /// \p NegOne = G_CONSTANT -1 1691 /// \p Res = G_OR \p Op0, NegOne 1692 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) { 1693 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1); 1694 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne}); 1695 } 1696 1697 /// Build and insert integer negation 1698 /// \p Zero = G_CONSTANT 0 1699 /// \p Res = G_SUB Zero, \p Op0 1700 MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) { 1701 auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0); 1702 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Zero, Src0}); 1703 } 1704 1705 /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0 1706 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) { 1707 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0}); 1708 } 1709 1710 /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0 1711 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) { 1712 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0}); 1713 } 1714 1715 /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0 1716 MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { 1717 return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0}); 1718 } 1719 1720 /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0 1721 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) { 1722 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0}); 1723 } 1724 1725 /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0 1726 MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { 1727 return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0}); 1728 } 1729 1730 /// Build and insert \p Dst = G_BSWAP \p Src0 1731 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) { 1732 return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0}); 1733 } 1734 1735 /// Build and insert \p Res = G_FADD \p Op0, \p Op1 1736 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, 1737 const SrcOp &Src1, 1738 std::optional<unsigned> Flags = std::nullopt) { 1739 return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags); 1740 } 1741 1742 /// Build and insert \p Res = G_STRICT_FADD \p Op0, \p Op1 1743 MachineInstrBuilder 1744 buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, 1745 std::optional<unsigned> Flags = std::nullopt) { 1746 return buildInstr(TargetOpcode::G_STRICT_FADD, {Dst}, {Src0, Src1}, Flags); 1747 } 1748 1749 /// Build and insert \p Res = G_FSUB \p Op0, \p Op1 1750 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, 1751 const SrcOp &Src1, 1752 std::optional<unsigned> Flags = std::nullopt) { 1753 return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags); 1754 } 1755 1756 /// Build and insert \p Res = G_FDIV \p Op0, \p Op1 1757 MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, 1758 const SrcOp &Src1, 1759 std::optional<unsigned> Flags = std::nullopt) { 1760 return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags); 1761 } 1762 1763 /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2 1764 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, 1765 const SrcOp &Src1, const SrcOp &Src2, 1766 std::optional<unsigned> Flags = std::nullopt) { 1767 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags); 1768 } 1769 1770 /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2 1771 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, 1772 const SrcOp &Src1, const SrcOp &Src2, 1773 std::optional<unsigned> Flags = std::nullopt) { 1774 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags); 1775 } 1776 1777 /// Build and insert \p Res = G_FNEG \p Op0 1778 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, 1779 std::optional<unsigned> Flags = std::nullopt) { 1780 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags); 1781 } 1782 1783 /// Build and insert \p Res = G_FABS \p Op0 1784 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, 1785 std::optional<unsigned> Flags = std::nullopt) { 1786 return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags); 1787 } 1788 1789 /// Build and insert \p Dst = G_FCANONICALIZE \p Src0 1790 MachineInstrBuilder 1791 buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, 1792 std::optional<unsigned> Flags = std::nullopt) { 1793 return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags); 1794 } 1795 1796 /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0 1797 MachineInstrBuilder 1798 buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, 1799 std::optional<unsigned> Flags = std::nullopt) { 1800 return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags); 1801 } 1802 1803 /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1 1804 MachineInstrBuilder 1805 buildFFloor(const DstOp &Dst, const SrcOp &Src0, 1806 std::optional<unsigned> Flags = std::nullopt) { 1807 return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags); 1808 } 1809 1810 /// Build and insert \p Dst = G_FLOG \p Src 1811 MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, 1812 std::optional<unsigned> Flags = std::nullopt) { 1813 return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags); 1814 } 1815 1816 /// Build and insert \p Dst = G_FLOG2 \p Src 1817 MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, 1818 std::optional<unsigned> Flags = std::nullopt) { 1819 return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags); 1820 } 1821 1822 /// Build and insert \p Dst = G_FEXP2 \p Src 1823 MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, 1824 std::optional<unsigned> Flags = std::nullopt) { 1825 return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags); 1826 } 1827 1828 /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1 1829 MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, 1830 const SrcOp &Src1, 1831 std::optional<unsigned> Flags = std::nullopt) { 1832 return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags); 1833 } 1834 1835 /// Build and insert \p Dst = G_FLDEXP \p Src0, \p Src1 1836 MachineInstrBuilder 1837 buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, 1838 std::optional<unsigned> Flags = std::nullopt) { 1839 return buildInstr(TargetOpcode::G_FLDEXP, {Dst}, {Src0, Src1}, Flags); 1840 } 1841 1842 /// Build and insert \p Fract, \p Exp = G_FFREXP \p Src 1843 MachineInstrBuilder 1844 buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src, 1845 std::optional<unsigned> Flags = std::nullopt) { 1846 return buildInstr(TargetOpcode::G_FFREXP, {Fract, Exp}, {Src}, Flags); 1847 } 1848 1849 /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1 1850 MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, 1851 const SrcOp &Src1) { 1852 return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1}); 1853 } 1854 1855 /// Build and insert \p Res = G_UITOFP \p Src0 1856 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) { 1857 return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0}); 1858 } 1859 1860 /// Build and insert \p Res = G_SITOFP \p Src0 1861 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) { 1862 return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0}); 1863 } 1864 1865 /// Build and insert \p Res = G_FPTOUI \p Src0 1866 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) { 1867 return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0}); 1868 } 1869 1870 /// Build and insert \p Res = G_FPTOSI \p Src0 1871 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) { 1872 return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0}); 1873 } 1874 1875 /// Build and insert \p Dst = G_FRINT \p Src0, \p Src1 1876 MachineInstrBuilder buildFRint(const DstOp &Dst, const SrcOp &Src0, 1877 std::optional<unsigned> Flags = std::nullopt) { 1878 return buildInstr(TargetOpcode::G_FRINT, {Dst}, {Src0}, Flags); 1879 } 1880 1881 /// Build and insert \p Res = G_SMIN \p Op0, \p Op1 1882 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, 1883 const SrcOp &Src1) { 1884 return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1}); 1885 } 1886 1887 /// Build and insert \p Res = G_SMAX \p Op0, \p Op1 1888 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, 1889 const SrcOp &Src1) { 1890 return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1}); 1891 } 1892 1893 /// Build and insert \p Res = G_UMIN \p Op0, \p Op1 1894 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, 1895 const SrcOp &Src1) { 1896 return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1}); 1897 } 1898 1899 /// Build and insert \p Res = G_UMAX \p Op0, \p Op1 1900 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, 1901 const SrcOp &Src1) { 1902 return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1}); 1903 } 1904 1905 /// Build and insert \p Dst = G_ABS \p Src 1906 MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) { 1907 return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src}); 1908 } 1909 1910 /// Build and insert \p Res = G_JUMP_TABLE \p JTI 1911 /// 1912 /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by 1913 /// the jump table index \p JTI. 1914 /// 1915 /// \return a MachineInstrBuilder for the newly created instruction. 1916 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI); 1917 1918 /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn 1919 /// 1920 /// \p ScalarIn is the scalar accumulator input to start the sequential 1921 /// reduction operation of \p VecIn. 1922 MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, 1923 const SrcOp &ScalarIn, 1924 const SrcOp &VecIn) { 1925 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst}, 1926 {ScalarIn, {VecIn}}); 1927 } 1928 1929 /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn 1930 /// 1931 /// \p ScalarIn is the scalar accumulator input to start the sequential 1932 /// reduction operation of \p VecIn. 1933 MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, 1934 const SrcOp &ScalarIn, 1935 const SrcOp &VecIn) { 1936 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst}, 1937 {ScalarIn, {VecIn}}); 1938 } 1939 1940 /// Build and insert \p Res = G_VECREDUCE_FADD \p Src 1941 /// 1942 /// \p ScalarIn is the scalar accumulator input to the reduction operation of 1943 /// \p VecIn. 1944 MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, 1945 const SrcOp &ScalarIn, 1946 const SrcOp &VecIn) { 1947 return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn}); 1948 } 1949 1950 /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src 1951 /// 1952 /// \p ScalarIn is the scalar accumulator input to the reduction operation of 1953 /// \p VecIn. 1954 MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, 1955 const SrcOp &ScalarIn, 1956 const SrcOp &VecIn) { 1957 return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn}); 1958 } 1959 1960 /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src 1961 MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src) { 1962 return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src}); 1963 } 1964 1965 /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src 1966 MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src) { 1967 return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src}); 1968 } 1969 /// Build and insert \p Res = G_VECREDUCE_ADD \p Src 1970 MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src) { 1971 return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src}); 1972 } 1973 1974 /// Build and insert \p Res = G_VECREDUCE_MUL \p Src 1975 MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src) { 1976 return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src}); 1977 } 1978 1979 /// Build and insert \p Res = G_VECREDUCE_AND \p Src 1980 MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src) { 1981 return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src}); 1982 } 1983 1984 /// Build and insert \p Res = G_VECREDUCE_OR \p Src 1985 MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src) { 1986 return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src}); 1987 } 1988 1989 /// Build and insert \p Res = G_VECREDUCE_XOR \p Src 1990 MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src) { 1991 return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src}); 1992 } 1993 1994 /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src 1995 MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src) { 1996 return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src}); 1997 } 1998 1999 /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src 2000 MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src) { 2001 return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src}); 2002 } 2003 2004 /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src 2005 MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src) { 2006 return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src}); 2007 } 2008 2009 /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src 2010 MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src) { 2011 return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src}); 2012 } 2013 2014 /// Build and insert G_MEMCPY or G_MEMMOVE 2015 MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, 2016 const SrcOp &SrcPtr, 2017 const SrcOp &Size, 2018 MachineMemOperand &DstMMO, 2019 MachineMemOperand &SrcMMO) { 2020 auto MIB = buildInstr( 2021 Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)}); 2022 MIB.addMemOperand(&DstMMO); 2023 MIB.addMemOperand(&SrcMMO); 2024 return MIB; 2025 } 2026 2027 MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, 2028 const SrcOp &Size, MachineMemOperand &DstMMO, 2029 MachineMemOperand &SrcMMO) { 2030 return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size, 2031 DstMMO, SrcMMO); 2032 } 2033 2034 /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width. 2035 MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, 2036 const SrcOp &LSB, const SrcOp &Width) { 2037 return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width}); 2038 } 2039 2040 /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width. 2041 MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, 2042 const SrcOp &LSB, const SrcOp &Width) { 2043 return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width}); 2044 } 2045 2046 /// Build and insert \p Dst = G_ROTR \p Src, \p Amt 2047 MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, 2048 const SrcOp &Amt) { 2049 return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt}); 2050 } 2051 2052 /// Build and insert \p Dst = G_ROTL \p Src, \p Amt 2053 MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, 2054 const SrcOp &Amt) { 2055 return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt}); 2056 } 2057 2058 /// Build and insert \p Dst = G_BITREVERSE \p Src 2059 MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src) { 2060 return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src}); 2061 } 2062 2063 virtual MachineInstrBuilder 2064 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps, 2065 std::optional<unsigned> Flags = std::nullopt); 2066 }; 2067 2068 } // End namespace llvm. 2069 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H 2070