1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file declares the API of helper functions used throughout the 10 /// GlobalISel pipeline. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H 15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H 16 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/CodeGen/Register.h" 19 #include "llvm/Support/Alignment.h" 20 #include "llvm/Support/LowLevelTypeImpl.h" 21 #include <cstdint> 22 23 namespace llvm { 24 25 class AnalysisUsage; 26 class GISelKnownBits; 27 class MachineFunction; 28 class MachineInstr; 29 class MachineOperand; 30 class MachineOptimizationRemarkEmitter; 31 class MachineOptimizationRemarkMissed; 32 struct MachinePointerInfo; 33 class MachineRegisterInfo; 34 class MCInstrDesc; 35 class RegisterBankInfo; 36 class TargetInstrInfo; 37 class TargetLowering; 38 class TargetPassConfig; 39 class TargetRegisterInfo; 40 class TargetRegisterClass; 41 class ConstantFP; 42 class APFloat; 43 44 /// Try to constrain Reg to the specified register class. If this fails, 45 /// create a new virtual register in the correct class. 46 /// 47 /// \return The virtual register constrained to the right register class. 48 Register constrainRegToClass(MachineRegisterInfo &MRI, 49 const TargetInstrInfo &TII, 50 const RegisterBankInfo &RBI, Register Reg, 51 const TargetRegisterClass &RegClass); 52 53 /// Constrain the Register operand OpIdx, so that it is now constrained to the 54 /// TargetRegisterClass passed as an argument (RegClass). 55 /// If this fails, create a new virtual register in the correct class and insert 56 /// a COPY before \p InsertPt if it is a use or after if it is a definition. 57 /// In both cases, the function also updates the register of RegMo. The debug 58 /// location of \p InsertPt is used for the new copy. 59 /// 60 /// \return The virtual register constrained to the right register class. 61 Register constrainOperandRegClass(const MachineFunction &MF, 62 const TargetRegisterInfo &TRI, 63 MachineRegisterInfo &MRI, 64 const TargetInstrInfo &TII, 65 const RegisterBankInfo &RBI, 66 MachineInstr &InsertPt, 67 const TargetRegisterClass &RegClass, 68 MachineOperand &RegMO); 69 70 /// Try to constrain Reg so that it is usable by argument OpIdx of the provided 71 /// MCInstrDesc \p II. If this fails, create a new virtual register in the 72 /// correct class and insert a COPY before \p InsertPt if it is a use or after 73 /// if it is a definition. In both cases, the function also updates the register 74 /// of RegMo. 75 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...) 76 /// with RegClass obtained from the MCInstrDesc. The debug location of \p 77 /// InsertPt is used for the new copy. 78 /// 79 /// \return The virtual register constrained to the right register class. 80 Register constrainOperandRegClass(const MachineFunction &MF, 81 const TargetRegisterInfo &TRI, 82 MachineRegisterInfo &MRI, 83 const TargetInstrInfo &TII, 84 const RegisterBankInfo &RBI, 85 MachineInstr &InsertPt, const MCInstrDesc &II, 86 MachineOperand &RegMO, unsigned OpIdx); 87 88 /// Mutate the newly-selected instruction \p I to constrain its (possibly 89 /// generic) virtual register operands to the instruction's register class. 90 /// This could involve inserting COPYs before (for uses) or after (for defs). 91 /// This requires the number of operands to match the instruction description. 92 /// \returns whether operand regclass constraining succeeded. 93 /// 94 // FIXME: Not all instructions have the same number of operands. We should 95 // probably expose a constrain helper per operand and let the target selector 96 // constrain individual registers, like fast-isel. 97 bool constrainSelectedInstRegOperands(MachineInstr &I, 98 const TargetInstrInfo &TII, 99 const TargetRegisterInfo &TRI, 100 const RegisterBankInfo &RBI); 101 102 /// Check if DstReg can be replaced with SrcReg depending on the register 103 /// constraints. 104 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI); 105 106 /// Check whether an instruction \p MI is dead: it only defines dead virtual 107 /// registers, and doesn't have other side effects. 108 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI); 109 110 /// Report an ISel error as a missed optimization remark to the LLVMContext's 111 /// diagnostic stream. Set the FailedISel MachineFunction property. 112 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 113 MachineOptimizationRemarkEmitter &MORE, 114 MachineOptimizationRemarkMissed &R); 115 116 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 117 MachineOptimizationRemarkEmitter &MORE, 118 const char *PassName, StringRef Msg, 119 const MachineInstr &MI); 120 121 /// Report an ISel warning as a missed optimization remark to the LLVMContext's 122 /// diagnostic stream. 123 void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, 124 MachineOptimizationRemarkEmitter &MORE, 125 MachineOptimizationRemarkMissed &R); 126 127 /// If \p VReg is defined by a G_CONSTANT, return the corresponding value. 128 Optional<APInt> getConstantVRegVal(Register VReg, 129 const MachineRegisterInfo &MRI); 130 131 /// If \p VReg is defined by a G_CONSTANT fits in int64_t 132 /// returns it. 133 Optional<int64_t> getConstantVRegSExtVal(Register VReg, 134 const MachineRegisterInfo &MRI); 135 136 /// Simple struct used to hold a constant integer value and a virtual 137 /// register. 138 struct ValueAndVReg { 139 APInt Value; 140 Register VReg; 141 }; 142 /// If \p VReg is defined by a statically evaluable chain of 143 /// instructions rooted on a G_F/CONSTANT (\p LookThroughInstrs == true) 144 /// and that constant fits in int64_t, returns its value as well as the 145 /// virtual register defined by this G_F/CONSTANT. 146 /// When \p LookThroughInstrs == false this function behaves like 147 /// getConstantVRegVal. 148 /// When \p HandleFConstants == false the function bails on G_FCONSTANTs. 149 /// When \p LookThroughAnyExt == true the function treats G_ANYEXT same as 150 /// G_SEXT. 151 Optional<ValueAndVReg> 152 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, 153 bool LookThroughInstrs = true, 154 bool HandleFConstants = true, 155 bool LookThroughAnyExt = false); 156 const ConstantFP* getConstantFPVRegVal(Register VReg, 157 const MachineRegisterInfo &MRI); 158 159 /// See if Reg is defined by an single def instruction that is 160 /// Opcode. Also try to do trivial folding if it's a COPY with 161 /// same types. Returns null otherwise. 162 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg, 163 const MachineRegisterInfo &MRI); 164 165 /// Simple struct used to hold a Register value and the instruction which 166 /// defines it. 167 struct DefinitionAndSourceRegister { 168 MachineInstr *MI; 169 Register Reg; 170 }; 171 172 /// Find the def instruction for \p Reg, and underlying value Register folding 173 /// away any copies. 174 Optional<DefinitionAndSourceRegister> 175 getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI); 176 177 /// Find the def instruction for \p Reg, folding away any trivial copies. May 178 /// return nullptr if \p Reg is not a generic virtual register. 179 MachineInstr *getDefIgnoringCopies(Register Reg, 180 const MachineRegisterInfo &MRI); 181 182 /// Find the source register for \p Reg, folding away any trivial copies. It 183 /// will be an output register of the instruction that getDefIgnoringCopies 184 /// returns. May return an invalid register if \p Reg is not a generic virtual 185 /// register. 186 Register getSrcRegIgnoringCopies(Register Reg, 187 const MachineRegisterInfo &MRI); 188 189 /// Returns an APFloat from Val converted to the appropriate size. 190 APFloat getAPFloatFromSize(double Val, unsigned Size); 191 192 /// Modify analysis usage so it preserves passes required for the SelectionDAG 193 /// fallback. 194 void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU); 195 196 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1, 197 const Register Op2, 198 const MachineRegisterInfo &MRI); 199 200 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1, 201 uint64_t Imm, const MachineRegisterInfo &MRI); 202 203 /// Test if the given value is known to have exactly one bit set. This differs 204 /// from computeKnownBits in that it doesn't necessarily determine which bit is 205 /// set. 206 bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI, 207 GISelKnownBits *KnownBits = nullptr); 208 209 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true, 210 /// this returns if \p Val can be assumed to never be a signaling NaN. 211 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI, 212 bool SNaN = false); 213 214 /// Returns true if \p Val can be assumed to never be a signaling NaN. 215 inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) { 216 return isKnownNeverNaN(Val, MRI, true); 217 } 218 219 Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO); 220 221 /// Return a virtual register corresponding to the incoming argument register \p 222 /// PhysReg. This register is expected to have class \p RC, and optional type \p 223 /// RegTy. This assumes all references to the register will use the same type. 224 /// 225 /// If there is an existing live-in argument register, it will be returned. 226 /// This will also ensure there is a valid copy 227 Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, 228 MCRegister PhysReg, 229 const TargetRegisterClass &RC, 230 LLT RegTy = LLT()); 231 232 /// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the 233 /// number of vector elements or scalar bitwidth. The intent is a 234 /// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from 235 /// \p OrigTy elements, and unmerged into \p TargetTy 236 LLVM_READNONE 237 LLT getLCMType(LLT OrigTy, LLT TargetTy); 238 239 /// Return a type where the total size is the greatest common divisor of \p 240 /// OrigTy and \p TargetTy. This will try to either change the number of vector 241 /// elements, or bitwidth of scalars. The intent is the result type can be used 242 /// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some 243 /// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly 244 /// with intermediate casts) can re-form \p TargetTy. 245 /// 246 /// If these are vectors with different element types, this will try to produce 247 /// a vector with a compatible total size, but the element type of \p OrigTy. If 248 /// this can't be satisfied, this will produce a scalar smaller than the 249 /// original vector elements. 250 /// 251 /// In the worst case, this returns LLT::scalar(1) 252 LLVM_READNONE 253 LLT getGCDType(LLT OrigTy, LLT TargetTy); 254 255 /// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat. 256 /// If \p MI is not a splat, returns None. 257 Optional<int> getSplatIndex(MachineInstr &MI); 258 259 /// Returns a scalar constant of a G_BUILD_VECTOR splat if it exists. 260 Optional<int64_t> getBuildVectorConstantSplat(const MachineInstr &MI, 261 const MachineRegisterInfo &MRI); 262 263 /// Return true if the specified instruction is a G_BUILD_VECTOR or 264 /// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef. 265 bool isBuildVectorAllZeros(const MachineInstr &MI, 266 const MachineRegisterInfo &MRI); 267 268 /// Return true if the specified instruction is a G_BUILD_VECTOR or 269 /// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef. 270 bool isBuildVectorAllOnes(const MachineInstr &MI, 271 const MachineRegisterInfo &MRI); 272 273 /// Returns true if given the TargetLowering's boolean contents information, 274 /// the value \p Val contains a true value. 275 bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, 276 bool IsFP); 277 278 /// Returns an integer representing true, as defined by the 279 /// TargetBooleanContents. 280 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP); 281 } // End namespace llvm. 282 #endif 283