1 //===- LiveRangeEdit.h - Basic tools for split and spill --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // The LiveRangeEdit class represents changes done to a virtual register when it 10 // is spilled or split. 11 // 12 // The parent register is never changed. Instead, a number of new virtual 13 // registers are created and added to the newRegs vector. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_CODEGEN_LIVERANGEEDIT_H 18 #define LLVM_CODEGEN_LIVERANGEEDIT_H 19 20 #include "llvm/ADT/ArrayRef.h" 21 #include "llvm/ADT/None.h" 22 #include "llvm/ADT/SetVector.h" 23 #include "llvm/ADT/SmallPtrSet.h" 24 #include "llvm/ADT/SmallVector.h" 25 #include "llvm/CodeGen/LiveInterval.h" 26 #include "llvm/CodeGen/MachineBasicBlock.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/SlotIndexes.h" 30 #include "llvm/CodeGen/TargetSubtargetInfo.h" 31 #include <cassert> 32 33 namespace llvm { 34 35 class AAResults; 36 class LiveIntervals; 37 class MachineBlockFrequencyInfo; 38 class MachineInstr; 39 class MachineLoopInfo; 40 class MachineOperand; 41 class TargetInstrInfo; 42 class TargetRegisterInfo; 43 class VirtRegMap; 44 class VirtRegAuxInfo; 45 46 class LiveRangeEdit : private MachineRegisterInfo::Delegate { 47 public: 48 /// Callback methods for LiveRangeEdit owners. 49 class Delegate { 50 virtual void anchor(); 51 52 public: 53 virtual ~Delegate() = default; 54 55 /// Called immediately before erasing a dead machine instruction. 56 virtual void LRE_WillEraseInstruction(MachineInstr *MI) {} 57 58 /// Called when a virtual register is no longer used. Return false to defer 59 /// its deletion from LiveIntervals. 60 virtual bool LRE_CanEraseVirtReg(Register) { return true; } 61 62 /// Called before shrinking the live range of a virtual register. 63 virtual void LRE_WillShrinkVirtReg(Register) {} 64 65 /// Called after cloning a virtual register. 66 /// This is used for new registers representing connected components of Old. 67 virtual void LRE_DidCloneVirtReg(Register New, Register Old) {} 68 }; 69 70 private: 71 LiveInterval *Parent; 72 SmallVectorImpl<Register> &NewRegs; 73 MachineRegisterInfo &MRI; 74 LiveIntervals &LIS; 75 VirtRegMap *VRM; 76 const TargetInstrInfo &TII; 77 Delegate *const TheDelegate; 78 79 /// FirstNew - Index of the first register added to NewRegs. 80 const unsigned FirstNew; 81 82 /// ScannedRemattable - true when remattable values have been identified. 83 bool ScannedRemattable = false; 84 85 /// DeadRemats - The saved instructions which have already been dead after 86 /// rematerialization but not deleted yet -- to be done in postOptimization. 87 SmallPtrSet<MachineInstr *, 32> *DeadRemats; 88 89 /// Remattable - Values defined by remattable instructions as identified by 90 /// tii.isTriviallyReMaterializable(). 91 SmallPtrSet<const VNInfo *, 4> Remattable; 92 93 /// Rematted - Values that were actually rematted, and so need to have their 94 /// live range trimmed or entirely removed. 95 SmallPtrSet<const VNInfo *, 4> Rematted; 96 97 /// scanRemattable - Identify the Parent values that may rematerialize. 98 void scanRemattable(AAResults *aa); 99 100 /// foldAsLoad - If LI has a single use and a single def that can be folded as 101 /// a load, eliminate the register by folding the def into the use. 102 bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr *> &Dead); 103 104 using ToShrinkSet = SetVector<LiveInterval *, SmallVector<LiveInterval *, 8>, 105 SmallPtrSet<LiveInterval *, 8>>; 106 107 /// Helper for eliminateDeadDefs. 108 void eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink, 109 AAResults *AA); 110 111 /// MachineRegisterInfo callback to notify when new virtual 112 /// registers are created. 113 void MRI_NoteNewVirtualRegister(Register VReg) override; 114 115 /// Check if MachineOperand \p MO is a last use/kill either in the 116 /// main live range of \p LI or in one of the matching subregister ranges. 117 bool useIsKill(const LiveInterval &LI, const MachineOperand &MO) const; 118 119 /// Create a new empty interval based on OldReg. 120 LiveInterval &createEmptyIntervalFrom(Register OldReg, bool createSubRanges); 121 122 public: 123 /// Create a LiveRangeEdit for breaking down parent into smaller pieces. 124 /// @param parent The register being spilled or split. 125 /// @param newRegs List to receive any new registers created. This needn't be 126 /// empty initially, any existing registers are ignored. 127 /// @param MF The MachineFunction the live range edit is taking place in. 128 /// @param lis The collection of all live intervals in this function. 129 /// @param vrm Map of virtual registers to physical registers for this 130 /// function. If NULL, no virtual register map updates will 131 /// be done. This could be the case if called before Regalloc. 132 /// @param deadRemats The collection of all the instructions defining an 133 /// original reg and are dead after remat. 134 LiveRangeEdit(LiveInterval *parent, SmallVectorImpl<Register> &newRegs, 135 MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm, 136 Delegate *delegate = nullptr, 137 SmallPtrSet<MachineInstr *, 32> *deadRemats = nullptr) 138 : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis), 139 VRM(vrm), TII(*MF.getSubtarget().getInstrInfo()), TheDelegate(delegate), 140 FirstNew(newRegs.size()), DeadRemats(deadRemats) { 141 MRI.setDelegate(this); 142 } 143 144 ~LiveRangeEdit() override { MRI.resetDelegate(this); } 145 146 LiveInterval &getParent() const { 147 assert(Parent && "No parent LiveInterval"); 148 return *Parent; 149 } 150 151 Register getReg() const { return getParent().reg(); } 152 153 /// Iterator for accessing the new registers added by this edit. 154 using iterator = SmallVectorImpl<Register>::const_iterator; 155 iterator begin() const { return NewRegs.begin() + FirstNew; } 156 iterator end() const { return NewRegs.end(); } 157 unsigned size() const { return NewRegs.size() - FirstNew; } 158 bool empty() const { return size() == 0; } 159 Register get(unsigned idx) const { return NewRegs[idx + FirstNew]; } 160 161 /// pop_back - It allows LiveRangeEdit users to drop new registers. 162 /// The context is when an original def instruction of a register is 163 /// dead after rematerialization, we still want to keep it for following 164 /// rematerializations. We save the def instruction in DeadRemats, 165 /// and replace the original dst register with a new dummy register so 166 /// the live range of original dst register can be shrinked normally. 167 /// We don't want to allocate phys register for the dummy register, so 168 /// we want to drop it from the NewRegs set. 169 void pop_back() { NewRegs.pop_back(); } 170 171 ArrayRef<Register> regs() const { 172 return makeArrayRef(NewRegs).slice(FirstNew); 173 } 174 175 /// createFrom - Create a new virtual register based on OldReg. 176 Register createFrom(Register OldReg); 177 178 /// create - Create a new register with the same class and original slot as 179 /// parent. 180 LiveInterval &createEmptyInterval() { 181 return createEmptyIntervalFrom(getReg(), true); 182 } 183 184 Register create() { return createFrom(getReg()); } 185 186 /// anyRematerializable - Return true if any parent values may be 187 /// rematerializable. 188 /// This function must be called before any rematerialization is attempted. 189 bool anyRematerializable(AAResults *); 190 191 /// checkRematerializable - Manually add VNI to the list of rematerializable 192 /// values if DefMI may be rematerializable. 193 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, 194 AAResults *); 195 196 /// Remat - Information needed to rematerialize at a specific location. 197 struct Remat { 198 VNInfo *ParentVNI; // parent_'s value at the remat location. 199 MachineInstr *OrigMI = nullptr; // Instruction defining OrigVNI. It contains 200 // the real expr for remat. 201 202 explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI) {} 203 }; 204 205 /// allUsesAvailableAt - Return true if all registers used by OrigMI at 206 /// OrigIdx are also available with the same value at UseIdx. 207 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, 208 SlotIndex UseIdx) const; 209 210 /// canRematerializeAt - Determine if ParentVNI can be rematerialized at 211 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI. 212 /// When cheapAsAMove is set, only cheap remats are allowed. 213 bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, 214 bool cheapAsAMove); 215 216 /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an 217 /// instruction into MBB before MI. The new instruction is mapped, but 218 /// liveness is not updated. 219 /// Return the SlotIndex of the new instruction. 220 SlotIndex rematerializeAt(MachineBasicBlock &MBB, 221 MachineBasicBlock::iterator MI, unsigned DestReg, 222 const Remat &RM, const TargetRegisterInfo &, 223 bool Late = false); 224 225 /// markRematerialized - explicitly mark a value as rematerialized after doing 226 /// it manually. 227 void markRematerialized(const VNInfo *ParentVNI) { 228 Rematted.insert(ParentVNI); 229 } 230 231 /// didRematerialize - Return true if ParentVNI was rematerialized anywhere. 232 bool didRematerialize(const VNInfo *ParentVNI) const { 233 return Rematted.count(ParentVNI); 234 } 235 236 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try 237 /// to erase it from LIS. 238 void eraseVirtReg(Register Reg); 239 240 /// eliminateDeadDefs - Try to delete machine instructions that are now dead 241 /// (allDefsAreDead returns true). This may cause live intervals to be trimmed 242 /// and further dead efs to be eliminated. 243 /// RegsBeingSpilled lists registers currently being spilled by the register 244 /// allocator. These registers should not be split into new intervals 245 /// as currently those new intervals are not guaranteed to spill. 246 void eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead, 247 ArrayRef<Register> RegsBeingSpilled = None, 248 AAResults *AA = nullptr); 249 250 /// calculateRegClassAndHint - Recompute register class and hint for each new 251 /// register. 252 void calculateRegClassAndHint(MachineFunction &, VirtRegAuxInfo &); 253 }; 254 255 } // end namespace llvm 256 257 #endif // LLVM_CODEGEN_LIVERANGEEDIT_H 258