1 //===- LiveRangeEdit.h - Basic tools for split and spill --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // The LiveRangeEdit class represents changes done to a virtual register when it 10 // is spilled or split. 11 // 12 // The parent register is never changed. Instead, a number of new virtual 13 // registers are created and added to the newRegs vector. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_CODEGEN_LIVERANGEEDIT_H 18 #define LLVM_CODEGEN_LIVERANGEEDIT_H 19 20 #include "llvm/ADT/ArrayRef.h" 21 #include "llvm/ADT/SetVector.h" 22 #include "llvm/ADT/SmallPtrSet.h" 23 #include "llvm/ADT/SmallVector.h" 24 #include "llvm/CodeGen/LiveInterval.h" 25 #include "llvm/CodeGen/MachineBasicBlock.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/SlotIndexes.h" 29 #include "llvm/CodeGen/TargetSubtargetInfo.h" 30 #include <cassert> 31 32 namespace llvm { 33 34 class LiveIntervals; 35 class MachineInstr; 36 class MachineOperand; 37 class TargetInstrInfo; 38 class TargetRegisterInfo; 39 class VirtRegMap; 40 class VirtRegAuxInfo; 41 42 class LiveRangeEdit : private MachineRegisterInfo::Delegate { 43 public: 44 /// Callback methods for LiveRangeEdit owners. 45 class Delegate { 46 virtual void anchor(); 47 48 public: 49 virtual ~Delegate() = default; 50 51 /// Called immediately before erasing a dead machine instruction. 52 virtual void LRE_WillEraseInstruction(MachineInstr *MI) {} 53 54 /// Called when a virtual register is no longer used. Return false to defer 55 /// its deletion from LiveIntervals. 56 virtual bool LRE_CanEraseVirtReg(Register) { return true; } 57 58 /// Called before shrinking the live range of a virtual register. 59 virtual void LRE_WillShrinkVirtReg(Register) {} 60 61 /// Called after cloning a virtual register. 62 /// This is used for new registers representing connected components of Old. 63 virtual void LRE_DidCloneVirtReg(Register New, Register Old) {} 64 }; 65 66 private: 67 const LiveInterval *const Parent; 68 SmallVectorImpl<Register> &NewRegs; 69 MachineRegisterInfo &MRI; 70 LiveIntervals &LIS; 71 VirtRegMap *VRM; 72 const TargetInstrInfo &TII; 73 Delegate *const TheDelegate; 74 75 /// FirstNew - Index of the first register added to NewRegs. 76 const unsigned FirstNew; 77 78 /// ScannedRemattable - true when remattable values have been identified. 79 bool ScannedRemattable = false; 80 81 /// DeadRemats - The saved instructions which have already been dead after 82 /// rematerialization but not deleted yet -- to be done in postOptimization. 83 SmallPtrSet<MachineInstr *, 32> *DeadRemats; 84 85 /// Remattable - Values defined by remattable instructions as identified by 86 /// tii.isTriviallyReMaterializable(). 87 SmallPtrSet<const VNInfo *, 4> Remattable; 88 89 /// Rematted - Values that were actually rematted, and so need to have their 90 /// live range trimmed or entirely removed. 91 SmallPtrSet<const VNInfo *, 4> Rematted; 92 93 /// scanRemattable - Identify the Parent values that may rematerialize. 94 void scanRemattable(); 95 96 /// foldAsLoad - If LI has a single use and a single def that can be folded as 97 /// a load, eliminate the register by folding the def into the use. 98 bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr *> &Dead); 99 100 using ToShrinkSet = SetVector<LiveInterval *, SmallVector<LiveInterval *, 8>, 101 SmallPtrSet<LiveInterval *, 8>>; 102 103 /// Helper for eliminateDeadDefs. 104 void eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink); 105 106 /// MachineRegisterInfo callback to notify when new virtual 107 /// registers are created. 108 void MRI_NoteNewVirtualRegister(Register VReg) override; 109 110 /// Check if MachineOperand \p MO is a last use/kill either in the 111 /// main live range of \p LI or in one of the matching subregister ranges. 112 bool useIsKill(const LiveInterval &LI, const MachineOperand &MO) const; 113 114 /// Create a new empty interval based on OldReg. 115 LiveInterval &createEmptyIntervalFrom(Register OldReg, bool createSubRanges); 116 117 public: 118 /// Create a LiveRangeEdit for breaking down parent into smaller pieces. 119 /// @param parent The register being spilled or split. 120 /// @param newRegs List to receive any new registers created. This needn't be 121 /// empty initially, any existing registers are ignored. 122 /// @param MF The MachineFunction the live range edit is taking place in. 123 /// @param lis The collection of all live intervals in this function. 124 /// @param vrm Map of virtual registers to physical registers for this 125 /// function. If NULL, no virtual register map updates will 126 /// be done. This could be the case if called before Regalloc. 127 /// @param deadRemats The collection of all the instructions defining an 128 /// original reg and are dead after remat. 129 LiveRangeEdit(const LiveInterval *parent, SmallVectorImpl<Register> &newRegs, 130 MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm, 131 Delegate *delegate = nullptr, 132 SmallPtrSet<MachineInstr *, 32> *deadRemats = nullptr) 133 : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis), 134 VRM(vrm), TII(*MF.getSubtarget().getInstrInfo()), TheDelegate(delegate), 135 FirstNew(newRegs.size()), DeadRemats(deadRemats) { 136 MRI.addDelegate(this); 137 } 138 139 ~LiveRangeEdit() override { MRI.resetDelegate(this); } 140 141 const LiveInterval &getParent() const { 142 assert(Parent && "No parent LiveInterval"); 143 return *Parent; 144 } 145 146 Register getReg() const { return getParent().reg(); } 147 148 /// Iterator for accessing the new registers added by this edit. 149 using iterator = SmallVectorImpl<Register>::const_iterator; 150 iterator begin() const { return NewRegs.begin() + FirstNew; } 151 iterator end() const { return NewRegs.end(); } 152 unsigned size() const { return NewRegs.size() - FirstNew; } 153 bool empty() const { return size() == 0; } 154 Register get(unsigned idx) const { return NewRegs[idx + FirstNew]; } 155 156 /// pop_back - It allows LiveRangeEdit users to drop new registers. 157 /// The context is when an original def instruction of a register is 158 /// dead after rematerialization, we still want to keep it for following 159 /// rematerializations. We save the def instruction in DeadRemats, 160 /// and replace the original dst register with a new dummy register so 161 /// the live range of original dst register can be shrinked normally. 162 /// We don't want to allocate phys register for the dummy register, so 163 /// we want to drop it from the NewRegs set. 164 void pop_back() { NewRegs.pop_back(); } 165 166 ArrayRef<Register> regs() const { return ArrayRef(NewRegs).slice(FirstNew); } 167 168 /// createFrom - Create a new virtual register based on OldReg. 169 Register createFrom(Register OldReg); 170 171 /// create - Create a new register with the same class and original slot as 172 /// parent. 173 LiveInterval &createEmptyInterval() { 174 return createEmptyIntervalFrom(getReg(), true); 175 } 176 177 Register create() { return createFrom(getReg()); } 178 179 /// anyRematerializable - Return true if any parent values may be 180 /// rematerializable. 181 /// This function must be called before any rematerialization is attempted. 182 bool anyRematerializable(); 183 184 /// checkRematerializable - Manually add VNI to the list of rematerializable 185 /// values if DefMI may be rematerializable. 186 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI); 187 188 /// Remat - Information needed to rematerialize at a specific location. 189 struct Remat { 190 const VNInfo *const ParentVNI; // parent_'s value at the remat location. 191 MachineInstr *OrigMI = nullptr; // Instruction defining OrigVNI. It contains 192 // the real expr for remat. 193 194 explicit Remat(const VNInfo *ParentVNI) : ParentVNI(ParentVNI) {} 195 }; 196 197 /// allUsesAvailableAt - Return true if all registers used by OrigMI at 198 /// OrigIdx are also available with the same value at UseIdx. 199 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, 200 SlotIndex UseIdx) const; 201 202 /// canRematerializeAt - Determine if ParentVNI can be rematerialized at 203 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI. 204 /// When cheapAsAMove is set, only cheap remats are allowed. 205 bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, 206 bool cheapAsAMove); 207 208 /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an 209 /// instruction into MBB before MI. The new instruction is mapped, but 210 /// liveness is not updated. If ReplaceIndexMI is not null it will be replaced 211 /// by new MI in the index map. 212 /// Return the SlotIndex of the new instruction. 213 SlotIndex rematerializeAt(MachineBasicBlock &MBB, 214 MachineBasicBlock::iterator MI, unsigned DestReg, 215 const Remat &RM, const TargetRegisterInfo &, 216 bool Late = false, unsigned SubIdx = 0, 217 MachineInstr *ReplaceIndexMI = nullptr); 218 219 /// markRematerialized - explicitly mark a value as rematerialized after doing 220 /// it manually. 221 void markRematerialized(const VNInfo *ParentVNI) { 222 Rematted.insert(ParentVNI); 223 } 224 225 /// didRematerialize - Return true if ParentVNI was rematerialized anywhere. 226 bool didRematerialize(const VNInfo *ParentVNI) const { 227 return Rematted.count(ParentVNI); 228 } 229 230 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try 231 /// to erase it from LIS. 232 void eraseVirtReg(Register Reg); 233 234 /// eliminateDeadDefs - Try to delete machine instructions that are now dead 235 /// (allDefsAreDead returns true). This may cause live intervals to be trimmed 236 /// and further dead efs to be eliminated. 237 /// RegsBeingSpilled lists registers currently being spilled by the register 238 /// allocator. These registers should not be split into new intervals 239 /// as currently those new intervals are not guaranteed to spill. 240 void eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead, 241 ArrayRef<Register> RegsBeingSpilled = std::nullopt); 242 243 /// calculateRegClassAndHint - Recompute register class and hint for each new 244 /// register. 245 void calculateRegClassAndHint(MachineFunction &, VirtRegAuxInfo &); 246 }; 247 248 } // end namespace llvm 249 250 #endif // LLVM_CODEGEN_LIVERANGEEDIT_H 251