1 //===- MIParser.h - Machine Instructions Parser -----------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the function that parses the machine instructions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_MIRPARSER_MIPARSER_H
14 #define LLVM_CODEGEN_MIRPARSER_MIPARSER_H
15 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/StringMap.h"
18 #include "llvm/CodeGen/MachineMemOperand.h"
19 #include "llvm/CodeGen/Register.h"
20 #include "llvm/Support/Allocator.h"
21 #include "llvm/Support/SMLoc.h"
22 #include <utility>
23 
24 namespace llvm {
25 
26 class MachineBasicBlock;
27 class MachineFunction;
28 class MDNode;
29 class RegisterBank;
30 struct SlotMapping;
31 class SMDiagnostic;
32 class SourceMgr;
33 class StringRef;
34 class TargetRegisterClass;
35 class TargetSubtargetInfo;
36 
37 struct VRegInfo {
38   enum uint8_t {
39     UNKNOWN, NORMAL, GENERIC, REGBANK
40   } Kind = UNKNOWN;
41   bool Explicit = false; ///< VReg was explicitly specified in the .mir file.
42   union {
43     const TargetRegisterClass *RC;
44     const RegisterBank *RegBank;
45   } D;
46   Register VReg;
47   Register PreferredReg;
48 };
49 
50 using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
51 using Name2RegBankMap = StringMap<const RegisterBank *>;
52 
53 struct PerTargetMIParsingState {
54 private:
55   const TargetSubtargetInfo &Subtarget;
56 
57   /// Maps from instruction names to op codes.
58   StringMap<unsigned> Names2InstrOpCodes;
59 
60   /// Maps from register names to registers.
61   StringMap<Register> Names2Regs;
62 
63   /// Maps from register mask names to register masks.
64   StringMap<const uint32_t *> Names2RegMasks;
65 
66   /// Maps from subregister names to subregister indices.
67   StringMap<unsigned> Names2SubRegIndices;
68 
69   /// Maps from target index names to target indices.
70   StringMap<int> Names2TargetIndices;
71 
72   /// Maps from direct target flag names to the direct target flag values.
73   StringMap<unsigned> Names2DirectTargetFlags;
74 
75   /// Maps from direct target flag names to the bitmask target flag values.
76   StringMap<unsigned> Names2BitmaskTargetFlags;
77 
78   /// Maps from MMO target flag names to MMO target flag values.
79   StringMap<MachineMemOperand::Flags> Names2MMOTargetFlags;
80 
81   /// Maps from register class names to register classes.
82   Name2RegClassMap Names2RegClasses;
83 
84   /// Maps from register bank names to register banks.
85   Name2RegBankMap Names2RegBanks;
86 
87   void initNames2InstrOpCodes();
88   void initNames2Regs();
89   void initNames2RegMasks();
90   void initNames2SubRegIndices();
91   void initNames2TargetIndices();
92   void initNames2DirectTargetFlags();
93   void initNames2BitmaskTargetFlags();
94   void initNames2MMOTargetFlags();
95 
96   void initNames2RegClasses();
97   void initNames2RegBanks();
98 
99 public:
100   /// Try to convert an instruction name to an opcode. Return true if the
101   /// instruction name is invalid.
102   bool parseInstrName(StringRef InstrName, unsigned &OpCode);
103 
104   /// Try to convert a register name to a register number. Return true if the
105   /// register name is invalid.
106   bool getRegisterByName(StringRef RegName, Register &Reg);
107 
108   /// Check if the given identifier is a name of a register mask.
109   ///
110   /// Return null if the identifier isn't a register mask.
111   const uint32_t *getRegMask(StringRef Identifier);
112 
113   /// Check if the given identifier is a name of a subregister index.
114   ///
115   /// Return 0 if the name isn't a subregister index class.
116   unsigned getSubRegIndex(StringRef Name);
117 
118   /// Try to convert a name of target index to the corresponding target index.
119   ///
120   /// Return true if the name isn't a name of a target index.
121   bool getTargetIndex(StringRef Name, int &Index);
122 
123   /// Try to convert a name of a direct target flag to the corresponding
124   /// target flag.
125   ///
126   /// Return true if the name isn't a name of a direct flag.
127   bool getDirectTargetFlag(StringRef Name, unsigned &Flag);
128 
129   /// Try to convert a name of a bitmask target flag to the corresponding
130   /// target flag.
131   ///
132   /// Return true if the name isn't a name of a bitmask target flag.
133   bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag);
134 
135   /// Try to convert a name of a MachineMemOperand target flag to the
136   /// corresponding target flag.
137   ///
138   /// Return true if the name isn't a name of a target MMO flag.
139   bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag);
140 
141   /// Check if the given identifier is a name of a register class.
142   ///
143   /// Return null if the name isn't a register class.
144   const TargetRegisterClass *getRegClass(StringRef Name);
145 
146   /// Check if the given identifier is a name of a register bank.
147   ///
148   /// Return null if the name isn't a register bank.
149   const RegisterBank *getRegBank(StringRef Name);
150 
151   PerTargetMIParsingState(const TargetSubtargetInfo &STI)
152     : Subtarget(STI) {
153     initNames2RegClasses();
154     initNames2RegBanks();
155   }
156 
157   ~PerTargetMIParsingState() = default;
158 
159   void setTarget(const TargetSubtargetInfo &NewSubtarget);
160 };
161 
162 struct PerFunctionMIParsingState {
163   BumpPtrAllocator Allocator;
164   MachineFunction &MF;
165   SourceMgr *SM;
166   const SlotMapping &IRSlots;
167   PerTargetMIParsingState &Target;
168 
169   std::map<unsigned, TrackingMDNodeRef> MachineMetadataNodes;
170   std::map<unsigned, std::pair<TempMDTuple, SMLoc>> MachineForwardRefMDNodes;
171 
172   DenseMap<unsigned, MachineBasicBlock *> MBBSlots;
173   DenseMap<Register, VRegInfo *> VRegInfos;
174   StringMap<VRegInfo *> VRegInfosNamed;
175   DenseMap<unsigned, int> FixedStackObjectSlots;
176   DenseMap<unsigned, int> StackObjectSlots;
177   DenseMap<unsigned, unsigned> ConstantPoolSlots;
178   DenseMap<unsigned, unsigned> JumpTableSlots;
179 
180   /// Maps from slot numbers to function's unnamed values.
181   DenseMap<unsigned, const Value *> Slots2Values;
182 
183   PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM,
184                             const SlotMapping &IRSlots,
185                             PerTargetMIParsingState &Target);
186 
187   VRegInfo &getVRegInfo(Register Num);
188   VRegInfo &getVRegInfoNamed(StringRef RegName);
189   const Value *getIRValue(unsigned Slot);
190 };
191 
192 /// Parse the machine basic block definitions, and skip the machine
193 /// instructions.
194 ///
195 /// This function runs the first parsing pass on the machine function's body.
196 /// It parses only the machine basic block definitions and creates the machine
197 /// basic blocks in the given machine function.
198 ///
199 /// The machine instructions aren't parsed during the first pass because all
200 /// the machine basic blocks aren't defined yet - this makes it impossible to
201 /// resolve the machine basic block references.
202 ///
203 /// Return true if an error occurred.
204 bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS,
205                                        StringRef Src, SMDiagnostic &Error);
206 
207 /// Parse the machine instructions.
208 ///
209 /// This function runs the second parsing pass on the machine function's body.
210 /// It skips the machine basic block definitions and parses only the machine
211 /// instructions and basic block attributes like liveins and successors.
212 ///
213 /// The second parsing pass assumes that the first parsing pass already ran
214 /// on the given source string.
215 ///
216 /// Return true if an error occurred.
217 bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src,
218                               SMDiagnostic &Error);
219 
220 bool parseMBBReference(PerFunctionMIParsingState &PFS,
221                        MachineBasicBlock *&MBB, StringRef Src,
222                        SMDiagnostic &Error);
223 
224 bool parseRegisterReference(PerFunctionMIParsingState &PFS,
225                             Register &Reg, StringRef Src,
226                             SMDiagnostic &Error);
227 
228 bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg,
229                                  StringRef Src, SMDiagnostic &Error);
230 
231 bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,
232                                    VRegInfo *&Info, StringRef Src,
233                                    SMDiagnostic &Error);
234 
235 bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI,
236                                StringRef Src, SMDiagnostic &Error);
237 
238 bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src,
239                  SMDiagnostic &Error);
240 
241 bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src,
242                           SMRange SourceRange, SMDiagnostic &Error);
243 
244 } // end namespace llvm
245 
246 #endif // LLVM_CODEGEN_MIRPARSER_MIPARSER_H
247