1 //===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the MachineRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 14 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H 15 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/ADT/BitVector.h" 18 #include "llvm/ADT/IndexedMap.h" 19 #include "llvm/ADT/PointerUnion.h" 20 #include "llvm/ADT/SmallPtrSet.h" 21 #include "llvm/ADT/SmallVector.h" 22 #include "llvm/ADT/StringSet.h" 23 #include "llvm/ADT/iterator_range.h" 24 #include "llvm/CodeGen/MachineBasicBlock.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBundle.h" 27 #include "llvm/CodeGen/MachineOperand.h" 28 #include "llvm/CodeGen/RegisterBank.h" 29 #include "llvm/CodeGen/TargetRegisterInfo.h" 30 #include "llvm/CodeGen/TargetSubtargetInfo.h" 31 #include "llvm/MC/LaneBitmask.h" 32 #include <cassert> 33 #include <cstddef> 34 #include <cstdint> 35 #include <iterator> 36 #include <memory> 37 #include <utility> 38 #include <vector> 39 40 namespace llvm { 41 42 class PSetIterator; 43 44 /// Convenient type to represent either a register class or a register bank. 45 using RegClassOrRegBank = 46 PointerUnion<const TargetRegisterClass *, const RegisterBank *>; 47 48 /// MachineRegisterInfo - Keep track of information for virtual and physical 49 /// registers, including vreg register classes, use/def chains for registers, 50 /// etc. 51 class MachineRegisterInfo { 52 public: 53 class Delegate { 54 virtual void anchor(); 55 56 public: 57 virtual ~Delegate() = default; 58 59 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0; 60 virtual void MRI_NoteCloneVirtualRegister(Register NewReg, 61 Register SrcReg) { 62 MRI_NoteNewVirtualRegister(NewReg); 63 } 64 }; 65 66 private: 67 MachineFunction *MF; 68 SmallPtrSet<Delegate *, 1> TheDelegates; 69 70 /// True if subregister liveness is tracked. 71 const bool TracksSubRegLiveness; 72 73 /// VRegInfo - Information we keep for each virtual register. 74 /// 75 /// Each element in this list contains the register class of the vreg and the 76 /// start of the use/def list for the register. 77 IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>, 78 VirtReg2IndexFunctor> 79 VRegInfo; 80 81 /// Map for recovering vreg name from vreg number. 82 /// This map is used by the MIR Printer. 83 IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name; 84 85 /// StringSet that is used to unique vreg names. 86 StringSet<> VRegNames; 87 88 /// The flag is true upon \p UpdatedCSRs initialization 89 /// and false otherwise. 90 bool IsUpdatedCSRsInitialized = false; 91 92 /// Contains the updated callee saved register list. 93 /// As opposed to the static list defined in register info, 94 /// all registers that were disabled are removed from the list. 95 SmallVector<MCPhysReg, 16> UpdatedCSRs; 96 97 /// RegAllocHints - This vector records register allocation hints for 98 /// virtual registers. For each virtual register, it keeps a pair of hint 99 /// type and hints vector making up the allocation hints. Only the first 100 /// hint may be target specific, and in that case this is reflected by the 101 /// first member of the pair being non-zero. If the hinted register is 102 /// virtual, it means the allocator should prefer the physical register 103 /// allocated to it if any. 104 IndexedMap<std::pair<unsigned, SmallVector<Register, 4>>, 105 VirtReg2IndexFunctor> 106 RegAllocHints; 107 108 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 109 /// physical registers. 110 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists; 111 112 /// getRegUseDefListHead - Return the head pointer for the register use/def 113 /// list for the specified virtual or physical register. 114 MachineOperand *&getRegUseDefListHead(Register RegNo) { 115 if (RegNo.isVirtual()) 116 return VRegInfo[RegNo.id()].second; 117 return PhysRegUseDefLists[RegNo.id()]; 118 } 119 120 MachineOperand *getRegUseDefListHead(Register RegNo) const { 121 if (RegNo.isVirtual()) 122 return VRegInfo[RegNo.id()].second; 123 return PhysRegUseDefLists[RegNo.id()]; 124 } 125 126 /// Get the next element in the use-def chain. 127 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) { 128 assert(MO && MO->isReg() && "This is not a register operand!"); 129 return MO->Contents.Reg.Next; 130 } 131 132 /// UsedPhysRegMask - Additional used physregs including aliases. 133 /// This bit vector represents all the registers clobbered by function calls. 134 BitVector UsedPhysRegMask; 135 136 /// ReservedRegs - This is a bit vector of reserved registers. The target 137 /// may change its mind about which registers should be reserved. This 138 /// vector is the frozen set of reserved registers when register allocation 139 /// started. 140 BitVector ReservedRegs; 141 142 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>; 143 /// Map generic virtual registers to their low-level type. 144 VRegToTypeMap VRegToType; 145 146 /// Keep track of the physical registers that are live in to the function. 147 /// Live in values are typically arguments in registers. LiveIn values are 148 /// allowed to have virtual registers associated with them, stored in the 149 /// second element. 150 std::vector<std::pair<MCRegister, Register>> LiveIns; 151 152 public: 153 explicit MachineRegisterInfo(MachineFunction *MF); 154 MachineRegisterInfo(const MachineRegisterInfo &) = delete; 155 MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete; 156 157 const TargetRegisterInfo *getTargetRegisterInfo() const { 158 return MF->getSubtarget().getRegisterInfo(); 159 } 160 161 void resetDelegate(Delegate *delegate) { 162 // Ensure another delegate does not take over unless the current 163 // delegate first unattaches itself. 164 assert(TheDelegates.count(delegate) && 165 "Only an existing delegate can perform reset!"); 166 TheDelegates.erase(delegate); 167 } 168 169 void addDelegate(Delegate *delegate) { 170 assert(delegate && !TheDelegates.count(delegate) && 171 "Attempted to add null delegate, or to change it without " 172 "first resetting it!"); 173 174 TheDelegates.insert(delegate); 175 } 176 177 void noteNewVirtualRegister(Register Reg) { 178 for (auto *TheDelegate : TheDelegates) 179 TheDelegate->MRI_NoteNewVirtualRegister(Reg); 180 } 181 182 void noteCloneVirtualRegister(Register NewReg, Register SrcReg) { 183 for (auto *TheDelegate : TheDelegates) 184 TheDelegate->MRI_NoteCloneVirtualRegister(NewReg, SrcReg); 185 } 186 187 //===--------------------------------------------------------------------===// 188 // Function State 189 //===--------------------------------------------------------------------===// 190 191 // isSSA - Returns true when the machine function is in SSA form. Early 192 // passes require the machine function to be in SSA form where every virtual 193 // register has a single defining instruction. 194 // 195 // The TwoAddressInstructionPass and PHIElimination passes take the machine 196 // function out of SSA form when they introduce multiple defs per virtual 197 // register. 198 bool isSSA() const { 199 return MF->getProperties().hasProperty( 200 MachineFunctionProperties::Property::IsSSA); 201 } 202 203 // leaveSSA - Indicates that the machine function is no longer in SSA form. 204 void leaveSSA() { 205 MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA); 206 } 207 208 /// tracksLiveness - Returns true when tracking register liveness accurately. 209 /// (see MachineFUnctionProperties::Property description for details) 210 bool tracksLiveness() const { 211 return MF->getProperties().hasProperty( 212 MachineFunctionProperties::Property::TracksLiveness); 213 } 214 215 /// invalidateLiveness - Indicates that register liveness is no longer being 216 /// tracked accurately. 217 /// 218 /// This should be called by late passes that invalidate the liveness 219 /// information. 220 void invalidateLiveness() { 221 MF->getProperties().reset( 222 MachineFunctionProperties::Property::TracksLiveness); 223 } 224 225 /// Returns true if liveness for register class @p RC should be tracked at 226 /// the subregister level. 227 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const { 228 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs; 229 } 230 bool shouldTrackSubRegLiveness(Register VReg) const { 231 assert(VReg.isVirtual() && "Must pass a VReg"); 232 return shouldTrackSubRegLiveness(*getRegClass(VReg)); 233 } 234 bool subRegLivenessEnabled() const { 235 return TracksSubRegLiveness; 236 } 237 238 //===--------------------------------------------------------------------===// 239 // Register Info 240 //===--------------------------------------------------------------------===// 241 242 /// Returns true if the updated CSR list was initialized and false otherwise. 243 bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; } 244 245 /// Returns true if a register can be used as an argument to a function. 246 bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const; 247 248 /// Returns true if a register is a fixed register. 249 bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const; 250 251 /// Returns true if a register is a general purpose register. 252 bool isGeneralPurposeRegister(const MachineFunction &MF, 253 MCRegister Reg) const; 254 255 /// Disables the register from the list of CSRs. 256 /// I.e. the register will not appear as part of the CSR mask. 257 /// \see UpdatedCalleeSavedRegs. 258 void disableCalleeSavedRegister(MCRegister Reg); 259 260 /// Returns list of callee saved registers. 261 /// The function returns the updated CSR list (after taking into account 262 /// registers that are disabled from the CSR list). 263 const MCPhysReg *getCalleeSavedRegs() const; 264 265 /// Sets the updated Callee Saved Registers list. 266 /// Notice that it will override ant previously disabled/saved CSRs. 267 void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs); 268 269 // Strictly for use by MachineInstr.cpp. 270 void addRegOperandToUseList(MachineOperand *MO); 271 272 // Strictly for use by MachineInstr.cpp. 273 void removeRegOperandFromUseList(MachineOperand *MO); 274 275 // Strictly for use by MachineInstr.cpp. 276 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps); 277 278 /// Verify the sanity of the use list for Reg. 279 void verifyUseList(Register Reg) const; 280 281 /// Verify the use list of all registers. 282 void verifyUseLists() const; 283 284 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 285 /// and uses of a register within the MachineFunction that corresponds to this 286 /// MachineRegisterInfo object. 287 template<bool Uses, bool Defs, bool SkipDebug, 288 bool ByOperand, bool ByInstr, bool ByBundle> 289 class defusechain_iterator; 290 template<bool Uses, bool Defs, bool SkipDebug, 291 bool ByOperand, bool ByInstr, bool ByBundle> 292 class defusechain_instr_iterator; 293 294 // Make it a friend so it can access getNextOperandForReg(). 295 template<bool, bool, bool, bool, bool, bool> 296 friend class defusechain_iterator; 297 template<bool, bool, bool, bool, bool, bool> 298 friend class defusechain_instr_iterator; 299 300 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 301 /// register. 302 using reg_iterator = 303 defusechain_iterator<true, true, false, true, false, false>; 304 reg_iterator reg_begin(Register RegNo) const { 305 return reg_iterator(getRegUseDefListHead(RegNo)); 306 } 307 static reg_iterator reg_end() { return reg_iterator(nullptr); } 308 309 inline iterator_range<reg_iterator> reg_operands(Register Reg) const { 310 return make_range(reg_begin(Reg), reg_end()); 311 } 312 313 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses 314 /// of the specified register, stepping by MachineInstr. 315 using reg_instr_iterator = 316 defusechain_instr_iterator<true, true, false, false, true, false>; 317 reg_instr_iterator reg_instr_begin(Register RegNo) const { 318 return reg_instr_iterator(getRegUseDefListHead(RegNo)); 319 } 320 static reg_instr_iterator reg_instr_end() { 321 return reg_instr_iterator(nullptr); 322 } 323 324 inline iterator_range<reg_instr_iterator> 325 reg_instructions(Register Reg) const { 326 return make_range(reg_instr_begin(Reg), reg_instr_end()); 327 } 328 329 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses 330 /// of the specified register, stepping by bundle. 331 using reg_bundle_iterator = 332 defusechain_instr_iterator<true, true, false, false, false, true>; 333 reg_bundle_iterator reg_bundle_begin(Register RegNo) const { 334 return reg_bundle_iterator(getRegUseDefListHead(RegNo)); 335 } 336 static reg_bundle_iterator reg_bundle_end() { 337 return reg_bundle_iterator(nullptr); 338 } 339 340 inline iterator_range<reg_bundle_iterator> reg_bundles(Register Reg) const { 341 return make_range(reg_bundle_begin(Reg), reg_bundle_end()); 342 } 343 344 /// reg_empty - Return true if there are no instructions using or defining the 345 /// specified register (it may be live-in). 346 bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); } 347 348 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 349 /// of the specified register, skipping those marked as Debug. 350 using reg_nodbg_iterator = 351 defusechain_iterator<true, true, true, true, false, false>; 352 reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const { 353 return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 354 } 355 static reg_nodbg_iterator reg_nodbg_end() { 356 return reg_nodbg_iterator(nullptr); 357 } 358 359 inline iterator_range<reg_nodbg_iterator> 360 reg_nodbg_operands(Register Reg) const { 361 return make_range(reg_nodbg_begin(Reg), reg_nodbg_end()); 362 } 363 364 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk 365 /// all defs and uses of the specified register, stepping by MachineInstr, 366 /// skipping those marked as Debug. 367 using reg_instr_nodbg_iterator = 368 defusechain_instr_iterator<true, true, true, false, true, false>; 369 reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const { 370 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); 371 } 372 static reg_instr_nodbg_iterator reg_instr_nodbg_end() { 373 return reg_instr_nodbg_iterator(nullptr); 374 } 375 376 inline iterator_range<reg_instr_nodbg_iterator> 377 reg_nodbg_instructions(Register Reg) const { 378 return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end()); 379 } 380 381 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk 382 /// all defs and uses of the specified register, stepping by bundle, 383 /// skipping those marked as Debug. 384 using reg_bundle_nodbg_iterator = 385 defusechain_instr_iterator<true, true, true, false, false, true>; 386 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const { 387 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); 388 } 389 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() { 390 return reg_bundle_nodbg_iterator(nullptr); 391 } 392 393 inline iterator_range<reg_bundle_nodbg_iterator> 394 reg_nodbg_bundles(Register Reg) const { 395 return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end()); 396 } 397 398 /// reg_nodbg_empty - Return true if the only instructions using or defining 399 /// Reg are Debug instructions. 400 bool reg_nodbg_empty(Register RegNo) const { 401 return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 402 } 403 404 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 405 using def_iterator = 406 defusechain_iterator<false, true, false, true, false, false>; 407 def_iterator def_begin(Register RegNo) const { 408 return def_iterator(getRegUseDefListHead(RegNo)); 409 } 410 static def_iterator def_end() { return def_iterator(nullptr); } 411 412 inline iterator_range<def_iterator> def_operands(Register Reg) const { 413 return make_range(def_begin(Reg), def_end()); 414 } 415 416 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the 417 /// specified register, stepping by MachineInst. 418 using def_instr_iterator = 419 defusechain_instr_iterator<false, true, false, false, true, false>; 420 def_instr_iterator def_instr_begin(Register RegNo) const { 421 return def_instr_iterator(getRegUseDefListHead(RegNo)); 422 } 423 static def_instr_iterator def_instr_end() { 424 return def_instr_iterator(nullptr); 425 } 426 427 inline iterator_range<def_instr_iterator> 428 def_instructions(Register Reg) const { 429 return make_range(def_instr_begin(Reg), def_instr_end()); 430 } 431 432 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the 433 /// specified register, stepping by bundle. 434 using def_bundle_iterator = 435 defusechain_instr_iterator<false, true, false, false, false, true>; 436 def_bundle_iterator def_bundle_begin(Register RegNo) const { 437 return def_bundle_iterator(getRegUseDefListHead(RegNo)); 438 } 439 static def_bundle_iterator def_bundle_end() { 440 return def_bundle_iterator(nullptr); 441 } 442 443 inline iterator_range<def_bundle_iterator> def_bundles(Register Reg) const { 444 return make_range(def_bundle_begin(Reg), def_bundle_end()); 445 } 446 447 /// def_empty - Return true if there are no instructions defining the 448 /// specified register (it may be live-in). 449 bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); } 450 451 StringRef getVRegName(Register Reg) const { 452 return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : ""; 453 } 454 455 void insertVRegByName(StringRef Name, Register Reg) { 456 assert((Name.empty() || !VRegNames.contains(Name)) && 457 "Named VRegs Must be Unique."); 458 if (!Name.empty()) { 459 VRegNames.insert(Name); 460 VReg2Name.grow(Reg); 461 VReg2Name[Reg] = Name.str(); 462 } 463 } 464 465 /// Return true if there is exactly one operand defining the specified 466 /// register. 467 bool hasOneDef(Register RegNo) const { 468 return hasSingleElement(def_operands(RegNo)); 469 } 470 471 /// Returns the defining operand if there is exactly one operand defining the 472 /// specified register, otherwise nullptr. 473 MachineOperand *getOneDef(Register Reg) const { 474 def_iterator DI = def_begin(Reg); 475 if (DI == def_end()) // No defs. 476 return nullptr; 477 478 def_iterator OneDef = DI; 479 if (++DI == def_end()) 480 return &*OneDef; 481 return nullptr; // Multiple defs. 482 } 483 484 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 485 using use_iterator = 486 defusechain_iterator<true, false, false, true, false, false>; 487 use_iterator use_begin(Register RegNo) const { 488 return use_iterator(getRegUseDefListHead(RegNo)); 489 } 490 static use_iterator use_end() { return use_iterator(nullptr); } 491 492 inline iterator_range<use_iterator> use_operands(Register Reg) const { 493 return make_range(use_begin(Reg), use_end()); 494 } 495 496 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the 497 /// specified register, stepping by MachineInstr. 498 using use_instr_iterator = 499 defusechain_instr_iterator<true, false, false, false, true, false>; 500 use_instr_iterator use_instr_begin(Register RegNo) const { 501 return use_instr_iterator(getRegUseDefListHead(RegNo)); 502 } 503 static use_instr_iterator use_instr_end() { 504 return use_instr_iterator(nullptr); 505 } 506 507 inline iterator_range<use_instr_iterator> 508 use_instructions(Register Reg) const { 509 return make_range(use_instr_begin(Reg), use_instr_end()); 510 } 511 512 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the 513 /// specified register, stepping by bundle. 514 using use_bundle_iterator = 515 defusechain_instr_iterator<true, false, false, false, false, true>; 516 use_bundle_iterator use_bundle_begin(Register RegNo) const { 517 return use_bundle_iterator(getRegUseDefListHead(RegNo)); 518 } 519 static use_bundle_iterator use_bundle_end() { 520 return use_bundle_iterator(nullptr); 521 } 522 523 inline iterator_range<use_bundle_iterator> use_bundles(Register Reg) const { 524 return make_range(use_bundle_begin(Reg), use_bundle_end()); 525 } 526 527 /// use_empty - Return true if there are no instructions using the specified 528 /// register. 529 bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); } 530 531 /// hasOneUse - Return true if there is exactly one instruction using the 532 /// specified register. 533 bool hasOneUse(Register RegNo) const { 534 return hasSingleElement(use_operands(RegNo)); 535 } 536 537 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 538 /// specified register, skipping those marked as Debug. 539 using use_nodbg_iterator = 540 defusechain_iterator<true, false, true, true, false, false>; 541 use_nodbg_iterator use_nodbg_begin(Register RegNo) const { 542 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 543 } 544 static use_nodbg_iterator use_nodbg_end() { 545 return use_nodbg_iterator(nullptr); 546 } 547 548 inline iterator_range<use_nodbg_iterator> 549 use_nodbg_operands(Register Reg) const { 550 return make_range(use_nodbg_begin(Reg), use_nodbg_end()); 551 } 552 553 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk 554 /// all uses of the specified register, stepping by MachineInstr, skipping 555 /// those marked as Debug. 556 using use_instr_nodbg_iterator = 557 defusechain_instr_iterator<true, false, true, false, true, false>; 558 use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const { 559 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); 560 } 561 static use_instr_nodbg_iterator use_instr_nodbg_end() { 562 return use_instr_nodbg_iterator(nullptr); 563 } 564 565 inline iterator_range<use_instr_nodbg_iterator> 566 use_nodbg_instructions(Register Reg) const { 567 return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end()); 568 } 569 570 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk 571 /// all uses of the specified register, stepping by bundle, skipping 572 /// those marked as Debug. 573 using use_bundle_nodbg_iterator = 574 defusechain_instr_iterator<true, false, true, false, false, true>; 575 use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const { 576 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); 577 } 578 static use_bundle_nodbg_iterator use_bundle_nodbg_end() { 579 return use_bundle_nodbg_iterator(nullptr); 580 } 581 582 inline iterator_range<use_bundle_nodbg_iterator> 583 use_nodbg_bundles(Register Reg) const { 584 return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end()); 585 } 586 587 /// use_nodbg_empty - Return true if there are no non-Debug instructions 588 /// using the specified register. 589 bool use_nodbg_empty(Register RegNo) const { 590 return use_nodbg_begin(RegNo) == use_nodbg_end(); 591 } 592 593 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 594 /// use of the specified register. 595 bool hasOneNonDBGUse(Register RegNo) const; 596 597 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 598 /// instruction using the specified register. Said instruction may have 599 /// multiple uses. 600 bool hasOneNonDBGUser(Register RegNo) const; 601 602 603 /// hasAtMostUses - Return true if the given register has at most \p MaxUsers 604 /// non-debug user instructions. 605 bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const; 606 607 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 608 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 609 /// except that it also changes any definitions of the register as well. 610 /// 611 /// Note that it is usually necessary to first constrain ToReg's register 612 /// class and register bank to match the FromReg constraints using one of the 613 /// methods: 614 /// 615 /// constrainRegClass(ToReg, getRegClass(FromReg)) 616 /// constrainRegAttrs(ToReg, FromReg) 617 /// RegisterBankInfo::constrainGenericRegister(ToReg, 618 /// *MRI.getRegClass(FromReg), MRI) 619 /// 620 /// These functions will return a falsy result if the virtual registers have 621 /// incompatible constraints. 622 /// 623 /// Note that if ToReg is a physical register the function will replace and 624 /// apply sub registers to ToReg in order to obtain a final/proper physical 625 /// register. 626 void replaceRegWith(Register FromReg, Register ToReg); 627 628 /// getVRegDef - Return the machine instr that defines the specified virtual 629 /// register or null if none is found. This assumes that the code is in SSA 630 /// form, so there should only be one definition. 631 MachineInstr *getVRegDef(Register Reg) const; 632 633 /// getUniqueVRegDef - Return the unique machine instr that defines the 634 /// specified virtual register or null if none is found. If there are 635 /// multiple definitions or no definition, return null. 636 MachineInstr *getUniqueVRegDef(Register Reg) const; 637 638 /// clearKillFlags - Iterate over all the uses of the given register and 639 /// clear the kill flag from the MachineOperand. This function is used by 640 /// optimization passes which extend register lifetimes and need only 641 /// preserve conservative kill flag information. 642 void clearKillFlags(Register Reg) const; 643 644 void dumpUses(Register RegNo) const; 645 646 /// Returns true if PhysReg is unallocatable and constant throughout the 647 /// function. Writing to a constant register has no effect. 648 bool isConstantPhysReg(MCRegister PhysReg) const; 649 650 /// Get an iterator over the pressure sets affected by the given physical or 651 /// virtual register. If RegUnit is physical, it must be a register unit (from 652 /// MCRegUnitIterator). 653 PSetIterator getPressureSets(Register RegUnit) const; 654 655 //===--------------------------------------------------------------------===// 656 // Virtual Register Info 657 //===--------------------------------------------------------------------===// 658 659 /// Return the register class of the specified virtual register. 660 /// This shouldn't be used directly unless \p Reg has a register class. 661 /// \see getRegClassOrNull when this might happen. 662 const TargetRegisterClass *getRegClass(Register Reg) const { 663 assert(isa<const TargetRegisterClass *>(VRegInfo[Reg.id()].first) && 664 "Register class not set, wrong accessor"); 665 return cast<const TargetRegisterClass *>(VRegInfo[Reg.id()].first); 666 } 667 668 /// Return the register class of \p Reg, or null if Reg has not been assigned 669 /// a register class yet. 670 /// 671 /// \note A null register class can only happen when these two 672 /// conditions are met: 673 /// 1. Generic virtual registers are created. 674 /// 2. The machine function has not completely been through the 675 /// instruction selection process. 676 /// None of this condition is possible without GlobalISel for now. 677 /// In other words, if GlobalISel is not used or if the query happens after 678 /// the select pass, using getRegClass is safe. 679 const TargetRegisterClass *getRegClassOrNull(Register Reg) const { 680 const RegClassOrRegBank &Val = VRegInfo[Reg].first; 681 return dyn_cast_if_present<const TargetRegisterClass *>(Val); 682 } 683 684 /// Return the register bank of \p Reg, or null if Reg has not been assigned 685 /// a register bank or has been assigned a register class. 686 /// \note It is possible to get the register bank from the register class via 687 /// RegisterBankInfo::getRegBankFromRegClass. 688 const RegisterBank *getRegBankOrNull(Register Reg) const { 689 const RegClassOrRegBank &Val = VRegInfo[Reg].first; 690 return dyn_cast_if_present<const RegisterBank *>(Val); 691 } 692 693 /// Return the register bank or register class of \p Reg. 694 /// \note Before the register bank gets assigned (i.e., before the 695 /// RegBankSelect pass) \p Reg may not have either. 696 const RegClassOrRegBank &getRegClassOrRegBank(Register Reg) const { 697 return VRegInfo[Reg].first; 698 } 699 700 /// setRegClass - Set the register class of the specified virtual register. 701 void setRegClass(Register Reg, const TargetRegisterClass *RC); 702 703 /// Set the register bank to \p RegBank for \p Reg. 704 void setRegBank(Register Reg, const RegisterBank &RegBank); 705 706 void setRegClassOrRegBank(Register Reg, 707 const RegClassOrRegBank &RCOrRB){ 708 VRegInfo[Reg].first = RCOrRB; 709 } 710 711 /// constrainRegClass - Constrain the register class of the specified virtual 712 /// register to be a common subclass of RC and the current register class, 713 /// but only if the new class has at least MinNumRegs registers. Return the 714 /// new register class, or NULL if no such class exists. 715 /// This should only be used when the constraint is known to be trivial, like 716 /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 717 /// 718 /// \note Assumes that the register has a register class assigned. 719 /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's 720 /// InstructionSelect pass and constrainRegAttrs in every other pass, 721 /// including non-select passes of GlobalISel, instead. 722 const TargetRegisterClass *constrainRegClass(Register Reg, 723 const TargetRegisterClass *RC, 724 unsigned MinNumRegs = 0); 725 726 /// Constrain the register class or the register bank of the virtual register 727 /// \p Reg (and low-level type) to be a common subclass or a common bank of 728 /// both registers provided respectively (and a common low-level type). Do 729 /// nothing if any of the attributes (classes, banks, or low-level types) of 730 /// the registers are deemed incompatible, or if the resulting register will 731 /// have a class smaller than before and of size less than \p MinNumRegs. 732 /// Return true if such register attributes exist, false otherwise. 733 /// 734 /// \note Use this method instead of constrainRegClass and 735 /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG 736 /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively. 737 bool constrainRegAttrs(Register Reg, Register ConstrainingReg, 738 unsigned MinNumRegs = 0); 739 740 /// recomputeRegClass - Try to find a legal super-class of Reg's register 741 /// class that still satisfies the constraints from the instructions using 742 /// Reg. Returns true if Reg was upgraded. 743 /// 744 /// This method can be used after constraints have been removed from a 745 /// virtual register, for example after removing instructions or splitting 746 /// the live range. 747 bool recomputeRegClass(Register Reg); 748 749 /// createVirtualRegister - Create and return a new virtual register in the 750 /// function with the specified register class. 751 Register createVirtualRegister(const TargetRegisterClass *RegClass, 752 StringRef Name = ""); 753 754 /// Create and return a new virtual register in the function with the same 755 /// attributes as the given register. 756 Register cloneVirtualRegister(Register VReg, StringRef Name = ""); 757 758 /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic 759 /// (target independent) virtual register. 760 LLT getType(Register Reg) const { 761 if (Reg.isVirtual() && VRegToType.inBounds(Reg)) 762 return VRegToType[Reg]; 763 return LLT{}; 764 } 765 766 /// Set the low-level type of \p VReg to \p Ty. 767 void setType(Register VReg, LLT Ty); 768 769 /// Create and return a new generic virtual register with low-level 770 /// type \p Ty. 771 Register createGenericVirtualRegister(LLT Ty, StringRef Name = ""); 772 773 /// Remove all types associated to virtual registers (after instruction 774 /// selection and constraining of all generic virtual registers). 775 void clearVirtRegTypes(); 776 777 /// Creates a new virtual register that has no register class, register bank 778 /// or size assigned yet. This is only allowed to be used 779 /// temporarily while constructing machine instructions. Most operations are 780 /// undefined on an incomplete register until one of setRegClass(), 781 /// setRegBank() or setSize() has been called on it. 782 Register createIncompleteVirtualRegister(StringRef Name = ""); 783 784 /// getNumVirtRegs - Return the number of virtual registers created. 785 unsigned getNumVirtRegs() const { return VRegInfo.size(); } 786 787 /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 788 void clearVirtRegs(); 789 790 /// setRegAllocationHint - Specify a register allocation hint for the 791 /// specified virtual register. This is typically used by target, and in case 792 /// of an earlier hint it will be overwritten. 793 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) { 794 assert(VReg.isVirtual()); 795 RegAllocHints[VReg].first = Type; 796 RegAllocHints[VReg].second.clear(); 797 RegAllocHints[VReg].second.push_back(PrefReg); 798 } 799 800 /// addRegAllocationHint - Add a register allocation hint to the hints 801 /// vector for VReg. 802 void addRegAllocationHint(Register VReg, Register PrefReg) { 803 assert(VReg.isVirtual()); 804 RegAllocHints[VReg].second.push_back(PrefReg); 805 } 806 807 /// Specify the preferred (target independent) register allocation hint for 808 /// the specified virtual register. 809 void setSimpleHint(Register VReg, Register PrefReg) { 810 setRegAllocationHint(VReg, /*Type=*/0, PrefReg); 811 } 812 813 void clearSimpleHint(Register VReg) { 814 assert (!RegAllocHints[VReg].first && 815 "Expected to clear a non-target hint!"); 816 RegAllocHints[VReg].second.clear(); 817 } 818 819 /// getRegAllocationHint - Return the register allocation hint for the 820 /// specified virtual register. If there are many hints, this returns the 821 /// one with the greatest weight. 822 std::pair<unsigned, Register> getRegAllocationHint(Register VReg) const { 823 assert(VReg.isVirtual()); 824 Register BestHint = (RegAllocHints[VReg.id()].second.size() ? 825 RegAllocHints[VReg.id()].second[0] : Register()); 826 return {RegAllocHints[VReg.id()].first, BestHint}; 827 } 828 829 /// getSimpleHint - same as getRegAllocationHint except it will only return 830 /// a target independent hint. 831 Register getSimpleHint(Register VReg) const { 832 assert(VReg.isVirtual()); 833 std::pair<unsigned, Register> Hint = getRegAllocationHint(VReg); 834 return Hint.first ? Register() : Hint.second; 835 } 836 837 /// getRegAllocationHints - Return a reference to the vector of all 838 /// register allocation hints for VReg. 839 const std::pair<unsigned, SmallVector<Register, 4>> & 840 getRegAllocationHints(Register VReg) const { 841 assert(VReg.isVirtual()); 842 return RegAllocHints[VReg]; 843 } 844 845 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the 846 /// specified register as undefined which causes the DBG_VALUE to be 847 /// deleted during LiveDebugVariables analysis. 848 void markUsesInDebugValueAsUndef(Register Reg) const; 849 850 /// updateDbgUsersToReg - Update a collection of debug instructions 851 /// to refer to the designated register. 852 void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, 853 ArrayRef<MachineInstr *> Users) const { 854 // If this operand is a register, check whether it overlaps with OldReg. 855 // If it does, replace with NewReg. 856 auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) { 857 if (Op.isReg() && 858 getTargetRegisterInfo()->regsOverlap(Op.getReg(), OldReg)) 859 Op.setReg(NewReg); 860 }; 861 862 // Iterate through (possibly several) operands to DBG_VALUEs and update 863 // each. For DBG_PHIs, only one operand will be present. 864 for (MachineInstr *MI : Users) { 865 if (MI->isDebugValue()) { 866 for (auto &Op : MI->debug_operands()) 867 UpdateOp(Op); 868 assert(MI->hasDebugOperandForReg(NewReg) && 869 "Expected debug value to have some overlap with OldReg"); 870 } else if (MI->isDebugPHI()) { 871 UpdateOp(MI->getOperand(0)); 872 } else { 873 llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated"); 874 } 875 } 876 } 877 878 /// Return true if the specified register is modified in this function. 879 /// This checks that no defining machine operands exist for the register or 880 /// any of its aliases. Definitions found on functions marked noreturn are 881 /// ignored, to consider them pass 'true' for optional parameter 882 /// SkipNoReturnDef. The register is also considered modified when it is set 883 /// in the UsedPhysRegMask. 884 bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const; 885 886 /// Return true if the specified register is modified or read in this 887 /// function. This checks that no machine operands exist for the register or 888 /// any of its aliases. If SkipRegMaskTest is false, the register is 889 /// considered used when it is set in the UsedPhysRegMask. 890 bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest = false) const; 891 892 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. 893 /// This corresponds to the bit mask attached to register mask operands. 894 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { 895 UsedPhysRegMask.setBitsNotInMask(RegMask); 896 } 897 898 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; } 899 900 //===--------------------------------------------------------------------===// 901 // Reserved Register Info 902 //===--------------------------------------------------------------------===// 903 // 904 // The set of reserved registers must be invariant during register 905 // allocation. For example, the target cannot suddenly decide it needs a 906 // frame pointer when the register allocator has already used the frame 907 // pointer register for something else. 908 // 909 // These methods can be used by target hooks like hasFP() to avoid changing 910 // the reserved register set during register allocation. 911 912 /// freezeReservedRegs - Called by the register allocator to freeze the set 913 /// of reserved registers before allocation begins. 914 void freezeReservedRegs(const MachineFunction&); 915 916 /// reserveReg -- Mark a register as reserved so checks like isAllocatable 917 /// will not suggest using it. This should not be used during the middle 918 /// of a function walk, or when liveness info is available. 919 void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI) { 920 assert(reservedRegsFrozen() && 921 "Reserved registers haven't been frozen yet. "); 922 MCRegAliasIterator R(PhysReg, TRI, true); 923 924 for (; R.isValid(); ++R) 925 ReservedRegs.set(*R); 926 } 927 928 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 929 /// to ensure the set of reserved registers stays constant. 930 bool reservedRegsFrozen() const { 931 return !ReservedRegs.empty(); 932 } 933 934 /// canReserveReg - Returns true if PhysReg can be used as a reserved 935 /// register. Any register can be reserved before freezeReservedRegs() is 936 /// called. 937 bool canReserveReg(MCRegister PhysReg) const { 938 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 939 } 940 941 /// getReservedRegs - Returns a reference to the frozen set of reserved 942 /// registers. This method should always be preferred to calling 943 /// TRI::getReservedRegs() when possible. 944 const BitVector &getReservedRegs() const { 945 assert(reservedRegsFrozen() && 946 "Reserved registers haven't been frozen yet. " 947 "Use TRI::getReservedRegs()."); 948 return ReservedRegs; 949 } 950 951 /// isReserved - Returns true when PhysReg is a reserved register. 952 /// 953 /// Reserved registers may belong to an allocatable register class, but the 954 /// target has explicitly requested that they are not used. 955 bool isReserved(MCRegister PhysReg) const { 956 return getReservedRegs().test(PhysReg.id()); 957 } 958 959 /// Returns true when the given register unit is considered reserved. 960 /// 961 /// Register units are considered reserved when for at least one of their 962 /// root registers, the root register and all super registers are reserved. 963 /// This currently iterates the register hierarchy and may be slower than 964 /// expected. 965 bool isReservedRegUnit(unsigned Unit) const; 966 967 /// isAllocatable - Returns true when PhysReg belongs to an allocatable 968 /// register class and it hasn't been reserved. 969 /// 970 /// Allocatable registers may show up in the allocation order of some virtual 971 /// register, so a register allocator needs to track its liveness and 972 /// availability. 973 bool isAllocatable(MCRegister PhysReg) const { 974 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) && 975 !isReserved(PhysReg); 976 } 977 978 //===--------------------------------------------------------------------===// 979 // LiveIn Management 980 //===--------------------------------------------------------------------===// 981 982 /// addLiveIn - Add the specified register as a live-in. Note that it 983 /// is an error to add the same register to the same set more than once. 984 void addLiveIn(MCRegister Reg, Register vreg = Register()) { 985 LiveIns.push_back(std::make_pair(Reg, vreg)); 986 } 987 988 // Iteration support for the live-ins set. It's kept in sorted order 989 // by register number. 990 using livein_iterator = 991 std::vector<std::pair<MCRegister,Register>>::const_iterator; 992 livein_iterator livein_begin() const { return LiveIns.begin(); } 993 livein_iterator livein_end() const { return LiveIns.end(); } 994 bool livein_empty() const { return LiveIns.empty(); } 995 996 ArrayRef<std::pair<MCRegister, Register>> liveins() const { 997 return LiveIns; 998 } 999 1000 bool isLiveIn(Register Reg) const; 1001 1002 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 1003 /// corresponding live-in physical register. 1004 MCRegister getLiveInPhysReg(Register VReg) const; 1005 1006 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 1007 /// corresponding live-in virtual register. 1008 Register getLiveInVirtReg(MCRegister PReg) const; 1009 1010 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 1011 /// into the given entry block. 1012 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 1013 const TargetRegisterInfo &TRI, 1014 const TargetInstrInfo &TII); 1015 1016 /// Returns a mask covering all bits that can appear in lane masks of 1017 /// subregisters of the virtual register @p Reg. 1018 LaneBitmask getMaxLaneMaskForVReg(Register Reg) const; 1019 1020 /// defusechain_iterator - This class provides iterator support for machine 1021 /// operands in the function that use or define a specific register. If 1022 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 1023 /// returns defs. If neither are true then you are silly and it always 1024 /// returns end(). If SkipDebug is true it skips uses marked Debug 1025 /// when incrementing. 1026 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand, 1027 bool ByInstr, bool ByBundle> 1028 class defusechain_iterator { 1029 friend class MachineRegisterInfo; 1030 1031 public: 1032 using iterator_category = std::forward_iterator_tag; 1033 using value_type = MachineOperand; 1034 using difference_type = std::ptrdiff_t; 1035 using pointer = value_type *; 1036 using reference = value_type &; 1037 1038 private: 1039 MachineOperand *Op = nullptr; 1040 1041 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 1042 // If the first node isn't one we're interested in, advance to one that 1043 // we are interested in. 1044 if (op) { 1045 if ((!ReturnUses && op->isUse()) || 1046 (!ReturnDefs && op->isDef()) || 1047 (SkipDebug && op->isDebug())) 1048 advance(); 1049 } 1050 } 1051 1052 void advance() { 1053 assert(Op && "Cannot increment end iterator!"); 1054 Op = getNextOperandForReg(Op); 1055 1056 // All defs come before the uses, so stop def_iterator early. 1057 if (!ReturnUses) { 1058 if (Op) { 1059 if (Op->isUse()) 1060 Op = nullptr; 1061 else 1062 assert(!Op->isDebug() && "Can't have debug defs"); 1063 } 1064 } else { 1065 // If this is an operand we don't care about, skip it. 1066 while (Op && ((!ReturnDefs && Op->isDef()) || 1067 (SkipDebug && Op->isDebug()))) 1068 Op = getNextOperandForReg(Op); 1069 } 1070 } 1071 1072 public: 1073 defusechain_iterator() = default; 1074 1075 bool operator==(const defusechain_iterator &x) const { 1076 return Op == x.Op; 1077 } 1078 bool operator!=(const defusechain_iterator &x) const { 1079 return !operator==(x); 1080 } 1081 1082 /// atEnd - return true if this iterator is equal to reg_end() on the value. 1083 bool atEnd() const { return Op == nullptr; } 1084 1085 // Iterator traversal: forward iteration only 1086 defusechain_iterator &operator++() { // Preincrement 1087 assert(Op && "Cannot increment end iterator!"); 1088 if (ByOperand) 1089 advance(); 1090 else if (ByInstr) { 1091 MachineInstr *P = Op->getParent(); 1092 do { 1093 advance(); 1094 } while (Op && Op->getParent() == P); 1095 } else if (ByBundle) { 1096 MachineBasicBlock::instr_iterator P = 1097 getBundleStart(Op->getParent()->getIterator()); 1098 do { 1099 advance(); 1100 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P); 1101 } 1102 1103 return *this; 1104 } 1105 defusechain_iterator operator++(int) { // Postincrement 1106 defusechain_iterator tmp = *this; ++*this; return tmp; 1107 } 1108 1109 /// getOperandNo - Return the operand # of this MachineOperand in its 1110 /// MachineInstr. 1111 unsigned getOperandNo() const { 1112 assert(Op && "Cannot dereference end iterator!"); 1113 return Op - &Op->getParent()->getOperand(0); 1114 } 1115 1116 // Retrieve a reference to the current operand. 1117 MachineOperand &operator*() const { 1118 assert(Op && "Cannot dereference end iterator!"); 1119 return *Op; 1120 } 1121 1122 MachineOperand *operator->() const { 1123 assert(Op && "Cannot dereference end iterator!"); 1124 return Op; 1125 } 1126 }; 1127 1128 /// defusechain_iterator - This class provides iterator support for machine 1129 /// operands in the function that use or define a specific register. If 1130 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 1131 /// returns defs. If neither are true then you are silly and it always 1132 /// returns end(). If SkipDebug is true it skips uses marked Debug 1133 /// when incrementing. 1134 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand, 1135 bool ByInstr, bool ByBundle> 1136 class defusechain_instr_iterator { 1137 friend class MachineRegisterInfo; 1138 1139 public: 1140 using iterator_category = std::forward_iterator_tag; 1141 using value_type = MachineInstr; 1142 using difference_type = std::ptrdiff_t; 1143 using pointer = value_type *; 1144 using reference = value_type &; 1145 1146 private: 1147 MachineOperand *Op = nullptr; 1148 1149 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) { 1150 // If the first node isn't one we're interested in, advance to one that 1151 // we are interested in. 1152 if (op) { 1153 if ((!ReturnUses && op->isUse()) || 1154 (!ReturnDefs && op->isDef()) || 1155 (SkipDebug && op->isDebug())) 1156 advance(); 1157 } 1158 } 1159 1160 void advance() { 1161 assert(Op && "Cannot increment end iterator!"); 1162 Op = getNextOperandForReg(Op); 1163 1164 // All defs come before the uses, so stop def_iterator early. 1165 if (!ReturnUses) { 1166 if (Op) { 1167 if (Op->isUse()) 1168 Op = nullptr; 1169 else 1170 assert(!Op->isDebug() && "Can't have debug defs"); 1171 } 1172 } else { 1173 // If this is an operand we don't care about, skip it. 1174 while (Op && ((!ReturnDefs && Op->isDef()) || 1175 (SkipDebug && Op->isDebug()))) 1176 Op = getNextOperandForReg(Op); 1177 } 1178 } 1179 1180 public: 1181 defusechain_instr_iterator() = default; 1182 1183 bool operator==(const defusechain_instr_iterator &x) const { 1184 return Op == x.Op; 1185 } 1186 bool operator!=(const defusechain_instr_iterator &x) const { 1187 return !operator==(x); 1188 } 1189 1190 /// atEnd - return true if this iterator is equal to reg_end() on the value. 1191 bool atEnd() const { return Op == nullptr; } 1192 1193 // Iterator traversal: forward iteration only 1194 defusechain_instr_iterator &operator++() { // Preincrement 1195 assert(Op && "Cannot increment end iterator!"); 1196 if (ByOperand) 1197 advance(); 1198 else if (ByInstr) { 1199 MachineInstr *P = Op->getParent(); 1200 do { 1201 advance(); 1202 } while (Op && Op->getParent() == P); 1203 } else if (ByBundle) { 1204 MachineBasicBlock::instr_iterator P = 1205 getBundleStart(Op->getParent()->getIterator()); 1206 do { 1207 advance(); 1208 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P); 1209 } 1210 1211 return *this; 1212 } 1213 defusechain_instr_iterator operator++(int) { // Postincrement 1214 defusechain_instr_iterator tmp = *this; ++*this; return tmp; 1215 } 1216 1217 // Retrieve a reference to the current operand. 1218 MachineInstr &operator*() const { 1219 assert(Op && "Cannot dereference end iterator!"); 1220 if (ByBundle) 1221 return *getBundleStart(Op->getParent()->getIterator()); 1222 return *Op->getParent(); 1223 } 1224 1225 MachineInstr *operator->() const { return &operator*(); } 1226 }; 1227 }; 1228 1229 /// Iterate over the pressure sets affected by the given physical or virtual 1230 /// register. If Reg is physical, it must be a register unit (from 1231 /// MCRegUnitIterator). 1232 class PSetIterator { 1233 const int *PSet = nullptr; 1234 unsigned Weight = 0; 1235 1236 public: 1237 PSetIterator() = default; 1238 1239 PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) { 1240 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); 1241 if (RegUnit.isVirtual()) { 1242 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); 1243 PSet = TRI->getRegClassPressureSets(RC); 1244 Weight = TRI->getRegClassWeight(RC).RegWeight; 1245 } else { 1246 PSet = TRI->getRegUnitPressureSets(RegUnit); 1247 Weight = TRI->getRegUnitWeight(RegUnit); 1248 } 1249 if (*PSet == -1) 1250 PSet = nullptr; 1251 } 1252 1253 bool isValid() const { return PSet; } 1254 1255 unsigned getWeight() const { return Weight; } 1256 1257 unsigned operator*() const { return *PSet; } 1258 1259 void operator++() { 1260 assert(isValid() && "Invalid PSetIterator."); 1261 ++PSet; 1262 if (*PSet == -1) 1263 PSet = nullptr; 1264 } 1265 }; 1266 1267 inline PSetIterator 1268 MachineRegisterInfo::getPressureSets(Register RegUnit) const { 1269 return PSetIterator(RegUnit, this); 1270 } 1271 1272 } // end namespace llvm 1273 1274 #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H 1275