1 //===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the MachineRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 14 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H 15 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/ADT/BitVector.h" 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/ADT/IndexedMap.h" 20 #include "llvm/ADT/PointerUnion.h" 21 #include "llvm/ADT/SmallVector.h" 22 #include "llvm/ADT/StringSet.h" 23 #include "llvm/ADT/iterator_range.h" 24 #include "llvm/CodeGen/GlobalISel/RegisterBank.h" 25 #include "llvm/CodeGen/LowLevelType.h" 26 #include "llvm/CodeGen/MachineBasicBlock.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/MachineInstrBundle.h" 29 #include "llvm/CodeGen/MachineOperand.h" 30 #include "llvm/CodeGen/TargetRegisterInfo.h" 31 #include "llvm/CodeGen/TargetSubtargetInfo.h" 32 #include "llvm/MC/LaneBitmask.h" 33 #include <cassert> 34 #include <cstddef> 35 #include <cstdint> 36 #include <iterator> 37 #include <memory> 38 #include <utility> 39 #include <vector> 40 41 namespace llvm { 42 43 class PSetIterator; 44 45 /// Convenient type to represent either a register class or a register bank. 46 using RegClassOrRegBank = 47 PointerUnion<const TargetRegisterClass *, const RegisterBank *>; 48 49 /// MachineRegisterInfo - Keep track of information for virtual and physical 50 /// registers, including vreg register classes, use/def chains for registers, 51 /// etc. 52 class MachineRegisterInfo { 53 public: 54 class Delegate { 55 virtual void anchor(); 56 57 public: 58 virtual ~Delegate() = default; 59 60 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0; 61 }; 62 63 private: 64 MachineFunction *MF; 65 Delegate *TheDelegate = nullptr; 66 67 /// True if subregister liveness is tracked. 68 const bool TracksSubRegLiveness; 69 70 /// VRegInfo - Information we keep for each virtual register. 71 /// 72 /// Each element in this list contains the register class of the vreg and the 73 /// start of the use/def list for the register. 74 IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>, 75 VirtReg2IndexFunctor> 76 VRegInfo; 77 78 /// Map for recovering vreg name from vreg number. 79 /// This map is used by the MIR Printer. 80 IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name; 81 82 /// StringSet that is used to unique vreg names. 83 StringSet<> VRegNames; 84 85 /// The flag is true upon \p UpdatedCSRs initialization 86 /// and false otherwise. 87 bool IsUpdatedCSRsInitialized; 88 89 /// Contains the updated callee saved register list. 90 /// As opposed to the static list defined in register info, 91 /// all registers that were disabled are removed from the list. 92 SmallVector<MCPhysReg, 16> UpdatedCSRs; 93 94 /// RegAllocHints - This vector records register allocation hints for 95 /// virtual registers. For each virtual register, it keeps a pair of hint 96 /// type and hints vector making up the allocation hints. Only the first 97 /// hint may be target specific, and in that case this is reflected by the 98 /// first member of the pair being non-zero. If the hinted register is 99 /// virtual, it means the allocator should prefer the physical register 100 /// allocated to it if any. 101 IndexedMap<std::pair<unsigned, SmallVector<unsigned, 4>>, 102 VirtReg2IndexFunctor> RegAllocHints; 103 104 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 105 /// physical registers. 106 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists; 107 108 /// getRegUseDefListHead - Return the head pointer for the register use/def 109 /// list for the specified virtual or physical register. 110 MachineOperand *&getRegUseDefListHead(Register RegNo) { 111 if (RegNo.isVirtual()) 112 return VRegInfo[RegNo.id()].second; 113 return PhysRegUseDefLists[RegNo.id()]; 114 } 115 116 MachineOperand *getRegUseDefListHead(Register RegNo) const { 117 if (RegNo.isVirtual()) 118 return VRegInfo[RegNo.id()].second; 119 return PhysRegUseDefLists[RegNo.id()]; 120 } 121 122 /// Get the next element in the use-def chain. 123 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) { 124 assert(MO && MO->isReg() && "This is not a register operand!"); 125 return MO->Contents.Reg.Next; 126 } 127 128 /// UsedPhysRegMask - Additional used physregs including aliases. 129 /// This bit vector represents all the registers clobbered by function calls. 130 BitVector UsedPhysRegMask; 131 132 /// ReservedRegs - This is a bit vector of reserved registers. The target 133 /// may change its mind about which registers should be reserved. This 134 /// vector is the frozen set of reserved registers when register allocation 135 /// started. 136 BitVector ReservedRegs; 137 138 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>; 139 /// Map generic virtual registers to their low-level type. 140 VRegToTypeMap VRegToType; 141 142 /// Keep track of the physical registers that are live in to the function. 143 /// Live in values are typically arguments in registers. LiveIn values are 144 /// allowed to have virtual registers associated with them, stored in the 145 /// second element. 146 std::vector<std::pair<unsigned, unsigned>> LiveIns; 147 148 public: 149 explicit MachineRegisterInfo(MachineFunction *MF); 150 MachineRegisterInfo(const MachineRegisterInfo &) = delete; 151 MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete; 152 153 const TargetRegisterInfo *getTargetRegisterInfo() const { 154 return MF->getSubtarget().getRegisterInfo(); 155 } 156 157 void resetDelegate(Delegate *delegate) { 158 // Ensure another delegate does not take over unless the current 159 // delegate first unattaches itself. If we ever need to multicast 160 // notifications, we will need to change to using a list. 161 assert(TheDelegate == delegate && 162 "Only the current delegate can perform reset!"); 163 TheDelegate = nullptr; 164 } 165 166 void setDelegate(Delegate *delegate) { 167 assert(delegate && !TheDelegate && 168 "Attempted to set delegate to null, or to change it without " 169 "first resetting it!"); 170 171 TheDelegate = delegate; 172 } 173 174 //===--------------------------------------------------------------------===// 175 // Function State 176 //===--------------------------------------------------------------------===// 177 178 // isSSA - Returns true when the machine function is in SSA form. Early 179 // passes require the machine function to be in SSA form where every virtual 180 // register has a single defining instruction. 181 // 182 // The TwoAddressInstructionPass and PHIElimination passes take the machine 183 // function out of SSA form when they introduce multiple defs per virtual 184 // register. 185 bool isSSA() const { 186 return MF->getProperties().hasProperty( 187 MachineFunctionProperties::Property::IsSSA); 188 } 189 190 // leaveSSA - Indicates that the machine function is no longer in SSA form. 191 void leaveSSA() { 192 MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA); 193 } 194 195 /// tracksLiveness - Returns true when tracking register liveness accurately. 196 /// (see MachineFUnctionProperties::Property description for details) 197 bool tracksLiveness() const { 198 return MF->getProperties().hasProperty( 199 MachineFunctionProperties::Property::TracksLiveness); 200 } 201 202 /// invalidateLiveness - Indicates that register liveness is no longer being 203 /// tracked accurately. 204 /// 205 /// This should be called by late passes that invalidate the liveness 206 /// information. 207 void invalidateLiveness() { 208 MF->getProperties().reset( 209 MachineFunctionProperties::Property::TracksLiveness); 210 } 211 212 /// Returns true if liveness for register class @p RC should be tracked at 213 /// the subregister level. 214 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const { 215 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs; 216 } 217 bool shouldTrackSubRegLiveness(Register VReg) const { 218 assert(VReg.isVirtual() && "Must pass a VReg"); 219 return shouldTrackSubRegLiveness(*getRegClass(VReg)); 220 } 221 bool subRegLivenessEnabled() const { 222 return TracksSubRegLiveness; 223 } 224 225 //===--------------------------------------------------------------------===// 226 // Register Info 227 //===--------------------------------------------------------------------===// 228 229 /// Returns true if the updated CSR list was initialized and false otherwise. 230 bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; } 231 232 /// Disables the register from the list of CSRs. 233 /// I.e. the register will not appear as part of the CSR mask. 234 /// \see UpdatedCalleeSavedRegs. 235 void disableCalleeSavedRegister(unsigned Reg); 236 237 /// Returns list of callee saved registers. 238 /// The function returns the updated CSR list (after taking into account 239 /// registers that are disabled from the CSR list). 240 const MCPhysReg *getCalleeSavedRegs() const; 241 242 /// Sets the updated Callee Saved Registers list. 243 /// Notice that it will override ant previously disabled/saved CSRs. 244 void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs); 245 246 // Strictly for use by MachineInstr.cpp. 247 void addRegOperandToUseList(MachineOperand *MO); 248 249 // Strictly for use by MachineInstr.cpp. 250 void removeRegOperandFromUseList(MachineOperand *MO); 251 252 // Strictly for use by MachineInstr.cpp. 253 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps); 254 255 /// Verify the sanity of the use list for Reg. 256 void verifyUseList(unsigned Reg) const; 257 258 /// Verify the use list of all registers. 259 void verifyUseLists() const; 260 261 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 262 /// and uses of a register within the MachineFunction that corresponds to this 263 /// MachineRegisterInfo object. 264 template<bool Uses, bool Defs, bool SkipDebug, 265 bool ByOperand, bool ByInstr, bool ByBundle> 266 class defusechain_iterator; 267 template<bool Uses, bool Defs, bool SkipDebug, 268 bool ByOperand, bool ByInstr, bool ByBundle> 269 class defusechain_instr_iterator; 270 271 // Make it a friend so it can access getNextOperandForReg(). 272 template<bool, bool, bool, bool, bool, bool> 273 friend class defusechain_iterator; 274 template<bool, bool, bool, bool, bool, bool> 275 friend class defusechain_instr_iterator; 276 277 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 278 /// register. 279 using reg_iterator = 280 defusechain_iterator<true, true, false, true, false, false>; 281 reg_iterator reg_begin(unsigned RegNo) const { 282 return reg_iterator(getRegUseDefListHead(RegNo)); 283 } 284 static reg_iterator reg_end() { return reg_iterator(nullptr); } 285 286 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { 287 return make_range(reg_begin(Reg), reg_end()); 288 } 289 290 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses 291 /// of the specified register, stepping by MachineInstr. 292 using reg_instr_iterator = 293 defusechain_instr_iterator<true, true, false, false, true, false>; 294 reg_instr_iterator reg_instr_begin(unsigned RegNo) const { 295 return reg_instr_iterator(getRegUseDefListHead(RegNo)); 296 } 297 static reg_instr_iterator reg_instr_end() { 298 return reg_instr_iterator(nullptr); 299 } 300 301 inline iterator_range<reg_instr_iterator> 302 reg_instructions(unsigned Reg) const { 303 return make_range(reg_instr_begin(Reg), reg_instr_end()); 304 } 305 306 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses 307 /// of the specified register, stepping by bundle. 308 using reg_bundle_iterator = 309 defusechain_instr_iterator<true, true, false, false, false, true>; 310 reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const { 311 return reg_bundle_iterator(getRegUseDefListHead(RegNo)); 312 } 313 static reg_bundle_iterator reg_bundle_end() { 314 return reg_bundle_iterator(nullptr); 315 } 316 317 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { 318 return make_range(reg_bundle_begin(Reg), reg_bundle_end()); 319 } 320 321 /// reg_empty - Return true if there are no instructions using or defining the 322 /// specified register (it may be live-in). 323 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 324 325 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 326 /// of the specified register, skipping those marked as Debug. 327 using reg_nodbg_iterator = 328 defusechain_iterator<true, true, true, true, false, false>; 329 reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const { 330 return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 331 } 332 static reg_nodbg_iterator reg_nodbg_end() { 333 return reg_nodbg_iterator(nullptr); 334 } 335 336 inline iterator_range<reg_nodbg_iterator> 337 reg_nodbg_operands(unsigned Reg) const { 338 return make_range(reg_nodbg_begin(Reg), reg_nodbg_end()); 339 } 340 341 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk 342 /// all defs and uses of the specified register, stepping by MachineInstr, 343 /// skipping those marked as Debug. 344 using reg_instr_nodbg_iterator = 345 defusechain_instr_iterator<true, true, true, false, true, false>; 346 reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const { 347 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); 348 } 349 static reg_instr_nodbg_iterator reg_instr_nodbg_end() { 350 return reg_instr_nodbg_iterator(nullptr); 351 } 352 353 inline iterator_range<reg_instr_nodbg_iterator> 354 reg_nodbg_instructions(unsigned Reg) const { 355 return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end()); 356 } 357 358 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk 359 /// all defs and uses of the specified register, stepping by bundle, 360 /// skipping those marked as Debug. 361 using reg_bundle_nodbg_iterator = 362 defusechain_instr_iterator<true, true, true, false, false, true>; 363 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const { 364 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); 365 } 366 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() { 367 return reg_bundle_nodbg_iterator(nullptr); 368 } 369 370 inline iterator_range<reg_bundle_nodbg_iterator> 371 reg_nodbg_bundles(unsigned Reg) const { 372 return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end()); 373 } 374 375 /// reg_nodbg_empty - Return true if the only instructions using or defining 376 /// Reg are Debug instructions. 377 bool reg_nodbg_empty(Register RegNo) const { 378 return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 379 } 380 381 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 382 using def_iterator = 383 defusechain_iterator<false, true, false, true, false, false>; 384 def_iterator def_begin(unsigned RegNo) const { 385 return def_iterator(getRegUseDefListHead(RegNo)); 386 } 387 static def_iterator def_end() { return def_iterator(nullptr); } 388 389 inline iterator_range<def_iterator> def_operands(unsigned Reg) const { 390 return make_range(def_begin(Reg), def_end()); 391 } 392 393 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the 394 /// specified register, stepping by MachineInst. 395 using def_instr_iterator = 396 defusechain_instr_iterator<false, true, false, false, true, false>; 397 def_instr_iterator def_instr_begin(unsigned RegNo) const { 398 return def_instr_iterator(getRegUseDefListHead(RegNo)); 399 } 400 static def_instr_iterator def_instr_end() { 401 return def_instr_iterator(nullptr); 402 } 403 404 inline iterator_range<def_instr_iterator> 405 def_instructions(unsigned Reg) const { 406 return make_range(def_instr_begin(Reg), def_instr_end()); 407 } 408 409 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the 410 /// specified register, stepping by bundle. 411 using def_bundle_iterator = 412 defusechain_instr_iterator<false, true, false, false, false, true>; 413 def_bundle_iterator def_bundle_begin(unsigned RegNo) const { 414 return def_bundle_iterator(getRegUseDefListHead(RegNo)); 415 } 416 static def_bundle_iterator def_bundle_end() { 417 return def_bundle_iterator(nullptr); 418 } 419 420 inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const { 421 return make_range(def_bundle_begin(Reg), def_bundle_end()); 422 } 423 424 /// def_empty - Return true if there are no instructions defining the 425 /// specified register (it may be live-in). 426 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 427 428 StringRef getVRegName(unsigned Reg) const { 429 return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : ""; 430 } 431 432 void insertVRegByName(StringRef Name, unsigned Reg) { 433 assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) && 434 "Named VRegs Must be Unique."); 435 if (!Name.empty()) { 436 VRegNames.insert(Name); 437 VReg2Name.grow(Reg); 438 VReg2Name[Reg] = Name.str(); 439 } 440 } 441 442 /// Return true if there is exactly one operand defining the specified 443 /// register. 444 bool hasOneDef(unsigned RegNo) const { 445 def_iterator DI = def_begin(RegNo); 446 if (DI == def_end()) 447 return false; 448 return ++DI == def_end(); 449 } 450 451 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 452 using use_iterator = 453 defusechain_iterator<true, false, false, true, false, false>; 454 use_iterator use_begin(unsigned RegNo) const { 455 return use_iterator(getRegUseDefListHead(RegNo)); 456 } 457 static use_iterator use_end() { return use_iterator(nullptr); } 458 459 inline iterator_range<use_iterator> use_operands(unsigned Reg) const { 460 return make_range(use_begin(Reg), use_end()); 461 } 462 463 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the 464 /// specified register, stepping by MachineInstr. 465 using use_instr_iterator = 466 defusechain_instr_iterator<true, false, false, false, true, false>; 467 use_instr_iterator use_instr_begin(unsigned RegNo) const { 468 return use_instr_iterator(getRegUseDefListHead(RegNo)); 469 } 470 static use_instr_iterator use_instr_end() { 471 return use_instr_iterator(nullptr); 472 } 473 474 inline iterator_range<use_instr_iterator> 475 use_instructions(unsigned Reg) const { 476 return make_range(use_instr_begin(Reg), use_instr_end()); 477 } 478 479 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the 480 /// specified register, stepping by bundle. 481 using use_bundle_iterator = 482 defusechain_instr_iterator<true, false, false, false, false, true>; 483 use_bundle_iterator use_bundle_begin(unsigned RegNo) const { 484 return use_bundle_iterator(getRegUseDefListHead(RegNo)); 485 } 486 static use_bundle_iterator use_bundle_end() { 487 return use_bundle_iterator(nullptr); 488 } 489 490 inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const { 491 return make_range(use_bundle_begin(Reg), use_bundle_end()); 492 } 493 494 /// use_empty - Return true if there are no instructions using the specified 495 /// register. 496 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 497 498 /// hasOneUse - Return true if there is exactly one instruction using the 499 /// specified register. 500 bool hasOneUse(unsigned RegNo) const { 501 use_iterator UI = use_begin(RegNo); 502 if (UI == use_end()) 503 return false; 504 return ++UI == use_end(); 505 } 506 507 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 508 /// specified register, skipping those marked as Debug. 509 using use_nodbg_iterator = 510 defusechain_iterator<true, false, true, true, false, false>; 511 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 512 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 513 } 514 static use_nodbg_iterator use_nodbg_end() { 515 return use_nodbg_iterator(nullptr); 516 } 517 518 inline iterator_range<use_nodbg_iterator> 519 use_nodbg_operands(unsigned Reg) const { 520 return make_range(use_nodbg_begin(Reg), use_nodbg_end()); 521 } 522 523 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk 524 /// all uses of the specified register, stepping by MachineInstr, skipping 525 /// those marked as Debug. 526 using use_instr_nodbg_iterator = 527 defusechain_instr_iterator<true, false, true, false, true, false>; 528 use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const { 529 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); 530 } 531 static use_instr_nodbg_iterator use_instr_nodbg_end() { 532 return use_instr_nodbg_iterator(nullptr); 533 } 534 535 inline iterator_range<use_instr_nodbg_iterator> 536 use_nodbg_instructions(unsigned Reg) const { 537 return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end()); 538 } 539 540 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk 541 /// all uses of the specified register, stepping by bundle, skipping 542 /// those marked as Debug. 543 using use_bundle_nodbg_iterator = 544 defusechain_instr_iterator<true, false, true, false, false, true>; 545 use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const { 546 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); 547 } 548 static use_bundle_nodbg_iterator use_bundle_nodbg_end() { 549 return use_bundle_nodbg_iterator(nullptr); 550 } 551 552 inline iterator_range<use_bundle_nodbg_iterator> 553 use_nodbg_bundles(unsigned Reg) const { 554 return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end()); 555 } 556 557 /// use_nodbg_empty - Return true if there are no non-Debug instructions 558 /// using the specified register. 559 bool use_nodbg_empty(unsigned RegNo) const { 560 return use_nodbg_begin(RegNo) == use_nodbg_end(); 561 } 562 563 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 564 /// use of the specified register. 565 bool hasOneNonDBGUse(unsigned RegNo) const; 566 567 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 568 /// instruction using the specified register. Said instruction may have 569 /// multiple uses. 570 bool hasOneNonDBGUser(unsigned RegNo) const; 571 572 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 573 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 574 /// except that it also changes any definitions of the register as well. 575 /// 576 /// Note that it is usually necessary to first constrain ToReg's register 577 /// class and register bank to match the FromReg constraints using one of the 578 /// methods: 579 /// 580 /// constrainRegClass(ToReg, getRegClass(FromReg)) 581 /// constrainRegAttrs(ToReg, FromReg) 582 /// RegisterBankInfo::constrainGenericRegister(ToReg, 583 /// *MRI.getRegClass(FromReg), MRI) 584 /// 585 /// These functions will return a falsy result if the virtual registers have 586 /// incompatible constraints. 587 /// 588 /// Note that if ToReg is a physical register the function will replace and 589 /// apply sub registers to ToReg in order to obtain a final/proper physical 590 /// register. 591 void replaceRegWith(unsigned FromReg, unsigned ToReg); 592 593 /// getVRegDef - Return the machine instr that defines the specified virtual 594 /// register or null if none is found. This assumes that the code is in SSA 595 /// form, so there should only be one definition. 596 MachineInstr *getVRegDef(unsigned Reg) const; 597 598 /// getUniqueVRegDef - Return the unique machine instr that defines the 599 /// specified virtual register or null if none is found. If there are 600 /// multiple definitions or no definition, return null. 601 MachineInstr *getUniqueVRegDef(unsigned Reg) const; 602 603 /// clearKillFlags - Iterate over all the uses of the given register and 604 /// clear the kill flag from the MachineOperand. This function is used by 605 /// optimization passes which extend register lifetimes and need only 606 /// preserve conservative kill flag information. 607 void clearKillFlags(unsigned Reg) const; 608 609 void dumpUses(unsigned RegNo) const; 610 611 /// Returns true if PhysReg is unallocatable and constant throughout the 612 /// function. Writing to a constant register has no effect. 613 bool isConstantPhysReg(unsigned PhysReg) const; 614 615 /// Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg 616 /// returns true. This is a utility member function. 617 bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const; 618 619 /// Get an iterator over the pressure sets affected by the given physical or 620 /// virtual register. If RegUnit is physical, it must be a register unit (from 621 /// MCRegUnitIterator). 622 PSetIterator getPressureSets(unsigned RegUnit) const; 623 624 //===--------------------------------------------------------------------===// 625 // Virtual Register Info 626 //===--------------------------------------------------------------------===// 627 628 /// Return the register class of the specified virtual register. 629 /// This shouldn't be used directly unless \p Reg has a register class. 630 /// \see getRegClassOrNull when this might happen. 631 const TargetRegisterClass *getRegClass(Register Reg) const { 632 assert(VRegInfo[Reg.id()].first.is<const TargetRegisterClass *>() && 633 "Register class not set, wrong accessor"); 634 return VRegInfo[Reg.id()].first.get<const TargetRegisterClass *>(); 635 } 636 637 /// Return the register class of \p Reg, or null if Reg has not been assigned 638 /// a register class yet. 639 /// 640 /// \note A null register class can only happen when these two 641 /// conditions are met: 642 /// 1. Generic virtual registers are created. 643 /// 2. The machine function has not completely been through the 644 /// instruction selection process. 645 /// None of this condition is possible without GlobalISel for now. 646 /// In other words, if GlobalISel is not used or if the query happens after 647 /// the select pass, using getRegClass is safe. 648 const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const { 649 const RegClassOrRegBank &Val = VRegInfo[Reg].first; 650 return Val.dyn_cast<const TargetRegisterClass *>(); 651 } 652 653 /// Return the register bank of \p Reg, or null if Reg has not been assigned 654 /// a register bank or has been assigned a register class. 655 /// \note It is possible to get the register bank from the register class via 656 /// RegisterBankInfo::getRegBankFromRegClass. 657 const RegisterBank *getRegBankOrNull(unsigned Reg) const { 658 const RegClassOrRegBank &Val = VRegInfo[Reg].first; 659 return Val.dyn_cast<const RegisterBank *>(); 660 } 661 662 /// Return the register bank or register class of \p Reg. 663 /// \note Before the register bank gets assigned (i.e., before the 664 /// RegBankSelect pass) \p Reg may not have either. 665 const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const { 666 return VRegInfo[Reg].first; 667 } 668 669 /// setRegClass - Set the register class of the specified virtual register. 670 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 671 672 /// Set the register bank to \p RegBank for \p Reg. 673 void setRegBank(unsigned Reg, const RegisterBank &RegBank); 674 675 void setRegClassOrRegBank(unsigned Reg, 676 const RegClassOrRegBank &RCOrRB){ 677 VRegInfo[Reg].first = RCOrRB; 678 } 679 680 /// constrainRegClass - Constrain the register class of the specified virtual 681 /// register to be a common subclass of RC and the current register class, 682 /// but only if the new class has at least MinNumRegs registers. Return the 683 /// new register class, or NULL if no such class exists. 684 /// This should only be used when the constraint is known to be trivial, like 685 /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 686 /// 687 /// \note Assumes that the register has a register class assigned. 688 /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's 689 /// InstructionSelect pass and constrainRegAttrs in every other pass, 690 /// including non-select passes of GlobalISel, instead. 691 const TargetRegisterClass *constrainRegClass(unsigned Reg, 692 const TargetRegisterClass *RC, 693 unsigned MinNumRegs = 0); 694 695 /// Constrain the register class or the register bank of the virtual register 696 /// \p Reg (and low-level type) to be a common subclass or a common bank of 697 /// both registers provided respectively (and a common low-level type). Do 698 /// nothing if any of the attributes (classes, banks, or low-level types) of 699 /// the registers are deemed incompatible, or if the resulting register will 700 /// have a class smaller than before and of size less than \p MinNumRegs. 701 /// Return true if such register attributes exist, false otherwise. 702 /// 703 /// \note Use this method instead of constrainRegClass and 704 /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG 705 /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively. 706 bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg, 707 unsigned MinNumRegs = 0); 708 709 /// recomputeRegClass - Try to find a legal super-class of Reg's register 710 /// class that still satisfies the constraints from the instructions using 711 /// Reg. Returns true if Reg was upgraded. 712 /// 713 /// This method can be used after constraints have been removed from a 714 /// virtual register, for example after removing instructions or splitting 715 /// the live range. 716 bool recomputeRegClass(unsigned Reg); 717 718 /// createVirtualRegister - Create and return a new virtual register in the 719 /// function with the specified register class. 720 Register createVirtualRegister(const TargetRegisterClass *RegClass, 721 StringRef Name = ""); 722 723 /// Create and return a new virtual register in the function with the same 724 /// attributes as the given register. 725 Register cloneVirtualRegister(Register VReg, StringRef Name = ""); 726 727 /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic 728 /// (target independent) virtual register. 729 LLT getType(unsigned Reg) const { 730 if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg)) 731 return VRegToType[Reg]; 732 return LLT{}; 733 } 734 735 /// Set the low-level type of \p VReg to \p Ty. 736 void setType(unsigned VReg, LLT Ty); 737 738 /// Create and return a new generic virtual register with low-level 739 /// type \p Ty. 740 Register createGenericVirtualRegister(LLT Ty, StringRef Name = ""); 741 742 /// Remove all types associated to virtual registers (after instruction 743 /// selection and constraining of all generic virtual registers). 744 void clearVirtRegTypes(); 745 746 /// Creates a new virtual register that has no register class, register bank 747 /// or size assigned yet. This is only allowed to be used 748 /// temporarily while constructing machine instructions. Most operations are 749 /// undefined on an incomplete register until one of setRegClass(), 750 /// setRegBank() or setSize() has been called on it. 751 unsigned createIncompleteVirtualRegister(StringRef Name = ""); 752 753 /// getNumVirtRegs - Return the number of virtual registers created. 754 unsigned getNumVirtRegs() const { return VRegInfo.size(); } 755 756 /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 757 void clearVirtRegs(); 758 759 /// setRegAllocationHint - Specify a register allocation hint for the 760 /// specified virtual register. This is typically used by target, and in case 761 /// of an earlier hint it will be overwritten. 762 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { 763 assert(Register::isVirtualRegister(VReg)); 764 RegAllocHints[VReg].first = Type; 765 RegAllocHints[VReg].second.clear(); 766 RegAllocHints[VReg].second.push_back(PrefReg); 767 } 768 769 /// addRegAllocationHint - Add a register allocation hint to the hints 770 /// vector for VReg. 771 void addRegAllocationHint(unsigned VReg, unsigned PrefReg) { 772 assert(Register::isVirtualRegister(VReg)); 773 RegAllocHints[VReg].second.push_back(PrefReg); 774 } 775 776 /// Specify the preferred (target independent) register allocation hint for 777 /// the specified virtual register. 778 void setSimpleHint(unsigned VReg, unsigned PrefReg) { 779 setRegAllocationHint(VReg, /*Type=*/0, PrefReg); 780 } 781 782 void clearSimpleHint(unsigned VReg) { 783 assert (RegAllocHints[VReg].first == 0 && 784 "Expected to clear a non-target hint!"); 785 RegAllocHints[VReg].second.clear(); 786 } 787 788 /// getRegAllocationHint - Return the register allocation hint for the 789 /// specified virtual register. If there are many hints, this returns the 790 /// one with the greatest weight. 791 std::pair<unsigned, unsigned> 792 getRegAllocationHint(Register VReg) const { 793 assert(VReg.isVirtual()); 794 unsigned BestHint = (RegAllocHints[VReg.id()].second.size() ? 795 RegAllocHints[VReg.id()].second[0] : 0); 796 return std::pair<unsigned, unsigned>(RegAllocHints[VReg.id()].first, 797 BestHint); 798 } 799 800 /// getSimpleHint - same as getRegAllocationHint except it will only return 801 /// a target independent hint. 802 Register getSimpleHint(Register VReg) const { 803 assert(VReg.isVirtual()); 804 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg); 805 return Hint.first ? 0 : Hint.second; 806 } 807 808 /// getRegAllocationHints - Return a reference to the vector of all 809 /// register allocation hints for VReg. 810 const std::pair<unsigned, SmallVector<unsigned, 4>> 811 &getRegAllocationHints(unsigned VReg) const { 812 assert(Register::isVirtualRegister(VReg)); 813 return RegAllocHints[VReg]; 814 } 815 816 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the 817 /// specified register as undefined which causes the DBG_VALUE to be 818 /// deleted during LiveDebugVariables analysis. 819 void markUsesInDebugValueAsUndef(unsigned Reg) const; 820 821 /// updateDbgUsersToReg - Update a collection of DBG_VALUE instructions 822 /// to refer to the designated register. 823 void updateDbgUsersToReg(unsigned Reg, 824 ArrayRef<MachineInstr*> Users) const { 825 for (MachineInstr *MI : Users) { 826 assert(MI->isDebugInstr()); 827 assert(MI->getOperand(0).isReg()); 828 MI->getOperand(0).setReg(Reg); 829 } 830 } 831 832 /// Return true if the specified register is modified in this function. 833 /// This checks that no defining machine operands exist for the register or 834 /// any of its aliases. Definitions found on functions marked noreturn are 835 /// ignored, to consider them pass 'true' for optional parameter 836 /// SkipNoReturnDef. The register is also considered modified when it is set 837 /// in the UsedPhysRegMask. 838 bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const; 839 840 /// Return true if the specified register is modified or read in this 841 /// function. This checks that no machine operands exist for the register or 842 /// any of its aliases. The register is also considered used when it is set 843 /// in the UsedPhysRegMask. 844 bool isPhysRegUsed(unsigned PhysReg) const; 845 846 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. 847 /// This corresponds to the bit mask attached to register mask operands. 848 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { 849 UsedPhysRegMask.setBitsNotInMask(RegMask); 850 } 851 852 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; } 853 854 //===--------------------------------------------------------------------===// 855 // Reserved Register Info 856 //===--------------------------------------------------------------------===// 857 // 858 // The set of reserved registers must be invariant during register 859 // allocation. For example, the target cannot suddenly decide it needs a 860 // frame pointer when the register allocator has already used the frame 861 // pointer register for something else. 862 // 863 // These methods can be used by target hooks like hasFP() to avoid changing 864 // the reserved register set during register allocation. 865 866 /// freezeReservedRegs - Called by the register allocator to freeze the set 867 /// of reserved registers before allocation begins. 868 void freezeReservedRegs(const MachineFunction&); 869 870 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 871 /// to ensure the set of reserved registers stays constant. 872 bool reservedRegsFrozen() const { 873 return !ReservedRegs.empty(); 874 } 875 876 /// canReserveReg - Returns true if PhysReg can be used as a reserved 877 /// register. Any register can be reserved before freezeReservedRegs() is 878 /// called. 879 bool canReserveReg(unsigned PhysReg) const { 880 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 881 } 882 883 /// getReservedRegs - Returns a reference to the frozen set of reserved 884 /// registers. This method should always be preferred to calling 885 /// TRI::getReservedRegs() when possible. 886 const BitVector &getReservedRegs() const { 887 assert(reservedRegsFrozen() && 888 "Reserved registers haven't been frozen yet. " 889 "Use TRI::getReservedRegs()."); 890 return ReservedRegs; 891 } 892 893 /// isReserved - Returns true when PhysReg is a reserved register. 894 /// 895 /// Reserved registers may belong to an allocatable register class, but the 896 /// target has explicitly requested that they are not used. 897 bool isReserved(Register PhysReg) const { 898 return getReservedRegs().test(PhysReg.id()); 899 } 900 901 /// Returns true when the given register unit is considered reserved. 902 /// 903 /// Register units are considered reserved when for at least one of their 904 /// root registers, the root register and all super registers are reserved. 905 /// This currently iterates the register hierarchy and may be slower than 906 /// expected. 907 bool isReservedRegUnit(unsigned Unit) const; 908 909 /// isAllocatable - Returns true when PhysReg belongs to an allocatable 910 /// register class and it hasn't been reserved. 911 /// 912 /// Allocatable registers may show up in the allocation order of some virtual 913 /// register, so a register allocator needs to track its liveness and 914 /// availability. 915 bool isAllocatable(unsigned PhysReg) const { 916 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) && 917 !isReserved(PhysReg); 918 } 919 920 //===--------------------------------------------------------------------===// 921 // LiveIn Management 922 //===--------------------------------------------------------------------===// 923 924 /// addLiveIn - Add the specified register as a live-in. Note that it 925 /// is an error to add the same register to the same set more than once. 926 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 927 LiveIns.push_back(std::make_pair(Reg, vreg)); 928 } 929 930 // Iteration support for the live-ins set. It's kept in sorted order 931 // by register number. 932 using livein_iterator = 933 std::vector<std::pair<unsigned,unsigned>>::const_iterator; 934 livein_iterator livein_begin() const { return LiveIns.begin(); } 935 livein_iterator livein_end() const { return LiveIns.end(); } 936 bool livein_empty() const { return LiveIns.empty(); } 937 938 ArrayRef<std::pair<unsigned, unsigned>> liveins() const { 939 return LiveIns; 940 } 941 942 bool isLiveIn(unsigned Reg) const; 943 944 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 945 /// corresponding live-in physical register. 946 unsigned getLiveInPhysReg(unsigned VReg) const; 947 948 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 949 /// corresponding live-in physical register. 950 unsigned getLiveInVirtReg(unsigned PReg) const; 951 952 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 953 /// into the given entry block. 954 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 955 const TargetRegisterInfo &TRI, 956 const TargetInstrInfo &TII); 957 958 /// Returns a mask covering all bits that can appear in lane masks of 959 /// subregisters of the virtual register @p Reg. 960 LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const; 961 962 /// defusechain_iterator - This class provides iterator support for machine 963 /// operands in the function that use or define a specific register. If 964 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 965 /// returns defs. If neither are true then you are silly and it always 966 /// returns end(). If SkipDebug is true it skips uses marked Debug 967 /// when incrementing. 968 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug, 969 bool ByOperand, bool ByInstr, bool ByBundle> 970 class defusechain_iterator 971 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 972 friend class MachineRegisterInfo; 973 974 MachineOperand *Op = nullptr; 975 976 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 977 // If the first node isn't one we're interested in, advance to one that 978 // we are interested in. 979 if (op) { 980 if ((!ReturnUses && op->isUse()) || 981 (!ReturnDefs && op->isDef()) || 982 (SkipDebug && op->isDebug())) 983 advance(); 984 } 985 } 986 987 void advance() { 988 assert(Op && "Cannot increment end iterator!"); 989 Op = getNextOperandForReg(Op); 990 991 // All defs come before the uses, so stop def_iterator early. 992 if (!ReturnUses) { 993 if (Op) { 994 if (Op->isUse()) 995 Op = nullptr; 996 else 997 assert(!Op->isDebug() && "Can't have debug defs"); 998 } 999 } else { 1000 // If this is an operand we don't care about, skip it. 1001 while (Op && ((!ReturnDefs && Op->isDef()) || 1002 (SkipDebug && Op->isDebug()))) 1003 Op = getNextOperandForReg(Op); 1004 } 1005 } 1006 1007 public: 1008 using reference = std::iterator<std::forward_iterator_tag, 1009 MachineInstr, ptrdiff_t>::reference; 1010 using pointer = std::iterator<std::forward_iterator_tag, 1011 MachineInstr, ptrdiff_t>::pointer; 1012 1013 defusechain_iterator() = default; 1014 1015 bool operator==(const defusechain_iterator &x) const { 1016 return Op == x.Op; 1017 } 1018 bool operator!=(const defusechain_iterator &x) const { 1019 return !operator==(x); 1020 } 1021 1022 /// atEnd - return true if this iterator is equal to reg_end() on the value. 1023 bool atEnd() const { return Op == nullptr; } 1024 1025 // Iterator traversal: forward iteration only 1026 defusechain_iterator &operator++() { // Preincrement 1027 assert(Op && "Cannot increment end iterator!"); 1028 if (ByOperand) 1029 advance(); 1030 else if (ByInstr) { 1031 MachineInstr *P = Op->getParent(); 1032 do { 1033 advance(); 1034 } while (Op && Op->getParent() == P); 1035 } else if (ByBundle) { 1036 MachineBasicBlock::instr_iterator P = 1037 getBundleStart(Op->getParent()->getIterator()); 1038 do { 1039 advance(); 1040 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P); 1041 } 1042 1043 return *this; 1044 } 1045 defusechain_iterator operator++(int) { // Postincrement 1046 defusechain_iterator tmp = *this; ++*this; return tmp; 1047 } 1048 1049 /// getOperandNo - Return the operand # of this MachineOperand in its 1050 /// MachineInstr. 1051 unsigned getOperandNo() const { 1052 assert(Op && "Cannot dereference end iterator!"); 1053 return Op - &Op->getParent()->getOperand(0); 1054 } 1055 1056 // Retrieve a reference to the current operand. 1057 MachineOperand &operator*() const { 1058 assert(Op && "Cannot dereference end iterator!"); 1059 return *Op; 1060 } 1061 1062 MachineOperand *operator->() const { 1063 assert(Op && "Cannot dereference end iterator!"); 1064 return Op; 1065 } 1066 }; 1067 1068 /// defusechain_iterator - This class provides iterator support for machine 1069 /// operands in the function that use or define a specific register. If 1070 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 1071 /// returns defs. If neither are true then you are silly and it always 1072 /// returns end(). If SkipDebug is true it skips uses marked Debug 1073 /// when incrementing. 1074 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug, 1075 bool ByOperand, bool ByInstr, bool ByBundle> 1076 class defusechain_instr_iterator 1077 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 1078 friend class MachineRegisterInfo; 1079 1080 MachineOperand *Op = nullptr; 1081 1082 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) { 1083 // If the first node isn't one we're interested in, advance to one that 1084 // we are interested in. 1085 if (op) { 1086 if ((!ReturnUses && op->isUse()) || 1087 (!ReturnDefs && op->isDef()) || 1088 (SkipDebug && op->isDebug())) 1089 advance(); 1090 } 1091 } 1092 1093 void advance() { 1094 assert(Op && "Cannot increment end iterator!"); 1095 Op = getNextOperandForReg(Op); 1096 1097 // All defs come before the uses, so stop def_iterator early. 1098 if (!ReturnUses) { 1099 if (Op) { 1100 if (Op->isUse()) 1101 Op = nullptr; 1102 else 1103 assert(!Op->isDebug() && "Can't have debug defs"); 1104 } 1105 } else { 1106 // If this is an operand we don't care about, skip it. 1107 while (Op && ((!ReturnDefs && Op->isDef()) || 1108 (SkipDebug && Op->isDebug()))) 1109 Op = getNextOperandForReg(Op); 1110 } 1111 } 1112 1113 public: 1114 using reference = std::iterator<std::forward_iterator_tag, 1115 MachineInstr, ptrdiff_t>::reference; 1116 using pointer = std::iterator<std::forward_iterator_tag, 1117 MachineInstr, ptrdiff_t>::pointer; 1118 1119 defusechain_instr_iterator() = default; 1120 1121 bool operator==(const defusechain_instr_iterator &x) const { 1122 return Op == x.Op; 1123 } 1124 bool operator!=(const defusechain_instr_iterator &x) const { 1125 return !operator==(x); 1126 } 1127 1128 /// atEnd - return true if this iterator is equal to reg_end() on the value. 1129 bool atEnd() const { return Op == nullptr; } 1130 1131 // Iterator traversal: forward iteration only 1132 defusechain_instr_iterator &operator++() { // Preincrement 1133 assert(Op && "Cannot increment end iterator!"); 1134 if (ByOperand) 1135 advance(); 1136 else if (ByInstr) { 1137 MachineInstr *P = Op->getParent(); 1138 do { 1139 advance(); 1140 } while (Op && Op->getParent() == P); 1141 } else if (ByBundle) { 1142 MachineBasicBlock::instr_iterator P = 1143 getBundleStart(Op->getParent()->getIterator()); 1144 do { 1145 advance(); 1146 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P); 1147 } 1148 1149 return *this; 1150 } 1151 defusechain_instr_iterator operator++(int) { // Postincrement 1152 defusechain_instr_iterator tmp = *this; ++*this; return tmp; 1153 } 1154 1155 // Retrieve a reference to the current operand. 1156 MachineInstr &operator*() const { 1157 assert(Op && "Cannot dereference end iterator!"); 1158 if (ByBundle) 1159 return *getBundleStart(Op->getParent()->getIterator()); 1160 return *Op->getParent(); 1161 } 1162 1163 MachineInstr *operator->() const { return &operator*(); } 1164 }; 1165 }; 1166 1167 /// Iterate over the pressure sets affected by the given physical or virtual 1168 /// register. If Reg is physical, it must be a register unit (from 1169 /// MCRegUnitIterator). 1170 class PSetIterator { 1171 const int *PSet = nullptr; 1172 unsigned Weight = 0; 1173 1174 public: 1175 PSetIterator() = default; 1176 1177 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { 1178 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); 1179 if (Register::isVirtualRegister(RegUnit)) { 1180 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); 1181 PSet = TRI->getRegClassPressureSets(RC); 1182 Weight = TRI->getRegClassWeight(RC).RegWeight; 1183 } 1184 else { 1185 PSet = TRI->getRegUnitPressureSets(RegUnit); 1186 Weight = TRI->getRegUnitWeight(RegUnit); 1187 } 1188 if (*PSet == -1) 1189 PSet = nullptr; 1190 } 1191 1192 bool isValid() const { return PSet; } 1193 1194 unsigned getWeight() const { return Weight; } 1195 1196 unsigned operator*() const { return *PSet; } 1197 1198 void operator++() { 1199 assert(isValid() && "Invalid PSetIterator."); 1200 ++PSet; 1201 if (*PSet == -1) 1202 PSet = nullptr; 1203 } 1204 }; 1205 1206 inline PSetIterator MachineRegisterInfo:: 1207 getPressureSets(unsigned RegUnit) const { 1208 return PSetIterator(RegUnit, this); 1209 } 1210 1211 } // end namespace llvm 1212 1213 #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H 1214