1 //===- llvm/CodeGen/RegisterBankInfo.h --------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file declares the API for the register bank info. 10 /// This API is responsible for handling the register banks. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_REGISTERBANKINFO_H 15 #define LLVM_CODEGEN_REGISTERBANKINFO_H 16 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/Hashing.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/ADT/iterator_range.h" 21 #include "llvm/CodeGen/LowLevelType.h" 22 #include "llvm/CodeGen/Register.h" 23 #include "llvm/CodeGen/RegisterBank.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include <cassert> 26 #include <initializer_list> 27 #include <memory> 28 29 namespace llvm { 30 31 class MachineInstr; 32 class MachineRegisterInfo; 33 class raw_ostream; 34 class TargetInstrInfo; 35 class TargetRegisterClass; 36 class TargetRegisterInfo; 37 38 /// Holds all the information related to register banks. 39 class RegisterBankInfo { 40 public: 41 /// Helper struct that represents how a value is partially mapped 42 /// into a register. 43 /// The StartIdx and Length represent what region of the orginal 44 /// value this partial mapping covers. 45 /// This can be represented as a Mask of contiguous bit starting 46 /// at StartIdx bit and spanning Length bits. 47 /// StartIdx is the number of bits from the less significant bits. 48 struct PartialMapping { 49 /// Number of bits at which this partial mapping starts in the 50 /// original value. The bits are counted from less significant 51 /// bits to most significant bits. 52 unsigned StartIdx; 53 54 /// Length of this mapping in bits. This is how many bits this 55 /// partial mapping covers in the original value: 56 /// from StartIdx to StartIdx + Length -1. 57 unsigned Length; 58 59 /// Register bank where the partial value lives. 60 const RegisterBank *RegBank; 61 62 PartialMapping() = default; 63 64 /// Provide a shortcut for quickly building PartialMapping. 65 PartialMapping(unsigned StartIdx, unsigned Length, 66 const RegisterBank &RegBank) 67 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} 68 69 /// \return the index of in the original value of the most 70 /// significant bit that this partial mapping covers. 71 unsigned getHighBitIdx() const { return StartIdx + Length - 1; } 72 73 /// Print this partial mapping on dbgs() stream. 74 void dump() const; 75 76 /// Print this partial mapping on \p OS; 77 void print(raw_ostream &OS) const; 78 79 /// Check that the Mask is compatible with the RegBank. 80 /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask, 81 /// there is no way this mapping is valid. 82 /// 83 /// \note This method does not check anything when assertions are disabled. 84 /// 85 /// \return True is the check was successful. 86 bool verify(const RegisterBankInfo &RBI) const; 87 }; 88 89 /// Helper struct that represents how a value is mapped through 90 /// different register banks. 91 /// 92 /// \note: So far we do not have any users of the complex mappings 93 /// (mappings with more than one partial mapping), but when we do, 94 /// we would have needed to duplicate partial mappings. 95 /// The alternative could be to use an array of pointers of partial 96 /// mapping (i.e., PartialMapping **BreakDown) and duplicate the 97 /// pointers instead. 98 /// 99 /// E.g., 100 /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We 101 /// can expand the 102 /// <2 x 32-bit> add into 2 x 32-bit add. 103 /// 104 /// Currently the TableGen-like file would look like: 105 /// \code 106 /// PartialMapping[] = { 107 /// /*32-bit add*/ {0, 32, GPR}, // Scalar entry repeated for first 108 /// // vec elt. 109 /// /*2x32-bit add*/ {0, 32, GPR}, {32, 32, GPR}, 110 /// /*<2x32-bit> vadd*/ {0, 64, VPR} 111 /// }; // PartialMapping duplicated. 112 /// 113 /// ValueMapping[] { 114 /// /*plain 32-bit add*/ {&PartialMapping[0], 1}, 115 /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2}, 116 /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1} 117 /// }; 118 /// \endcode 119 /// 120 /// With the array of pointer, we would have: 121 /// \code 122 /// PartialMapping[] = { 123 /// /*32-bit add lower */ { 0, 32, GPR}, 124 /// /*32-bit add upper */ {32, 32, GPR}, 125 /// /*<2x32-bit> vadd */ { 0, 64, VPR} 126 /// }; // No more duplication. 127 /// 128 /// BreakDowns[] = { 129 /// /*AddBreakDown*/ &PartialMapping[0], 130 /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[1], 131 /// /*VAddBreakDown*/ &PartialMapping[2] 132 /// }; // Addresses of PartialMapping duplicated (smaller). 133 /// 134 /// ValueMapping[] { 135 /// /*plain 32-bit add*/ {&BreakDowns[0], 1}, 136 /// /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2}, 137 /// /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1} 138 /// }; 139 /// \endcode 140 /// 141 /// Given that a PartialMapping is actually small, the code size 142 /// impact is actually a degradation. Moreover the compile time will 143 /// be hit by the additional indirection. 144 /// If PartialMapping gets bigger we may reconsider. 145 struct ValueMapping { 146 /// How the value is broken down between the different register banks. 147 const PartialMapping *BreakDown; 148 149 /// Number of partial mapping to break down this value. 150 unsigned NumBreakDowns; 151 152 /// The default constructor creates an invalid (isValid() == false) 153 /// instance. 154 ValueMapping() : ValueMapping(nullptr, 0) {} 155 156 /// Initialize a ValueMapping with the given parameter. 157 /// \p BreakDown needs to have a life time at least as long 158 /// as this instance. 159 ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns) 160 : BreakDown(BreakDown), NumBreakDowns(NumBreakDowns) {} 161 162 /// Iterators through the PartialMappings. 163 const PartialMapping *begin() const { return BreakDown; } 164 const PartialMapping *end() const { return BreakDown + NumBreakDowns; } 165 166 /// \return true if all partial mappings are the same size and register 167 /// bank. 168 bool partsAllUniform() const; 169 170 /// Check if this ValueMapping is valid. 171 bool isValid() const { return BreakDown && NumBreakDowns; } 172 173 /// Verify that this mapping makes sense for a value of 174 /// \p MeaningfulBitWidth. 175 /// \note This method does not check anything when assertions are disabled. 176 /// 177 /// \return True is the check was successful. 178 bool verify(const RegisterBankInfo &RBI, unsigned MeaningfulBitWidth) const; 179 180 /// Print this on dbgs() stream. 181 void dump() const; 182 183 /// Print this on \p OS; 184 void print(raw_ostream &OS) const; 185 }; 186 187 /// Helper class that represents how the value of an instruction may be 188 /// mapped and what is the related cost of such mapping. 189 class InstructionMapping { 190 /// Identifier of the mapping. 191 /// This is used to communicate between the target and the optimizers 192 /// which mapping should be realized. 193 unsigned ID = InvalidMappingID; 194 195 /// Cost of this mapping. 196 unsigned Cost = 0; 197 198 /// Mapping of all the operands. 199 const ValueMapping *OperandsMapping = nullptr; 200 201 /// Number of operands. 202 unsigned NumOperands = 0; 203 204 const ValueMapping &getOperandMapping(unsigned i) { 205 assert(i < getNumOperands() && "Out of bound operand"); 206 return OperandsMapping[i]; 207 } 208 209 public: 210 /// Constructor for the mapping of an instruction. 211 /// \p NumOperands must be equal to number of all the operands of 212 /// the related instruction. 213 /// The rationale is that it is more efficient for the optimizers 214 /// to be able to assume that the mapping of the ith operand is 215 /// at the index i. 216 InstructionMapping(unsigned ID, unsigned Cost, 217 const ValueMapping *OperandsMapping, 218 unsigned NumOperands) 219 : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping), 220 NumOperands(NumOperands) {} 221 222 /// Default constructor. 223 /// Use this constructor to express that the mapping is invalid. 224 InstructionMapping() = default; 225 226 /// Get the cost. 227 unsigned getCost() const { return Cost; } 228 229 /// Get the ID. 230 unsigned getID() const { return ID; } 231 232 /// Get the number of operands. 233 unsigned getNumOperands() const { return NumOperands; } 234 235 /// Get the value mapping of the ith operand. 236 /// \pre The mapping for the ith operand has been set. 237 /// \pre The ith operand is a register. 238 const ValueMapping &getOperandMapping(unsigned i) const { 239 const ValueMapping &ValMapping = 240 const_cast<InstructionMapping *>(this)->getOperandMapping(i); 241 return ValMapping; 242 } 243 244 /// Set the mapping for all the operands. 245 /// In other words, OpdsMapping should hold at least getNumOperands 246 /// ValueMapping. 247 void setOperandsMapping(const ValueMapping *OpdsMapping) { 248 OperandsMapping = OpdsMapping; 249 } 250 251 /// Check whether this object is valid. 252 /// This is a lightweight check for obvious wrong instance. 253 bool isValid() const { 254 return getID() != InvalidMappingID && OperandsMapping; 255 } 256 257 /// Verifiy that this mapping makes sense for \p MI. 258 /// \pre \p MI must be connected to a MachineFunction. 259 /// 260 /// \note This method does not check anything when assertions are disabled. 261 /// 262 /// \return True is the check was successful. 263 bool verify(const MachineInstr &MI) const; 264 265 /// Print this on dbgs() stream. 266 void dump() const; 267 268 /// Print this on \p OS; 269 void print(raw_ostream &OS) const; 270 }; 271 272 /// Convenient type to represent the alternatives for mapping an 273 /// instruction. 274 /// \todo When we move to TableGen this should be an array ref. 275 using InstructionMappings = SmallVector<const InstructionMapping *, 4>; 276 277 /// Helper class used to get/create the virtual registers that will be used 278 /// to replace the MachineOperand when applying a mapping. 279 class OperandsMapper { 280 /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the 281 /// OpIdx-th operand starts. -1 means we do not have such mapping yet. 282 /// Note: We use a SmallVector to avoid heap allocation for most cases. 283 SmallVector<int, 8> OpToNewVRegIdx; 284 285 /// Hold the registers that will be used to map MI with InstrMapping. 286 SmallVector<Register, 8> NewVRegs; 287 288 /// Current MachineRegisterInfo, used to create new virtual registers. 289 MachineRegisterInfo &MRI; 290 291 /// Instruction being remapped. 292 MachineInstr &MI; 293 294 /// New mapping of the instruction. 295 const InstructionMapping &InstrMapping; 296 297 /// Constant value identifying that the index in OpToNewVRegIdx 298 /// for an operand has not been set yet. 299 static const int DontKnowIdx; 300 301 /// Get the range in NewVRegs to store all the partial 302 /// values for the \p OpIdx-th operand. 303 /// 304 /// \return The iterator range for the space created. 305 // 306 /// \pre getMI().getOperand(OpIdx).isReg() 307 iterator_range<SmallVectorImpl<Register>::iterator> 308 getVRegsMem(unsigned OpIdx); 309 310 /// Get the end iterator for a range starting at \p StartIdx and 311 /// spannig \p NumVal in NewVRegs. 312 /// \pre StartIdx + NumVal <= NewVRegs.size() 313 SmallVectorImpl<Register>::const_iterator 314 getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const; 315 SmallVectorImpl<Register>::iterator getNewVRegsEnd(unsigned StartIdx, 316 unsigned NumVal); 317 318 public: 319 /// Create an OperandsMapper that will hold the information to apply \p 320 /// InstrMapping to \p MI. 321 /// \pre InstrMapping.verify(MI) 322 OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, 323 MachineRegisterInfo &MRI); 324 325 /// \name Getters. 326 /// @{ 327 /// The MachineInstr being remapped. 328 MachineInstr &getMI() const { return MI; } 329 330 /// The final mapping of the instruction. 331 const InstructionMapping &getInstrMapping() const { return InstrMapping; } 332 333 /// The MachineRegisterInfo we used to realize the mapping. 334 MachineRegisterInfo &getMRI() const { return MRI; } 335 /// @} 336 337 /// Create as many new virtual registers as needed for the mapping of the \p 338 /// OpIdx-th operand. 339 /// The number of registers is determined by the number of breakdown for the 340 /// related operand in the instruction mapping. 341 /// The type of the new registers is a plain scalar of the right size. 342 /// The proper type is expected to be set when the mapping is applied to 343 /// the instruction(s) that realizes the mapping. 344 /// 345 /// \pre getMI().getOperand(OpIdx).isReg() 346 /// 347 /// \post All the partial mapping of the \p OpIdx-th operand have been 348 /// assigned a new virtual register. 349 void createVRegs(unsigned OpIdx); 350 351 /// Set the virtual register of the \p PartialMapIdx-th partial mapping of 352 /// the OpIdx-th operand to \p NewVReg. 353 /// 354 /// \pre getMI().getOperand(OpIdx).isReg() 355 /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() > 356 /// PartialMapIdx 357 /// \pre NewReg != 0 358 /// 359 /// \post the \p PartialMapIdx-th register of the value mapping of the \p 360 /// OpIdx-th operand has been set. 361 void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg); 362 363 /// Get all the virtual registers required to map the \p OpIdx-th operand of 364 /// the instruction. 365 /// 366 /// This return an empty range when createVRegs or setVRegs has not been 367 /// called. 368 /// The iterator may be invalidated by a call to setVRegs or createVRegs. 369 /// 370 /// When \p ForDebug is true, we will not check that the list of new virtual 371 /// registers does not contain uninitialized values. 372 /// 373 /// \pre getMI().getOperand(OpIdx).isReg() 374 /// \pre ForDebug || All partial mappings have been set a register 375 iterator_range<SmallVectorImpl<Register>::const_iterator> 376 getVRegs(unsigned OpIdx, bool ForDebug = false) const; 377 378 /// Print this operands mapper on dbgs() stream. 379 void dump() const; 380 381 /// Print this operands mapper on \p OS stream. 382 void print(raw_ostream &OS, bool ForDebug = false) const; 383 }; 384 385 protected: 386 /// Hold the set of supported register banks. 387 const RegisterBank **RegBanks; 388 389 /// Total number of register banks. 390 unsigned NumRegBanks; 391 392 /// Hold the sizes of the register banks for all HwModes. 393 const unsigned *Sizes; 394 395 /// Current HwMode for the target. 396 unsigned HwMode; 397 398 /// Keep dynamically allocated PartialMapping in a separate map. 399 /// This shouldn't be needed when everything gets TableGen'ed. 400 mutable DenseMap<unsigned, std::unique_ptr<const PartialMapping>> 401 MapOfPartialMappings; 402 403 /// Keep dynamically allocated ValueMapping in a separate map. 404 /// This shouldn't be needed when everything gets TableGen'ed. 405 mutable DenseMap<unsigned, std::unique_ptr<const ValueMapping>> 406 MapOfValueMappings; 407 408 /// Keep dynamically allocated array of ValueMapping in a separate map. 409 /// This shouldn't be needed when everything gets TableGen'ed. 410 mutable DenseMap<unsigned, std::unique_ptr<ValueMapping[]>> 411 MapOfOperandsMappings; 412 413 /// Keep dynamically allocated InstructionMapping in a separate map. 414 /// This shouldn't be needed when everything gets TableGen'ed. 415 mutable DenseMap<unsigned, std::unique_ptr<const InstructionMapping>> 416 MapOfInstructionMappings; 417 418 /// Getting the minimal register class of a physreg is expensive. 419 /// Cache this information as we get it. 420 mutable DenseMap<unsigned, const TargetRegisterClass *> PhysRegMinimalRCs; 421 422 /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks 423 /// RegisterBank instances. 424 RegisterBankInfo(const RegisterBank **RegBanks, unsigned NumRegBanks, 425 const unsigned *Sizes, unsigned HwMode); 426 427 /// This constructor is meaningless. 428 /// It just provides a default constructor that can be used at link time 429 /// when GlobalISel is not built. 430 /// That way, targets can still inherit from this class without doing 431 /// crazy gymnastic to avoid link time failures. 432 /// \note That works because the constructor is inlined. 433 RegisterBankInfo() { 434 llvm_unreachable("This constructor should not be executed"); 435 } 436 437 /// Get the register bank identified by \p ID. 438 const RegisterBank &getRegBank(unsigned ID) { 439 assert(ID < getNumRegBanks() && "Accessing an unknown register bank"); 440 return *RegBanks[ID]; 441 } 442 443 /// Get the MinimalPhysRegClass for Reg. 444 /// \pre Reg is a physical register. 445 const TargetRegisterClass * 446 getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const; 447 448 /// Try to get the mapping of \p MI. 449 /// See getInstrMapping for more details on what a mapping represents. 450 /// 451 /// Unlike getInstrMapping the returned InstructionMapping may be invalid 452 /// (isValid() == false). 453 /// This means that the target independent code is not smart enough 454 /// to get the mapping of \p MI and thus, the target has to provide the 455 /// information for \p MI. 456 /// 457 /// This implementation is able to get the mapping of: 458 /// - Target specific instructions by looking at the encoding constraints. 459 /// - Any instruction if all the register operands have already been assigned 460 /// a register, a register class, or a register bank. 461 /// - Copies and phis if at least one of the operands has been assigned a 462 /// register, a register class, or a register bank. 463 /// In other words, this method will likely fail to find a mapping for 464 /// any generic opcode that has not been lowered by target specific code. 465 const InstructionMapping &getInstrMappingImpl(const MachineInstr &MI) const; 466 467 /// Get the uniquely generated PartialMapping for the 468 /// given arguments. 469 const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length, 470 const RegisterBank &RegBank) const; 471 472 /// \name Methods to get a uniquely generated ValueMapping. 473 /// @{ 474 475 /// The most common ValueMapping consists of a single PartialMapping. 476 /// Feature a method for that. 477 const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length, 478 const RegisterBank &RegBank) const; 479 480 /// Get the ValueMapping for the given arguments. 481 const ValueMapping &getValueMapping(const PartialMapping *BreakDown, 482 unsigned NumBreakDowns) const; 483 /// @} 484 485 /// \name Methods to get a uniquely generated array of ValueMapping. 486 /// @{ 487 488 /// Get the uniquely generated array of ValueMapping for the 489 /// elements of between \p Begin and \p End. 490 /// 491 /// Elements that are nullptr will be replaced by 492 /// invalid ValueMapping (ValueMapping::isValid == false). 493 /// 494 /// \pre The pointers on ValueMapping between \p Begin and \p End 495 /// must uniquely identify a ValueMapping. Otherwise, there is no 496 /// guarantee that the return instance will be unique, i.e., another 497 /// OperandsMapping could have the same content. 498 template <typename Iterator> 499 const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const; 500 501 /// Get the uniquely generated array of ValueMapping for the 502 /// elements of \p OpdsMapping. 503 /// 504 /// Elements of \p OpdsMapping that are nullptr will be replaced by 505 /// invalid ValueMapping (ValueMapping::isValid == false). 506 const ValueMapping *getOperandsMapping( 507 const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const; 508 509 /// Get the uniquely generated array of ValueMapping for the 510 /// given arguments. 511 /// 512 /// Arguments that are nullptr will be replaced by invalid 513 /// ValueMapping (ValueMapping::isValid == false). 514 const ValueMapping *getOperandsMapping( 515 std::initializer_list<const ValueMapping *> OpdsMapping) const; 516 /// @} 517 518 /// \name Methods to get a uniquely generated InstructionMapping. 519 /// @{ 520 521 private: 522 /// Method to get a uniquely generated InstructionMapping. 523 const InstructionMapping & 524 getInstructionMappingImpl(bool IsInvalid, unsigned ID = InvalidMappingID, 525 unsigned Cost = 0, 526 const ValueMapping *OperandsMapping = nullptr, 527 unsigned NumOperands = 0) const; 528 529 public: 530 /// Method to get a uniquely generated InstructionMapping. 531 const InstructionMapping & 532 getInstructionMapping(unsigned ID, unsigned Cost, 533 const ValueMapping *OperandsMapping, 534 unsigned NumOperands) const { 535 return getInstructionMappingImpl(/*IsInvalid*/ false, ID, Cost, 536 OperandsMapping, NumOperands); 537 } 538 539 /// Method to get a uniquely generated invalid InstructionMapping. 540 const InstructionMapping &getInvalidInstructionMapping() const { 541 return getInstructionMappingImpl(/*IsInvalid*/ true); 542 } 543 /// @} 544 545 /// Get the register bank for the \p OpIdx-th operand of \p MI form 546 /// the encoding constraints, if any. 547 /// 548 /// \return A register bank that covers the register class of the 549 /// related encoding constraints or nullptr if \p MI did not provide 550 /// enough information to deduce it. 551 const RegisterBank * 552 getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, 553 const TargetInstrInfo &TII, 554 const MachineRegisterInfo &MRI) const; 555 556 /// Helper method to apply something that is like the default mapping. 557 /// Basically, that means that \p OpdMapper.getMI() is left untouched 558 /// aside from the reassignment of the register operand that have been 559 /// remapped. 560 /// 561 /// The type of all the new registers that have been created by the 562 /// mapper are properly remapped to the type of the original registers 563 /// they replace. In other words, the semantic of the instruction does 564 /// not change, only the register banks. 565 /// 566 /// If the mapping of one of the operand spans several registers, this 567 /// method will abort as this is not like a default mapping anymore. 568 /// 569 /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands()) 570 /// the range OpdMapper.getVRegs(OpIdx) is empty or of size 1. 571 static void applyDefaultMapping(const OperandsMapper &OpdMapper); 572 573 /// See ::applyMapping. 574 virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const { 575 llvm_unreachable("The target has to implement that part"); 576 } 577 578 public: 579 virtual ~RegisterBankInfo() = default; 580 581 /// Get the register bank identified by \p ID. 582 const RegisterBank &getRegBank(unsigned ID) const { 583 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID); 584 } 585 586 /// Get the maximum size in bits that fits in the given register bank. 587 unsigned getMaximumSize(unsigned RegBankID) const { 588 return Sizes[RegBankID + HwMode * NumRegBanks]; 589 } 590 591 /// Get the register bank of \p Reg. 592 /// If Reg has not been assigned a register, a register class, 593 /// or a register bank, then this returns nullptr. 594 /// 595 /// \pre Reg != 0 (NoRegister) 596 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI, 597 const TargetRegisterInfo &TRI) const; 598 599 /// Get the total number of register banks. 600 unsigned getNumRegBanks() const { return NumRegBanks; } 601 602 /// Returns true if the register bank is considered divergent. 603 virtual bool isDivergentRegBank(const RegisterBank *RB) const { 604 return false; 605 } 606 607 /// Get a register bank that covers \p RC. 608 /// 609 /// \pre \p RC is a user-defined register class (as opposed as one 610 /// generated by TableGen). 611 /// 612 /// \note The mapping RC -> RegBank could be built while adding the 613 /// coverage for the register banks. However, we do not do it, because, 614 /// at least for now, we only need this information for register classes 615 /// that are used in the description of instruction. In other words, 616 /// there are just a handful of them and we do not want to waste space. 617 /// 618 /// \todo This should be TableGen'ed. 619 virtual const RegisterBank & 620 getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const { 621 llvm_unreachable("The target must override this method"); 622 } 623 624 /// Get the cost of a copy from \p B to \p A, or put differently, 625 /// get the cost of A = COPY B. Since register banks may cover 626 /// different size, \p Size specifies what will be the size in bits 627 /// that will be copied around. 628 /// 629 /// \note Since this is a copy, both registers have the same size. 630 virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 631 unsigned Size) const { 632 // Optimistically assume that copies are coalesced. I.e., when 633 // they are on the same bank, they are free. 634 // Otherwise assume a non-zero cost of 1. The targets are supposed 635 // to override that properly anyway if they care. 636 return &A != &B; 637 } 638 639 /// \returns true if emitting a copy from \p Src to \p Dst is impossible. 640 bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, 641 unsigned Size) const { 642 return copyCost(Dst, Src, Size) == std::numeric_limits<unsigned>::max(); 643 } 644 645 /// Get the cost of using \p ValMapping to decompose a register. This is 646 /// similar to ::copyCost, except for cases where multiple copy-like 647 /// operations need to be inserted. If the register is used as a source 648 /// operand and already has a bank assigned, \p CurBank is non-null. 649 virtual unsigned 650 getBreakDownCost(const ValueMapping &ValMapping, 651 const RegisterBank *CurBank = nullptr) const { 652 return std::numeric_limits<unsigned>::max(); 653 } 654 655 /// Constrain the (possibly generic) virtual register \p Reg to \p RC. 656 /// 657 /// \pre \p Reg is a virtual register that either has a bank or a class. 658 /// \returns The constrained register class, or nullptr if there is none. 659 /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass 660 /// \note Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel 661 /// purpose, including non-select passes of GlobalISel 662 static const TargetRegisterClass * 663 constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, 664 MachineRegisterInfo &MRI); 665 666 /// Identifier used when the related instruction mapping instance 667 /// is generated by target independent code. 668 /// Make sure not to use that identifier to avoid possible collision. 669 static const unsigned DefaultMappingID; 670 671 /// Identifier used when the related instruction mapping instance 672 /// is generated by the default constructor. 673 /// Make sure not to use that identifier. 674 static const unsigned InvalidMappingID; 675 676 /// Get the mapping of the different operands of \p MI 677 /// on the register bank. 678 /// This mapping should be the direct translation of \p MI. 679 /// In other words, when \p MI is mapped with the returned mapping, 680 /// only the register banks of the operands of \p MI need to be updated. 681 /// In particular, neither the opcode nor the type of \p MI needs to be 682 /// updated for this direct mapping. 683 /// 684 /// The target independent implementation gives a mapping based on 685 /// the register classes for the target specific opcode. 686 /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. 687 /// Make sure you do not use that ID for the alternative mapping 688 /// for MI. See getInstrAlternativeMappings for the alternative 689 /// mappings. 690 /// 691 /// For instance, if \p MI is a vector add, the mapping should 692 /// not be a scalarization of the add. 693 /// 694 /// \post returnedVal.verify(MI). 695 /// 696 /// \note If returnedVal does not verify MI, this would probably mean 697 /// that the target does not support that instruction. 698 virtual const InstructionMapping & 699 getInstrMapping(const MachineInstr &MI) const; 700 701 /// Get the alternative mappings for \p MI. 702 /// Alternative in the sense different from getInstrMapping. 703 virtual InstructionMappings 704 getInstrAlternativeMappings(const MachineInstr &MI) const; 705 706 /// Get the possible mapping for \p MI. 707 /// A mapping defines where the different operands may live and at what cost. 708 /// For instance, let us consider: 709 /// v0(16) = G_ADD <2 x i8> v1, v2 710 /// The possible mapping could be: 711 /// 712 /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)}, 713 /// /*v2*/{(0xFFFF, VPR)}} 714 /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)}, 715 /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)}, 716 /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}} 717 /// 718 /// \note The first alternative of the returned mapping should be the 719 /// direct translation of \p MI current form. 720 /// 721 /// \post !returnedVal.empty(). 722 InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const; 723 724 /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI(). 725 /// After this call \p OpdMapper.getMI() may not be valid anymore. 726 /// \p OpdMapper.getInstrMapping().getID() carries the information of 727 /// what has been chosen to map \p OpdMapper.getMI(). This ID is set 728 /// by the various getInstrXXXMapping method. 729 /// 730 /// Therefore, getting the mapping and applying it should be kept in 731 /// sync. 732 void applyMapping(const OperandsMapper &OpdMapper) const { 733 // The only mapping we know how to handle is the default mapping. 734 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID) 735 return applyDefaultMapping(OpdMapper); 736 // For other mapping, the target needs to do the right thing. 737 // If that means calling applyDefaultMapping, fine, but this 738 // must be explicitly stated. 739 applyMappingImpl(OpdMapper); 740 } 741 742 /// Get the size in bits of \p Reg. 743 /// Utility method to get the size of any registers. Unlike 744 /// MachineRegisterInfo::getSize, the register does not need to be a 745 /// virtual register. 746 /// 747 /// \pre \p Reg != 0 (NoRegister). 748 unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, 749 const TargetRegisterInfo &TRI) const; 750 751 /// Check that information hold by this instance make sense for the 752 /// given \p TRI. 753 /// 754 /// \note This method does not check anything when assertions are disabled. 755 /// 756 /// \return True is the check was successful. 757 bool verify(const TargetRegisterInfo &TRI) const; 758 }; 759 760 inline raw_ostream & 761 operator<<(raw_ostream &OS, 762 const RegisterBankInfo::PartialMapping &PartMapping) { 763 PartMapping.print(OS); 764 return OS; 765 } 766 767 inline raw_ostream & 768 operator<<(raw_ostream &OS, const RegisterBankInfo::ValueMapping &ValMapping) { 769 ValMapping.print(OS); 770 return OS; 771 } 772 773 inline raw_ostream & 774 operator<<(raw_ostream &OS, 775 const RegisterBankInfo::InstructionMapping &InstrMapping) { 776 InstrMapping.print(OS); 777 return OS; 778 } 779 780 inline raw_ostream & 781 operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) { 782 OpdMapper.print(OS, /*ForDebug*/ false); 783 return OS; 784 } 785 786 /// Hashing function for PartialMapping. 787 /// It is required for the hashing of ValueMapping. 788 hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping); 789 790 } // end namespace llvm 791 792 #endif // LLVM_CODEGEN_REGISTERBANKINFO_H 793