1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file describes the target machine instruction set to the code generator. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CODEGEN_TARGETINSTRINFO_H 14 #define LLVM_CODEGEN_TARGETINSTRINFO_H 15 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/DenseMapInfo.h" 19 #include "llvm/ADT/None.h" 20 #include "llvm/CodeGen/MIRFormatter.h" 21 #include "llvm/CodeGen/MachineBasicBlock.h" 22 #include "llvm/CodeGen/MachineCombinerPattern.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/MachineInstr.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineOperand.h" 27 #include "llvm/CodeGen/MachineOutliner.h" 28 #include "llvm/CodeGen/RegisterClassInfo.h" 29 #include "llvm/CodeGen/VirtRegMap.h" 30 #include "llvm/MC/MCInstrInfo.h" 31 #include "llvm/Support/BranchProbability.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include <cassert> 34 #include <cstddef> 35 #include <cstdint> 36 #include <utility> 37 #include <vector> 38 39 namespace llvm { 40 41 class DFAPacketizer; 42 class InstrItineraryData; 43 class LiveIntervals; 44 class LiveVariables; 45 class MachineLoop; 46 class MachineMemOperand; 47 class MachineRegisterInfo; 48 class MCAsmInfo; 49 class MCInst; 50 struct MCSchedModel; 51 class Module; 52 class ScheduleDAG; 53 class ScheduleDAGMI; 54 class ScheduleHazardRecognizer; 55 class SDNode; 56 class SelectionDAG; 57 class RegScavenger; 58 class TargetRegisterClass; 59 class TargetRegisterInfo; 60 class TargetSchedModel; 61 class TargetSubtargetInfo; 62 63 template <class T> class SmallVectorImpl; 64 65 using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>; 66 67 struct DestSourcePair { 68 const MachineOperand *Destination; 69 const MachineOperand *Source; 70 71 DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src) 72 : Destination(&Dest), Source(&Src) {} 73 }; 74 75 /// Used to describe a register and immediate addition. 76 struct RegImmPair { 77 Register Reg; 78 int64_t Imm; 79 80 RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {} 81 }; 82 83 /// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare. 84 /// It holds the register values, the scale value and the displacement. 85 struct ExtAddrMode { 86 Register BaseReg; 87 Register ScaledReg; 88 int64_t Scale; 89 int64_t Displacement; 90 }; 91 92 //--------------------------------------------------------------------------- 93 /// 94 /// TargetInstrInfo - Interface to description of machine instruction set 95 /// 96 class TargetInstrInfo : public MCInstrInfo { 97 public: 98 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, 99 unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u) 100 : CallFrameSetupOpcode(CFSetupOpcode), 101 CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode), 102 ReturnOpcode(ReturnOpcode) {} 103 TargetInstrInfo(const TargetInstrInfo &) = delete; 104 TargetInstrInfo &operator=(const TargetInstrInfo &) = delete; 105 virtual ~TargetInstrInfo(); 106 107 static bool isGenericOpcode(unsigned Opc) { 108 return Opc <= TargetOpcode::GENERIC_OP_END; 109 } 110 111 /// Given a machine instruction descriptor, returns the register 112 /// class constraint for OpNum, or NULL. 113 virtual 114 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum, 115 const TargetRegisterInfo *TRI, 116 const MachineFunction &MF) const; 117 118 /// Return true if the instruction is trivially rematerializable, meaning it 119 /// has no side effects and requires no operands that aren't always available. 120 /// This means the only allowed uses are constants and unallocatable physical 121 /// registers so that the instructions result is independent of the place 122 /// in the function. 123 bool isTriviallyReMaterializable(const MachineInstr &MI) const { 124 return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF || 125 (MI.getDesc().isRematerializable() && 126 (isReallyTriviallyReMaterializable(MI) || 127 isReallyTriviallyReMaterializableGeneric(MI))); 128 } 129 130 /// Given \p MO is a PhysReg use return if it can be ignored for the purpose 131 /// of instruction rematerialization or sinking. 132 virtual bool isIgnorableUse(const MachineOperand &MO) const { 133 return false; 134 } 135 136 protected: 137 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is 138 /// set, this hook lets the target specify whether the instruction is actually 139 /// trivially rematerializable, taking into consideration its operands. This 140 /// predicate must return false if the instruction has any side effects other 141 /// than producing a value, or if it requres any address registers that are 142 /// not always available. 143 /// Requirements must be check as stated in isTriviallyReMaterializable() . 144 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const { 145 return false; 146 } 147 148 /// This method commutes the operands of the given machine instruction MI. 149 /// The operands to be commuted are specified by their indices OpIdx1 and 150 /// OpIdx2. 151 /// 152 /// If a target has any instructions that are commutable but require 153 /// converting to different instructions or making non-trivial changes 154 /// to commute them, this method can be overloaded to do that. 155 /// The default implementation simply swaps the commutable operands. 156 /// 157 /// If NewMI is false, MI is modified in place and returned; otherwise, a 158 /// new machine instruction is created and returned. 159 /// 160 /// Do not call this method for a non-commutable instruction. 161 /// Even though the instruction is commutable, the method may still 162 /// fail to commute the operands, null pointer is returned in such cases. 163 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 164 unsigned OpIdx1, 165 unsigned OpIdx2) const; 166 167 /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable 168 /// operand indices to (ResultIdx1, ResultIdx2). 169 /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be 170 /// predefined to some indices or be undefined (designated by the special 171 /// value 'CommuteAnyOperandIndex'). 172 /// The predefined result indices cannot be re-defined. 173 /// The function returns true iff after the result pair redefinition 174 /// the fixed result pair is equal to or equivalent to the source pair of 175 /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that 176 /// the pairs (x,y) and (y,x) are equivalent. 177 static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, 178 unsigned CommutableOpIdx1, 179 unsigned CommutableOpIdx2); 180 181 private: 182 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is 183 /// set and the target hook isReallyTriviallyReMaterializable returns false, 184 /// this function does target-independent tests to determine if the 185 /// instruction is really trivially rematerializable. 186 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI) const; 187 188 public: 189 /// These methods return the opcode of the frame setup/destroy instructions 190 /// if they exist (-1 otherwise). Some targets use pseudo instructions in 191 /// order to abstract away the difference between operating with a frame 192 /// pointer and operating without, through the use of these two instructions. 193 /// 194 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 195 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 196 197 /// Returns true if the argument is a frame pseudo instruction. 198 bool isFrameInstr(const MachineInstr &I) const { 199 return I.getOpcode() == getCallFrameSetupOpcode() || 200 I.getOpcode() == getCallFrameDestroyOpcode(); 201 } 202 203 /// Returns true if the argument is a frame setup pseudo instruction. 204 bool isFrameSetup(const MachineInstr &I) const { 205 return I.getOpcode() == getCallFrameSetupOpcode(); 206 } 207 208 /// Returns size of the frame associated with the given frame instruction. 209 /// For frame setup instruction this is frame that is set up space set up 210 /// after the instruction. For frame destroy instruction this is the frame 211 /// freed by the caller. 212 /// Note, in some cases a call frame (or a part of it) may be prepared prior 213 /// to the frame setup instruction. It occurs in the calls that involve 214 /// inalloca arguments. This function reports only the size of the frame part 215 /// that is set up between the frame setup and destroy pseudo instructions. 216 int64_t getFrameSize(const MachineInstr &I) const { 217 assert(isFrameInstr(I) && "Not a frame instruction"); 218 assert(I.getOperand(0).getImm() >= 0); 219 return I.getOperand(0).getImm(); 220 } 221 222 /// Returns the total frame size, which is made up of the space set up inside 223 /// the pair of frame start-stop instructions and the space that is set up 224 /// prior to the pair. 225 int64_t getFrameTotalSize(const MachineInstr &I) const { 226 if (isFrameSetup(I)) { 227 assert(I.getOperand(1).getImm() >= 0 && 228 "Frame size must not be negative"); 229 return getFrameSize(I) + I.getOperand(1).getImm(); 230 } 231 return getFrameSize(I); 232 } 233 234 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; } 235 unsigned getReturnOpcode() const { return ReturnOpcode; } 236 237 /// Returns the actual stack pointer adjustment made by an instruction 238 /// as part of a call sequence. By default, only call frame setup/destroy 239 /// instructions adjust the stack, but targets may want to override this 240 /// to enable more fine-grained adjustment, or adjust by a different value. 241 virtual int getSPAdjust(const MachineInstr &MI) const; 242 243 /// Return true if the instruction is a "coalescable" extension instruction. 244 /// That is, it's like a copy where it's legal for the source to overlap the 245 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's 246 /// expected the pre-extension value is available as a subreg of the result 247 /// register. This also returns the sub-register index in SubIdx. 248 virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, 249 Register &DstReg, unsigned &SubIdx) const { 250 return false; 251 } 252 253 /// If the specified machine instruction is a direct 254 /// load from a stack slot, return the virtual or physical register number of 255 /// the destination along with the FrameIndex of the loaded stack slot. If 256 /// not, return 0. This predicate must return 0 if the instruction has 257 /// any side effects other than loading from the stack slot. 258 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, 259 int &FrameIndex) const { 260 return 0; 261 } 262 263 /// Optional extension of isLoadFromStackSlot that returns the number of 264 /// bytes loaded from the stack. This must be implemented if a backend 265 /// supports partial stack slot spills/loads to further disambiguate 266 /// what the load does. 267 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, 268 int &FrameIndex, 269 unsigned &MemBytes) const { 270 MemBytes = 0; 271 return isLoadFromStackSlot(MI, FrameIndex); 272 } 273 274 /// Check for post-frame ptr elimination stack locations as well. 275 /// This uses a heuristic so it isn't reliable for correctness. 276 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 277 int &FrameIndex) const { 278 return 0; 279 } 280 281 /// If the specified machine instruction has a load from a stack slot, 282 /// return true along with the FrameIndices of the loaded stack slot and the 283 /// machine mem operands containing the reference. 284 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for 285 /// any instructions that loads from the stack. This is just a hint, as some 286 /// cases may be missed. 287 virtual bool hasLoadFromStackSlot( 288 const MachineInstr &MI, 289 SmallVectorImpl<const MachineMemOperand *> &Accesses) const; 290 291 /// If the specified machine instruction is a direct 292 /// store to a stack slot, return the virtual or physical register number of 293 /// the source reg along with the FrameIndex of the loaded stack slot. If 294 /// not, return 0. This predicate must return 0 if the instruction has 295 /// any side effects other than storing to the stack slot. 296 virtual unsigned isStoreToStackSlot(const MachineInstr &MI, 297 int &FrameIndex) const { 298 return 0; 299 } 300 301 /// Optional extension of isStoreToStackSlot that returns the number of 302 /// bytes stored to the stack. This must be implemented if a backend 303 /// supports partial stack slot spills/loads to further disambiguate 304 /// what the store does. 305 virtual unsigned isStoreToStackSlot(const MachineInstr &MI, 306 int &FrameIndex, 307 unsigned &MemBytes) const { 308 MemBytes = 0; 309 return isStoreToStackSlot(MI, FrameIndex); 310 } 311 312 /// Check for post-frame ptr elimination stack locations as well. 313 /// This uses a heuristic, so it isn't reliable for correctness. 314 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 315 int &FrameIndex) const { 316 return 0; 317 } 318 319 /// If the specified machine instruction has a store to a stack slot, 320 /// return true along with the FrameIndices of the loaded stack slot and the 321 /// machine mem operands containing the reference. 322 /// If not, return false. Unlike isStoreToStackSlot, 323 /// this returns true for any instructions that stores to the 324 /// stack. This is just a hint, as some cases may be missed. 325 virtual bool hasStoreToStackSlot( 326 const MachineInstr &MI, 327 SmallVectorImpl<const MachineMemOperand *> &Accesses) const; 328 329 /// Return true if the specified machine instruction 330 /// is a copy of one stack slot to another and has no other effect. 331 /// Provide the identity of the two frame indices. 332 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, 333 int &SrcFrameIndex) const { 334 return false; 335 } 336 337 /// Compute the size in bytes and offset within a stack slot of a spilled 338 /// register or subregister. 339 /// 340 /// \param [out] Size in bytes of the spilled value. 341 /// \param [out] Offset in bytes within the stack slot. 342 /// \returns true if both Size and Offset are successfully computed. 343 /// 344 /// Not all subregisters have computable spill slots. For example, 345 /// subregisters registers may not be byte-sized, and a pair of discontiguous 346 /// subregisters has no single offset. 347 /// 348 /// Targets with nontrivial bigendian implementations may need to override 349 /// this, particularly to support spilled vector registers. 350 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, 351 unsigned &Size, unsigned &Offset, 352 const MachineFunction &MF) const; 353 354 /// Return true if the given instruction is terminator that is unspillable, 355 /// according to isUnspillableTerminatorImpl. 356 bool isUnspillableTerminator(const MachineInstr *MI) const { 357 return MI->isTerminator() && isUnspillableTerminatorImpl(MI); 358 } 359 360 /// Returns the size in bytes of the specified MachineInstr, or ~0U 361 /// when this function is not implemented by a target. 362 virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const { 363 return ~0U; 364 } 365 366 /// Return true if the instruction is as cheap as a move instruction. 367 /// 368 /// Targets for different archs need to override this, and different 369 /// micro-architectures can also be finely tuned inside. 370 virtual bool isAsCheapAsAMove(const MachineInstr &MI) const { 371 return MI.isAsCheapAsAMove(); 372 } 373 374 /// Return true if the instruction should be sunk by MachineSink. 375 /// 376 /// MachineSink determines on its own whether the instruction is safe to sink; 377 /// this gives the target a hook to override the default behavior with regards 378 /// to which instructions should be sunk. 379 virtual bool shouldSink(const MachineInstr &MI) const { return true; } 380 381 /// Return false if the instruction should not be hoisted by MachineLICM. 382 /// 383 /// MachineLICM determines on its own whether the instruction is safe to 384 /// hoist; this gives the target a hook to extend this assessment and prevent 385 /// an instruction being hoisted from a given loop for target specific 386 /// reasons. 387 virtual bool shouldHoist(const MachineInstr &MI, 388 const MachineLoop *FromLoop) const { 389 return true; 390 } 391 392 /// Re-issue the specified 'original' instruction at the 393 /// specific location targeting a new destination register. 394 /// The register in Orig->getOperand(0).getReg() will be substituted by 395 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 396 /// SubIdx. 397 virtual void reMaterialize(MachineBasicBlock &MBB, 398 MachineBasicBlock::iterator MI, Register DestReg, 399 unsigned SubIdx, const MachineInstr &Orig, 400 const TargetRegisterInfo &TRI) const; 401 402 /// Clones instruction or the whole instruction bundle \p Orig and 403 /// insert into \p MBB before \p InsertBefore. The target may update operands 404 /// that are required to be unique. 405 /// 406 /// \p Orig must not return true for MachineInstr::isNotDuplicable(). 407 virtual MachineInstr &duplicate(MachineBasicBlock &MBB, 408 MachineBasicBlock::iterator InsertBefore, 409 const MachineInstr &Orig) const; 410 411 /// This method must be implemented by targets that 412 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 413 /// may be able to convert a two-address instruction into one or more true 414 /// three-address instructions on demand. This allows the X86 target (for 415 /// example) to convert ADD and SHL instructions into LEA instructions if they 416 /// would require register copies due to two-addressness. 417 /// 418 /// This method returns a null pointer if the transformation cannot be 419 /// performed, otherwise it returns the last new instruction. 420 /// 421 /// If \p LIS is not nullptr, the LiveIntervals info should be updated for 422 /// replacing \p MI with new instructions, even though this function does not 423 /// remove MI. 424 virtual MachineInstr *convertToThreeAddress(MachineInstr &MI, 425 LiveVariables *LV, 426 LiveIntervals *LIS) const { 427 return nullptr; 428 } 429 430 // This constant can be used as an input value of operand index passed to 431 // the method findCommutedOpIndices() to tell the method that the 432 // corresponding operand index is not pre-defined and that the method 433 // can pick any commutable operand. 434 static const unsigned CommuteAnyOperandIndex = ~0U; 435 436 /// This method commutes the operands of the given machine instruction MI. 437 /// 438 /// The operands to be commuted are specified by their indices OpIdx1 and 439 /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value 440 /// 'CommuteAnyOperandIndex', which means that the method is free to choose 441 /// any arbitrarily chosen commutable operand. If both arguments are set to 442 /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable 443 /// operands; then commutes them if such operands could be found. 444 /// 445 /// If NewMI is false, MI is modified in place and returned; otherwise, a 446 /// new machine instruction is created and returned. 447 /// 448 /// Do not call this method for a non-commutable instruction or 449 /// for non-commuable operands. 450 /// Even though the instruction is commutable, the method may still 451 /// fail to commute the operands, null pointer is returned in such cases. 452 MachineInstr * 453 commuteInstruction(MachineInstr &MI, bool NewMI = false, 454 unsigned OpIdx1 = CommuteAnyOperandIndex, 455 unsigned OpIdx2 = CommuteAnyOperandIndex) const; 456 457 /// Returns true iff the routine could find two commutable operands in the 458 /// given machine instruction. 459 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. 460 /// If any of the INPUT values is set to the special value 461 /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable 462 /// operand, then returns its index in the corresponding argument. 463 /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method 464 /// looks for 2 commutable operands. 465 /// If INPUT values refer to some operands of MI, then the method simply 466 /// returns true if the corresponding operands are commutable and returns 467 /// false otherwise. 468 /// 469 /// For example, calling this method this way: 470 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 471 /// findCommutedOpIndices(MI, Op1, Op2); 472 /// can be interpreted as a query asking to find an operand that would be 473 /// commutable with the operand#1. 474 virtual bool findCommutedOpIndices(const MachineInstr &MI, 475 unsigned &SrcOpIdx1, 476 unsigned &SrcOpIdx2) const; 477 478 /// Returns true if the target has a preference on the operands order of 479 /// the given machine instruction. And specify if \p Commute is required to 480 /// get the desired operands order. 481 virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const { 482 return false; 483 } 484 485 /// A pair composed of a register and a sub-register index. 486 /// Used to give some type checking when modeling Reg:SubReg. 487 struct RegSubRegPair { 488 Register Reg; 489 unsigned SubReg; 490 491 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0) 492 : Reg(Reg), SubReg(SubReg) {} 493 494 bool operator==(const RegSubRegPair& P) const { 495 return Reg == P.Reg && SubReg == P.SubReg; 496 } 497 bool operator!=(const RegSubRegPair& P) const { 498 return !(*this == P); 499 } 500 }; 501 502 /// A pair composed of a pair of a register and a sub-register index, 503 /// and another sub-register index. 504 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2. 505 struct RegSubRegPairAndIdx : RegSubRegPair { 506 unsigned SubIdx; 507 508 RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0, 509 unsigned SubIdx = 0) 510 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} 511 }; 512 513 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI 514 /// and \p DefIdx. 515 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of 516 /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef 517 /// flag are not added to this list. 518 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce 519 /// two elements: 520 /// - %1:sub1, sub0 521 /// - %2<:0>, sub1 522 /// 523 /// \returns true if it is possible to build such an input sequence 524 /// with the pair \p MI, \p DefIdx. False otherwise. 525 /// 526 /// \pre MI.isRegSequence() or MI.isRegSequenceLike(). 527 /// 528 /// \note The generic implementation does not provide any support for 529 /// MI.isRegSequenceLike(). In other words, one has to override 530 /// getRegSequenceLikeInputs for target specific instructions. 531 bool 532 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, 533 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const; 534 535 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI 536 /// and \p DefIdx. 537 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. 538 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: 539 /// - %1:sub1, sub0 540 /// 541 /// \returns true if it is possible to build such an input sequence 542 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. 543 /// False otherwise. 544 /// 545 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike(). 546 /// 547 /// \note The generic implementation does not provide any support for 548 /// MI.isExtractSubregLike(). In other words, one has to override 549 /// getExtractSubregLikeInputs for target specific instructions. 550 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, 551 RegSubRegPairAndIdx &InputReg) const; 552 553 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI 554 /// and \p DefIdx. 555 /// \p [out] BaseReg and \p [out] InsertedReg contain 556 /// the equivalent inputs of INSERT_SUBREG. 557 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: 558 /// - BaseReg: %0:sub0 559 /// - InsertedReg: %1:sub1, sub3 560 /// 561 /// \returns true if it is possible to build such an input sequence 562 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. 563 /// False otherwise. 564 /// 565 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike(). 566 /// 567 /// \note The generic implementation does not provide any support for 568 /// MI.isInsertSubregLike(). In other words, one has to override 569 /// getInsertSubregLikeInputs for target specific instructions. 570 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, 571 RegSubRegPair &BaseReg, 572 RegSubRegPairAndIdx &InsertedReg) const; 573 574 /// Return true if two machine instructions would produce identical values. 575 /// By default, this is only true when the two instructions 576 /// are deemed identical except for defs. If this function is called when the 577 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 578 /// aggressive checks. 579 virtual bool produceSameValue(const MachineInstr &MI0, 580 const MachineInstr &MI1, 581 const MachineRegisterInfo *MRI = nullptr) const; 582 583 /// \returns true if a branch from an instruction with opcode \p BranchOpc 584 /// bytes is capable of jumping to a position \p BrOffset bytes away. 585 virtual bool isBranchOffsetInRange(unsigned BranchOpc, 586 int64_t BrOffset) const { 587 llvm_unreachable("target did not implement"); 588 } 589 590 /// \returns The block that branch instruction \p MI jumps to. 591 virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const { 592 llvm_unreachable("target did not implement"); 593 } 594 595 /// Insert an unconditional indirect branch at the end of \p MBB to \p 596 /// NewDestBB. Optionally, insert the clobbered register restoring in \p 597 /// RestoreBB. \p BrOffset indicates the offset of \p NewDestBB relative to 598 /// the offset of the position to insert the new branch. 599 virtual void insertIndirectBranch(MachineBasicBlock &MBB, 600 MachineBasicBlock &NewDestBB, 601 MachineBasicBlock &RestoreBB, 602 const DebugLoc &DL, int64_t BrOffset = 0, 603 RegScavenger *RS = nullptr) const { 604 llvm_unreachable("target did not implement"); 605 } 606 607 /// Analyze the branching code at the end of MBB, returning 608 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 609 /// implemented for a target). Upon success, this returns false and returns 610 /// with the following information in various cases: 611 /// 612 /// 1. If this block ends with no branches (it just falls through to its succ) 613 /// just return false, leaving TBB/FBB null. 614 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 615 /// the destination block. 616 /// 3. If this block ends with a conditional branch and it falls through to a 617 /// successor block, it sets TBB to be the branch destination block and a 618 /// list of operands that evaluate the condition. These operands can be 619 /// passed to other TargetInstrInfo methods to create new branches. 620 /// 4. If this block ends with a conditional branch followed by an 621 /// unconditional branch, it returns the 'true' destination in TBB, the 622 /// 'false' destination in FBB, and a list of operands that evaluate the 623 /// condition. These operands can be passed to other TargetInstrInfo 624 /// methods to create new branches. 625 /// 626 /// Note that removeBranch and insertBranch must be implemented to support 627 /// cases where this method returns success. 628 /// 629 /// If AllowModify is true, then this routine is allowed to modify the basic 630 /// block (e.g. delete instructions after the unconditional branch). 631 /// 632 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid 633 /// before calling this function. 634 virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 635 MachineBasicBlock *&FBB, 636 SmallVectorImpl<MachineOperand> &Cond, 637 bool AllowModify = false) const { 638 return true; 639 } 640 641 /// Represents a predicate at the MachineFunction level. The control flow a 642 /// MachineBranchPredicate represents is: 643 /// 644 /// Reg = LHS `Predicate` RHS == ConditionDef 645 /// if Reg then goto TrueDest else goto FalseDest 646 /// 647 struct MachineBranchPredicate { 648 enum ComparePredicate { 649 PRED_EQ, // True if two values are equal 650 PRED_NE, // True if two values are not equal 651 PRED_INVALID // Sentinel value 652 }; 653 654 ComparePredicate Predicate = PRED_INVALID; 655 MachineOperand LHS = MachineOperand::CreateImm(0); 656 MachineOperand RHS = MachineOperand::CreateImm(0); 657 MachineBasicBlock *TrueDest = nullptr; 658 MachineBasicBlock *FalseDest = nullptr; 659 MachineInstr *ConditionDef = nullptr; 660 661 /// SingleUseCondition is true if ConditionDef is dead except for the 662 /// branch(es) at the end of the basic block. 663 /// 664 bool SingleUseCondition = false; 665 666 explicit MachineBranchPredicate() = default; 667 }; 668 669 /// Analyze the branching code at the end of MBB and parse it into the 670 /// MachineBranchPredicate structure if possible. Returns false on success 671 /// and true on failure. 672 /// 673 /// If AllowModify is true, then this routine is allowed to modify the basic 674 /// block (e.g. delete instructions after the unconditional branch). 675 /// 676 virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, 677 MachineBranchPredicate &MBP, 678 bool AllowModify = false) const { 679 return true; 680 } 681 682 /// Remove the branching code at the end of the specific MBB. 683 /// This is only invoked in cases where analyzeBranch returns success. It 684 /// returns the number of instructions that were removed. 685 /// If \p BytesRemoved is non-null, report the change in code size from the 686 /// removed instructions. 687 virtual unsigned removeBranch(MachineBasicBlock &MBB, 688 int *BytesRemoved = nullptr) const { 689 llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!"); 690 } 691 692 /// Insert branch code into the end of the specified MachineBasicBlock. The 693 /// operands to this method are the same as those returned by analyzeBranch. 694 /// This is only invoked in cases where analyzeBranch returns success. It 695 /// returns the number of instructions inserted. If \p BytesAdded is non-null, 696 /// report the change in code size from the added instructions. 697 /// 698 /// It is also invoked by tail merging to add unconditional branches in 699 /// cases where analyzeBranch doesn't apply because there was no original 700 /// branch to analyze. At least this much must be implemented, else tail 701 /// merging needs to be disabled. 702 /// 703 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid 704 /// before calling this function. 705 virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 706 MachineBasicBlock *FBB, 707 ArrayRef<MachineOperand> Cond, 708 const DebugLoc &DL, 709 int *BytesAdded = nullptr) const { 710 llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!"); 711 } 712 713 unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, 714 MachineBasicBlock *DestBB, 715 const DebugLoc &DL, 716 int *BytesAdded = nullptr) const { 717 return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL, 718 BytesAdded); 719 } 720 721 /// Object returned by analyzeLoopForPipelining. Allows software pipelining 722 /// implementations to query attributes of the loop being pipelined and to 723 /// apply target-specific updates to the loop once pipelining is complete. 724 class PipelinerLoopInfo { 725 public: 726 virtual ~PipelinerLoopInfo(); 727 /// Return true if the given instruction should not be pipelined and should 728 /// be ignored. An example could be a loop comparison, or induction variable 729 /// update with no users being pipelined. 730 virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0; 731 732 /// Create a condition to determine if the trip count of the loop is greater 733 /// than TC, where TC is always one more than for the previous prologue or 734 /// 0 if this is being called for the outermost prologue. 735 /// 736 /// If the trip count is statically known to be greater than TC, return 737 /// true. If the trip count is statically known to be not greater than TC, 738 /// return false. Otherwise return nullopt and fill out Cond with the test 739 /// condition. 740 /// 741 /// Note: This hook is guaranteed to be called from the innermost to the 742 /// outermost prologue of the loop being software pipelined. 743 virtual Optional<bool> 744 createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, 745 SmallVectorImpl<MachineOperand> &Cond) = 0; 746 747 /// Modify the loop such that the trip count is 748 /// OriginalTC + TripCountAdjust. 749 virtual void adjustTripCount(int TripCountAdjust) = 0; 750 751 /// Called when the loop's preheader has been modified to NewPreheader. 752 virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0; 753 754 /// Called when the loop is being removed. Any instructions in the preheader 755 /// should be removed. 756 /// 757 /// Once this function is called, no other functions on this object are 758 /// valid; the loop has been removed. 759 virtual void disposed() = 0; 760 }; 761 762 /// Analyze loop L, which must be a single-basic-block loop, and if the 763 /// conditions can be understood enough produce a PipelinerLoopInfo object. 764 virtual std::unique_ptr<PipelinerLoopInfo> 765 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const { 766 return nullptr; 767 } 768 769 /// Analyze the loop code, return true if it cannot be understood. Upon 770 /// success, this function returns false and returns information about the 771 /// induction variable and compare instruction used at the end. 772 virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, 773 MachineInstr *&CmpInst) const { 774 return true; 775 } 776 777 /// Generate code to reduce the loop iteration by one and check if the loop 778 /// is finished. Return the value/register of the new loop count. We need 779 /// this function when peeling off one or more iterations of a loop. This 780 /// function assumes the nth iteration is peeled first. 781 virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, 782 MachineBasicBlock &PreHeader, 783 MachineInstr *IndVar, MachineInstr &Cmp, 784 SmallVectorImpl<MachineOperand> &Cond, 785 SmallVectorImpl<MachineInstr *> &PrevInsts, 786 unsigned Iter, unsigned MaxIter) const { 787 llvm_unreachable("Target didn't implement ReduceLoopCount"); 788 } 789 790 /// Delete the instruction OldInst and everything after it, replacing it with 791 /// an unconditional branch to NewDest. This is used by the tail merging pass. 792 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 793 MachineBasicBlock *NewDest) const; 794 795 /// Return true if it's legal to split the given basic 796 /// block at the specified instruction (i.e. instruction would be the start 797 /// of a new basic block). 798 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 799 MachineBasicBlock::iterator MBBI) const { 800 return true; 801 } 802 803 /// Return true if it's profitable to predicate 804 /// instructions with accumulated instruction latency of "NumCycles" 805 /// of the specified basic block, where the probability of the instructions 806 /// being executed is given by Probability, and Confidence is a measure 807 /// of our confidence that it will be properly predicted. 808 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 809 unsigned ExtraPredCycles, 810 BranchProbability Probability) const { 811 return false; 812 } 813 814 /// Second variant of isProfitableToIfCvt. This one 815 /// checks for the case where two basic blocks from true and false path 816 /// of a if-then-else (diamond) are predicated on mutually exclusive 817 /// predicates, where the probability of the true path being taken is given 818 /// by Probability, and Confidence is a measure of our confidence that it 819 /// will be properly predicted. 820 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, 821 unsigned ExtraTCycles, 822 MachineBasicBlock &FMBB, unsigned NumFCycles, 823 unsigned ExtraFCycles, 824 BranchProbability Probability) const { 825 return false; 826 } 827 828 /// Return true if it's profitable for if-converter to duplicate instructions 829 /// of specified accumulated instruction latencies in the specified MBB to 830 /// enable if-conversion. 831 /// The probability of the instructions being executed is given by 832 /// Probability, and Confidence is a measure of our confidence that it 833 /// will be properly predicted. 834 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 835 unsigned NumCycles, 836 BranchProbability Probability) const { 837 return false; 838 } 839 840 /// Return the increase in code size needed to predicate a contiguous run of 841 /// NumInsts instructions. 842 virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, 843 unsigned NumInsts) const { 844 return 0; 845 } 846 847 /// Return an estimate for the code size reduction (in bytes) which will be 848 /// caused by removing the given branch instruction during if-conversion. 849 virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const { 850 return getInstSizeInBytes(MI); 851 } 852 853 /// Return true if it's profitable to unpredicate 854 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually 855 /// exclusive predicates. 856 /// e.g. 857 /// subeq r0, r1, #1 858 /// addne r0, r1, #1 859 /// => 860 /// sub r0, r1, #1 861 /// addne r0, r1, #1 862 /// 863 /// This may be profitable is conditional instructions are always executed. 864 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 865 MachineBasicBlock &FMBB) const { 866 return false; 867 } 868 869 /// Return true if it is possible to insert a select 870 /// instruction that chooses between TrueReg and FalseReg based on the 871 /// condition code in Cond. 872 /// 873 /// When successful, also return the latency in cycles from TrueReg, 874 /// FalseReg, and Cond to the destination register. In most cases, a select 875 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1 876 /// 877 /// Some x86 implementations have 2-cycle cmov instructions. 878 /// 879 /// @param MBB Block where select instruction would be inserted. 880 /// @param Cond Condition returned by analyzeBranch. 881 /// @param DstReg Virtual dest register that the result should write to. 882 /// @param TrueReg Virtual register to select when Cond is true. 883 /// @param FalseReg Virtual register to select when Cond is false. 884 /// @param CondCycles Latency from Cond+Branch to select output. 885 /// @param TrueCycles Latency from TrueReg to select output. 886 /// @param FalseCycles Latency from FalseReg to select output. 887 virtual bool canInsertSelect(const MachineBasicBlock &MBB, 888 ArrayRef<MachineOperand> Cond, Register DstReg, 889 Register TrueReg, Register FalseReg, 890 int &CondCycles, int &TrueCycles, 891 int &FalseCycles) const { 892 return false; 893 } 894 895 /// Insert a select instruction into MBB before I that will copy TrueReg to 896 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false. 897 /// 898 /// This function can only be called after canInsertSelect() returned true. 899 /// The condition in Cond comes from analyzeBranch, and it can be assumed 900 /// that the same flags or registers required by Cond are available at the 901 /// insertion point. 902 /// 903 /// @param MBB Block where select instruction should be inserted. 904 /// @param I Insertion point. 905 /// @param DL Source location for debugging. 906 /// @param DstReg Virtual register to be defined by select instruction. 907 /// @param Cond Condition as computed by analyzeBranch. 908 /// @param TrueReg Virtual register to copy when Cond is true. 909 /// @param FalseReg Virtual register to copy when Cons is false. 910 virtual void insertSelect(MachineBasicBlock &MBB, 911 MachineBasicBlock::iterator I, const DebugLoc &DL, 912 Register DstReg, ArrayRef<MachineOperand> Cond, 913 Register TrueReg, Register FalseReg) const { 914 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); 915 } 916 917 /// Analyze the given select instruction, returning true if 918 /// it cannot be understood. It is assumed that MI->isSelect() is true. 919 /// 920 /// When successful, return the controlling condition and the operands that 921 /// determine the true and false result values. 922 /// 923 /// Result = SELECT Cond, TrueOp, FalseOp 924 /// 925 /// Some targets can optimize select instructions, for example by predicating 926 /// the instruction defining one of the operands. Such targets should set 927 /// Optimizable. 928 /// 929 /// @param MI Select instruction to analyze. 930 /// @param Cond Condition controlling the select. 931 /// @param TrueOp Operand number of the value selected when Cond is true. 932 /// @param FalseOp Operand number of the value selected when Cond is false. 933 /// @param Optimizable Returned as true if MI is optimizable. 934 /// @returns False on success. 935 virtual bool analyzeSelect(const MachineInstr &MI, 936 SmallVectorImpl<MachineOperand> &Cond, 937 unsigned &TrueOp, unsigned &FalseOp, 938 bool &Optimizable) const { 939 assert(MI.getDesc().isSelect() && "MI must be a select instruction"); 940 return true; 941 } 942 943 /// Given a select instruction that was understood by 944 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by 945 /// merging it with one of its operands. Returns NULL on failure. 946 /// 947 /// When successful, returns the new select instruction. The client is 948 /// responsible for deleting MI. 949 /// 950 /// If both sides of the select can be optimized, PreferFalse is used to pick 951 /// a side. 952 /// 953 /// @param MI Optimizable select instruction. 954 /// @param NewMIs Set that record all MIs in the basic block up to \p 955 /// MI. Has to be updated with any newly created MI or deleted ones. 956 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp. 957 /// @returns Optimized instruction or NULL. 958 virtual MachineInstr *optimizeSelect(MachineInstr &MI, 959 SmallPtrSetImpl<MachineInstr *> &NewMIs, 960 bool PreferFalse = false) const { 961 // This function must be implemented if Optimizable is ever set. 962 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!"); 963 } 964 965 /// Emit instructions to copy a pair of physical registers. 966 /// 967 /// This function should support copies within any legal register class as 968 /// well as any cross-class copies created during instruction selection. 969 /// 970 /// The source and destination registers may overlap, which may require a 971 /// careful implementation when multiple copy instructions are required for 972 /// large registers. See for example the ARM target. 973 virtual void copyPhysReg(MachineBasicBlock &MBB, 974 MachineBasicBlock::iterator MI, const DebugLoc &DL, 975 MCRegister DestReg, MCRegister SrcReg, 976 bool KillSrc) const { 977 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!"); 978 } 979 980 /// Allow targets to tell MachineVerifier whether a specific register 981 /// MachineOperand can be used as part of PC-relative addressing. 982 /// PC-relative addressing modes in many CISC architectures contain 983 /// (non-PC) registers as offsets or scaling values, which inherently 984 /// tags the corresponding MachineOperand with OPERAND_PCREL. 985 /// 986 /// @param MO The MachineOperand in question. MO.isReg() should always 987 /// be true. 988 /// @return Whether this operand is allowed to be used PC-relatively. 989 virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const { 990 return false; 991 } 992 993 protected: 994 /// Target-dependent implementation for IsCopyInstr. 995 /// If the specific machine instruction is a instruction that moves/copies 996 /// value from one register to another register return destination and source 997 /// registers as machine operands. 998 virtual Optional<DestSourcePair> 999 isCopyInstrImpl(const MachineInstr &MI) const { 1000 return None; 1001 } 1002 1003 /// Return true if the given terminator MI is not expected to spill. This 1004 /// sets the live interval as not spillable and adjusts phi node lowering to 1005 /// not introduce copies after the terminator. Use with care, these are 1006 /// currently used for hardware loop intrinsics in very controlled situations, 1007 /// created prior to registry allocation in loops that only have single phi 1008 /// users for the terminators value. They may run out of registers if not used 1009 /// carefully. 1010 virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const { 1011 return false; 1012 } 1013 1014 public: 1015 /// If the specific machine instruction is a instruction that moves/copies 1016 /// value from one register to another register return destination and source 1017 /// registers as machine operands. 1018 /// For COPY-instruction the method naturally returns destination and source 1019 /// registers as machine operands, for all other instructions the method calls 1020 /// target-dependent implementation. 1021 Optional<DestSourcePair> isCopyInstr(const MachineInstr &MI) const { 1022 if (MI.isCopy()) { 1023 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; 1024 } 1025 return isCopyInstrImpl(MI); 1026 } 1027 1028 /// If the specific machine instruction is an instruction that adds an 1029 /// immediate value and a physical register, and stores the result in 1030 /// the given physical register \c Reg, return a pair of the source 1031 /// register and the offset which has been added. 1032 virtual Optional<RegImmPair> isAddImmediate(const MachineInstr &MI, 1033 Register Reg) const { 1034 return None; 1035 } 1036 1037 /// Returns true if MI is an instruction that defines Reg to have a constant 1038 /// value and the value is recorded in ImmVal. The ImmVal is a result that 1039 /// should be interpreted as modulo size of Reg. 1040 virtual bool getConstValDefinedInReg(const MachineInstr &MI, 1041 const Register Reg, 1042 int64_t &ImmVal) const { 1043 return false; 1044 } 1045 1046 /// Store the specified register of the given register class to the specified 1047 /// stack frame index. The store instruction is to be added to the given 1048 /// machine basic block before the specified machine instruction. If isKill 1049 /// is true, the register operand is the last use and must be marked kill. 1050 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 1051 MachineBasicBlock::iterator MI, 1052 Register SrcReg, bool isKill, int FrameIndex, 1053 const TargetRegisterClass *RC, 1054 const TargetRegisterInfo *TRI) const { 1055 llvm_unreachable("Target didn't implement " 1056 "TargetInstrInfo::storeRegToStackSlot!"); 1057 } 1058 1059 /// Load the specified register of the given register class from the specified 1060 /// stack frame index. The load instruction is to be added to the given 1061 /// machine basic block before the specified machine instruction. 1062 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 1063 MachineBasicBlock::iterator MI, 1064 Register DestReg, int FrameIndex, 1065 const TargetRegisterClass *RC, 1066 const TargetRegisterInfo *TRI) const { 1067 llvm_unreachable("Target didn't implement " 1068 "TargetInstrInfo::loadRegFromStackSlot!"); 1069 } 1070 1071 /// This function is called for all pseudo instructions 1072 /// that remain after register allocation. Many pseudo instructions are 1073 /// created to help register allocation. This is the place to convert them 1074 /// into real instructions. The target can edit MI in place, or it can insert 1075 /// new instructions and erase MI. The function should return true if 1076 /// anything was changed. 1077 virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; } 1078 1079 /// Check whether the target can fold a load that feeds a subreg operand 1080 /// (or a subreg operand that feeds a store). 1081 /// For example, X86 may want to return true if it can fold 1082 /// movl (%esp), %eax 1083 /// subb, %al, ... 1084 /// Into: 1085 /// subb (%esp), ... 1086 /// 1087 /// Ideally, we'd like the target implementation of foldMemoryOperand() to 1088 /// reject subregs - but since this behavior used to be enforced in the 1089 /// target-independent code, moving this responsibility to the targets 1090 /// has the potential of causing nasty silent breakage in out-of-tree targets. 1091 virtual bool isSubregFoldable() const { return false; } 1092 1093 /// For a patchpoint, stackmap, or statepoint intrinsic, return the range of 1094 /// operands which can't be folded into stack references. Operands outside 1095 /// of the range are most likely foldable but it is not guaranteed. 1096 /// These instructions are unique in that stack references for some operands 1097 /// have the same execution cost (e.g. none) as the unfolded register forms. 1098 /// The ranged return is guaranteed to include all operands which can't be 1099 /// folded at zero cost. 1100 virtual std::pair<unsigned, unsigned> 1101 getPatchpointUnfoldableRange(const MachineInstr &MI) const; 1102 1103 /// Attempt to fold a load or store of the specified stack 1104 /// slot into the specified machine instruction for the specified operand(s). 1105 /// If this is possible, a new instruction is returned with the specified 1106 /// operand folded, otherwise NULL is returned. 1107 /// The new instruction is inserted before MI, and the client is responsible 1108 /// for removing the old instruction. 1109 /// If VRM is passed, the assigned physregs can be inspected by target to 1110 /// decide on using an opcode (note that those assignments can still change). 1111 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops, 1112 int FI, 1113 LiveIntervals *LIS = nullptr, 1114 VirtRegMap *VRM = nullptr) const; 1115 1116 /// Same as the previous version except it allows folding of any load and 1117 /// store from / to any address, not just from a specific stack slot. 1118 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops, 1119 MachineInstr &LoadMI, 1120 LiveIntervals *LIS = nullptr) const; 1121 1122 /// Return true when there is potentially a faster code sequence 1123 /// for an instruction chain ending in \p Root. All potential patterns are 1124 /// returned in the \p Pattern vector. Pattern should be sorted in priority 1125 /// order since the pattern evaluator stops checking as soon as it finds a 1126 /// faster sequence. 1127 /// \param Root - Instruction that could be combined with one of its operands 1128 /// \param Patterns - Vector of possible combination patterns 1129 virtual bool 1130 getMachineCombinerPatterns(MachineInstr &Root, 1131 SmallVectorImpl<MachineCombinerPattern> &Patterns, 1132 bool DoRegPressureReduce) const; 1133 1134 /// Return true if target supports reassociation of instructions in machine 1135 /// combiner pass to reduce register pressure for a given BB. 1136 virtual bool 1137 shouldReduceRegisterPressure(MachineBasicBlock *MBB, 1138 RegisterClassInfo *RegClassInfo) const { 1139 return false; 1140 } 1141 1142 /// Fix up the placeholder we may add in genAlternativeCodeSequence(). 1143 virtual void 1144 finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, 1145 SmallVectorImpl<MachineInstr *> &InsInstrs) const {} 1146 1147 /// Return true when a code sequence can improve throughput. It 1148 /// should be called only for instructions in loops. 1149 /// \param Pattern - combiner pattern 1150 virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const; 1151 1152 /// Return true if the input \P Inst is part of a chain of dependent ops 1153 /// that are suitable for reassociation, otherwise return false. 1154 /// If the instruction's operands must be commuted to have a previous 1155 /// instruction of the same type define the first source operand, \P Commuted 1156 /// will be set to true. 1157 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const; 1158 1159 /// Return true when \P Inst is both associative and commutative. 1160 virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const { 1161 return false; 1162 } 1163 1164 /// Return true when \P Inst has reassociable operands in the same \P MBB. 1165 virtual bool hasReassociableOperands(const MachineInstr &Inst, 1166 const MachineBasicBlock *MBB) const; 1167 1168 /// Return true when \P Inst has reassociable sibling. 1169 bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const; 1170 1171 /// When getMachineCombinerPatterns() finds patterns, this function generates 1172 /// the instructions that could replace the original code sequence. The client 1173 /// has to decide whether the actual replacement is beneficial or not. 1174 /// \param Root - Instruction that could be combined with one of its operands 1175 /// \param Pattern - Combination pattern for Root 1176 /// \param InsInstrs - Vector of new instructions that implement P 1177 /// \param DelInstrs - Old instructions, including Root, that could be 1178 /// replaced by InsInstr 1179 /// \param InstIdxForVirtReg - map of virtual register to instruction in 1180 /// InsInstr that defines it 1181 virtual void genAlternativeCodeSequence( 1182 MachineInstr &Root, MachineCombinerPattern Pattern, 1183 SmallVectorImpl<MachineInstr *> &InsInstrs, 1184 SmallVectorImpl<MachineInstr *> &DelInstrs, 1185 DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const; 1186 1187 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to 1188 /// reduce critical path length. 1189 void reassociateOps(MachineInstr &Root, MachineInstr &Prev, 1190 MachineCombinerPattern Pattern, 1191 SmallVectorImpl<MachineInstr *> &InsInstrs, 1192 SmallVectorImpl<MachineInstr *> &DelInstrs, 1193 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const; 1194 1195 /// The limit on resource length extension we accept in MachineCombiner Pass. 1196 virtual int getExtendResourceLenLimit() const { return 0; } 1197 1198 /// This is an architecture-specific helper function of reassociateOps. 1199 /// Set special operand attributes for new instructions after reassociation. 1200 virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 1201 MachineInstr &NewMI1, 1202 MachineInstr &NewMI2) const {} 1203 1204 /// Return true when a target supports MachineCombiner. 1205 virtual bool useMachineCombiner() const { return false; } 1206 1207 /// Return true if the given SDNode can be copied during scheduling 1208 /// even if it has glue. 1209 virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; } 1210 1211 protected: 1212 /// Target-dependent implementation for foldMemoryOperand. 1213 /// Target-independent code in foldMemoryOperand will 1214 /// take care of adding a MachineMemOperand to the newly created instruction. 1215 /// The instruction and any auxiliary instructions necessary will be inserted 1216 /// at InsertPt. 1217 virtual MachineInstr * 1218 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 1219 ArrayRef<unsigned> Ops, 1220 MachineBasicBlock::iterator InsertPt, int FrameIndex, 1221 LiveIntervals *LIS = nullptr, 1222 VirtRegMap *VRM = nullptr) const { 1223 return nullptr; 1224 } 1225 1226 /// Target-dependent implementation for foldMemoryOperand. 1227 /// Target-independent code in foldMemoryOperand will 1228 /// take care of adding a MachineMemOperand to the newly created instruction. 1229 /// The instruction and any auxiliary instructions necessary will be inserted 1230 /// at InsertPt. 1231 virtual MachineInstr *foldMemoryOperandImpl( 1232 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 1233 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, 1234 LiveIntervals *LIS = nullptr) const { 1235 return nullptr; 1236 } 1237 1238 /// Target-dependent implementation of getRegSequenceInputs. 1239 /// 1240 /// \returns true if it is possible to build the equivalent 1241 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise. 1242 /// 1243 /// \pre MI.isRegSequenceLike(). 1244 /// 1245 /// \see TargetInstrInfo::getRegSequenceInputs. 1246 virtual bool getRegSequenceLikeInputs( 1247 const MachineInstr &MI, unsigned DefIdx, 1248 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const { 1249 return false; 1250 } 1251 1252 /// Target-dependent implementation of getExtractSubregInputs. 1253 /// 1254 /// \returns true if it is possible to build the equivalent 1255 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise. 1256 /// 1257 /// \pre MI.isExtractSubregLike(). 1258 /// 1259 /// \see TargetInstrInfo::getExtractSubregInputs. 1260 virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, 1261 unsigned DefIdx, 1262 RegSubRegPairAndIdx &InputReg) const { 1263 return false; 1264 } 1265 1266 /// Target-dependent implementation of getInsertSubregInputs. 1267 /// 1268 /// \returns true if it is possible to build the equivalent 1269 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise. 1270 /// 1271 /// \pre MI.isInsertSubregLike(). 1272 /// 1273 /// \see TargetInstrInfo::getInsertSubregInputs. 1274 virtual bool 1275 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 1276 RegSubRegPair &BaseReg, 1277 RegSubRegPairAndIdx &InsertedReg) const { 1278 return false; 1279 } 1280 1281 public: 1282 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 1283 /// a store or a load and a store into two or more instruction. If this is 1284 /// possible, returns true as well as the new instructions by reference. 1285 virtual bool 1286 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, 1287 bool UnfoldLoad, bool UnfoldStore, 1288 SmallVectorImpl<MachineInstr *> &NewMIs) const { 1289 return false; 1290 } 1291 1292 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 1293 SmallVectorImpl<SDNode *> &NewNodes) const { 1294 return false; 1295 } 1296 1297 /// Returns the opcode of the would be new 1298 /// instruction after load / store are unfolded from an instruction of the 1299 /// specified opcode. It returns zero if the specified unfolding is not 1300 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 1301 /// index of the operand which will hold the register holding the loaded 1302 /// value. 1303 virtual unsigned 1304 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, 1305 unsigned *LoadRegIndex = nullptr) const { 1306 return 0; 1307 } 1308 1309 /// This is used by the pre-regalloc scheduler to determine if two loads are 1310 /// loading from the same base address. It should only return true if the base 1311 /// pointers are the same and the only differences between the two addresses 1312 /// are the offset. It also returns the offsets by reference. 1313 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 1314 int64_t &Offset1, 1315 int64_t &Offset2) const { 1316 return false; 1317 } 1318 1319 /// This is a used by the pre-regalloc scheduler to determine (in conjunction 1320 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together. 1321 /// On some targets if two loads are loading from 1322 /// addresses in the same cache line, it's better if they are scheduled 1323 /// together. This function takes two integers that represent the load offsets 1324 /// from the common base address. It returns true if it decides it's desirable 1325 /// to schedule the two loads together. "NumLoads" is the number of loads that 1326 /// have already been scheduled after Load1. 1327 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 1328 int64_t Offset1, int64_t Offset2, 1329 unsigned NumLoads) const { 1330 return false; 1331 } 1332 1333 /// Get the base operand and byte offset of an instruction that reads/writes 1334 /// memory. This is a convenience function for callers that are only prepared 1335 /// to handle a single base operand. 1336 bool getMemOperandWithOffset(const MachineInstr &MI, 1337 const MachineOperand *&BaseOp, int64_t &Offset, 1338 bool &OffsetIsScalable, 1339 const TargetRegisterInfo *TRI) const; 1340 1341 /// Get zero or more base operands and the byte offset of an instruction that 1342 /// reads/writes memory. Note that there may be zero base operands if the 1343 /// instruction accesses a constant address. 1344 /// It returns false if MI does not read/write memory. 1345 /// It returns false if base operands and offset could not be determined. 1346 /// It is not guaranteed to always recognize base operands and offsets in all 1347 /// cases. 1348 virtual bool getMemOperandsWithOffsetWidth( 1349 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps, 1350 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, 1351 const TargetRegisterInfo *TRI) const { 1352 return false; 1353 } 1354 1355 /// Return true if the instruction contains a base register and offset. If 1356 /// true, the function also sets the operand position in the instruction 1357 /// for the base register and offset. 1358 virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, 1359 unsigned &BasePos, 1360 unsigned &OffsetPos) const { 1361 return false; 1362 } 1363 1364 /// Target dependent implementation to get the values constituting the address 1365 /// MachineInstr that is accessing memory. These values are returned as a 1366 /// struct ExtAddrMode which contains all relevant information to make up the 1367 /// address. 1368 virtual Optional<ExtAddrMode> 1369 getAddrModeFromMemoryOp(const MachineInstr &MemI, 1370 const TargetRegisterInfo *TRI) const { 1371 return None; 1372 } 1373 1374 /// Returns true if MI's Def is NullValueReg, and the MI 1375 /// does not change the Zero value. i.e. cases such as rax = shr rax, X where 1376 /// NullValueReg = rax. Note that if the NullValueReg is non-zero, this 1377 /// function can return true even if becomes zero. Specifically cases such as 1378 /// NullValueReg = shl NullValueReg, 63. 1379 virtual bool preservesZeroValueInReg(const MachineInstr *MI, 1380 const Register NullValueReg, 1381 const TargetRegisterInfo *TRI) const { 1382 return false; 1383 } 1384 1385 /// If the instruction is an increment of a constant value, return the amount. 1386 virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const { 1387 return false; 1388 } 1389 1390 /// Returns true if the two given memory operations should be scheduled 1391 /// adjacent. Note that you have to add: 1392 /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); 1393 /// or 1394 /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 1395 /// to TargetPassConfig::createMachineScheduler() to have an effect. 1396 /// 1397 /// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations. 1398 /// \p NumLoads is the number of loads that will be in the cluster if this 1399 /// hook returns true. 1400 /// \p NumBytes is the number of bytes that will be loaded from all the 1401 /// clustered loads if this hook returns true. 1402 virtual bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1, 1403 ArrayRef<const MachineOperand *> BaseOps2, 1404 unsigned NumLoads, unsigned NumBytes) const { 1405 llvm_unreachable("target did not implement shouldClusterMemOps()"); 1406 } 1407 1408 /// Reverses the branch condition of the specified condition list, 1409 /// returning false on success and true if it cannot be reversed. 1410 virtual bool 1411 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 1412 return true; 1413 } 1414 1415 /// Insert a noop into the instruction stream at the specified point. 1416 virtual void insertNoop(MachineBasicBlock &MBB, 1417 MachineBasicBlock::iterator MI) const; 1418 1419 /// Insert noops into the instruction stream at the specified point. 1420 virtual void insertNoops(MachineBasicBlock &MBB, 1421 MachineBasicBlock::iterator MI, 1422 unsigned Quantity) const; 1423 1424 /// Return the noop instruction to use for a noop. 1425 virtual MCInst getNop() const; 1426 1427 /// Return true for post-incremented instructions. 1428 virtual bool isPostIncrement(const MachineInstr &MI) const { return false; } 1429 1430 /// Returns true if the instruction is already predicated. 1431 virtual bool isPredicated(const MachineInstr &MI) const { return false; } 1432 1433 // Returns a MIRPrinter comment for this machine operand. 1434 virtual std::string 1435 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, 1436 unsigned OpIdx, const TargetRegisterInfo *TRI) const; 1437 1438 /// Returns true if the instruction is a 1439 /// terminator instruction that has not been predicated. 1440 bool isUnpredicatedTerminator(const MachineInstr &MI) const; 1441 1442 /// Returns true if MI is an unconditional tail call. 1443 virtual bool isUnconditionalTailCall(const MachineInstr &MI) const { 1444 return false; 1445 } 1446 1447 /// Returns true if the tail call can be made conditional on BranchCond. 1448 virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond, 1449 const MachineInstr &TailCall) const { 1450 return false; 1451 } 1452 1453 /// Replace the conditional branch in MBB with a conditional tail call. 1454 virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, 1455 SmallVectorImpl<MachineOperand> &Cond, 1456 const MachineInstr &TailCall) const { 1457 llvm_unreachable("Target didn't implement replaceBranchWithTailCall!"); 1458 } 1459 1460 /// Convert the instruction into a predicated instruction. 1461 /// It returns true if the operation was successful. 1462 virtual bool PredicateInstruction(MachineInstr &MI, 1463 ArrayRef<MachineOperand> Pred) const; 1464 1465 /// Returns true if the first specified predicate 1466 /// subsumes the second, e.g. GE subsumes GT. 1467 virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 1468 ArrayRef<MachineOperand> Pred2) const { 1469 return false; 1470 } 1471 1472 /// If the specified instruction defines any predicate 1473 /// or condition code register(s) used for predication, returns true as well 1474 /// as the definition predicate(s) by reference. 1475 /// SkipDead should be set to false at any point that dead 1476 /// predicate instructions should be considered as being defined. 1477 /// A dead predicate instruction is one that is guaranteed to be removed 1478 /// after a call to PredicateInstruction. 1479 virtual bool ClobbersPredicate(MachineInstr &MI, 1480 std::vector<MachineOperand> &Pred, 1481 bool SkipDead) const { 1482 return false; 1483 } 1484 1485 /// Return true if the specified instruction can be predicated. 1486 /// By default, this returns true for every instruction with a 1487 /// PredicateOperand. 1488 virtual bool isPredicable(const MachineInstr &MI) const { 1489 return MI.getDesc().isPredicable(); 1490 } 1491 1492 /// Return true if it's safe to move a machine 1493 /// instruction that defines the specified register class. 1494 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 1495 return true; 1496 } 1497 1498 /// Test if the given instruction should be considered a scheduling boundary. 1499 /// This primarily includes labels and terminators. 1500 virtual bool isSchedulingBoundary(const MachineInstr &MI, 1501 const MachineBasicBlock *MBB, 1502 const MachineFunction &MF) const; 1503 1504 /// Measure the specified inline asm to determine an approximation of its 1505 /// length. 1506 virtual unsigned getInlineAsmLength( 1507 const char *Str, const MCAsmInfo &MAI, 1508 const TargetSubtargetInfo *STI = nullptr) const; 1509 1510 /// Allocate and return a hazard recognizer to use for this target when 1511 /// scheduling the machine instructions before register allocation. 1512 virtual ScheduleHazardRecognizer * 1513 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 1514 const ScheduleDAG *DAG) const; 1515 1516 /// Allocate and return a hazard recognizer to use for this target when 1517 /// scheduling the machine instructions before register allocation. 1518 virtual ScheduleHazardRecognizer * 1519 CreateTargetMIHazardRecognizer(const InstrItineraryData *, 1520 const ScheduleDAGMI *DAG) const; 1521 1522 /// Allocate and return a hazard recognizer to use for this target when 1523 /// scheduling the machine instructions after register allocation. 1524 virtual ScheduleHazardRecognizer * 1525 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, 1526 const ScheduleDAG *DAG) const; 1527 1528 /// Allocate and return a hazard recognizer to use for by non-scheduling 1529 /// passes. 1530 virtual ScheduleHazardRecognizer * 1531 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const { 1532 return nullptr; 1533 } 1534 1535 /// Provide a global flag for disabling the PreRA hazard recognizer that 1536 /// targets may choose to honor. 1537 bool usePreRAHazardRecognizer() const; 1538 1539 /// For a comparison instruction, return the source registers 1540 /// in SrcReg and SrcReg2 if having two register operands, and the value it 1541 /// compares against in CmpValue. Return true if the comparison instruction 1542 /// can be analyzed. 1543 virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 1544 Register &SrcReg2, int64_t &Mask, 1545 int64_t &Value) const { 1546 return false; 1547 } 1548 1549 /// See if the comparison instruction can be converted 1550 /// into something more efficient. E.g., on ARM most instructions can set the 1551 /// flags register, obviating the need for a separate CMP. 1552 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 1553 Register SrcReg2, int64_t Mask, 1554 int64_t Value, 1555 const MachineRegisterInfo *MRI) const { 1556 return false; 1557 } 1558 virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; } 1559 1560 /// Try to remove the load by folding it to a register operand at the use. 1561 /// We fold the load instructions if and only if the 1562 /// def and use are in the same BB. We only look at one load and see 1563 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 1564 /// defined by the load we are trying to fold. DefMI returns the machine 1565 /// instruction that defines FoldAsLoadDefReg, and the function returns 1566 /// the machine instruction generated due to folding. 1567 virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI, 1568 const MachineRegisterInfo *MRI, 1569 Register &FoldAsLoadDefReg, 1570 MachineInstr *&DefMI) const { 1571 return nullptr; 1572 } 1573 1574 /// 'Reg' is known to be defined by a move immediate instruction, 1575 /// try to fold the immediate into the use instruction. 1576 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 1577 /// then the caller may assume that DefMI has been erased from its parent 1578 /// block. The caller may assume that it will not be erased by this 1579 /// function otherwise. 1580 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 1581 Register Reg, MachineRegisterInfo *MRI) const { 1582 return false; 1583 } 1584 1585 /// Return the number of u-operations the given machine 1586 /// instruction will be decoded to on the target cpu. The itinerary's 1587 /// IssueWidth is the number of microops that can be dispatched each 1588 /// cycle. An instruction with zero microops takes no dispatch resources. 1589 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 1590 const MachineInstr &MI) const; 1591 1592 /// Return true for pseudo instructions that don't consume any 1593 /// machine resources in their current form. These are common cases that the 1594 /// scheduler should consider free, rather than conservatively handling them 1595 /// as instructions with no itinerary. 1596 bool isZeroCost(unsigned Opcode) const { 1597 return Opcode <= TargetOpcode::COPY; 1598 } 1599 1600 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1601 SDNode *DefNode, unsigned DefIdx, 1602 SDNode *UseNode, unsigned UseIdx) const; 1603 1604 /// Compute and return the use operand latency of a given pair of def and use. 1605 /// In most cases, the static scheduling itinerary was enough to determine the 1606 /// operand latency. But it may not be possible for instructions with variable 1607 /// number of defs / uses. 1608 /// 1609 /// This is a raw interface to the itinerary that may be directly overridden 1610 /// by a target. Use computeOperandLatency to get the best estimate of 1611 /// latency. 1612 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1613 const MachineInstr &DefMI, unsigned DefIdx, 1614 const MachineInstr &UseMI, 1615 unsigned UseIdx) const; 1616 1617 /// Compute the instruction latency of a given instruction. 1618 /// If the instruction has higher cost when predicated, it's returned via 1619 /// PredCost. 1620 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 1621 const MachineInstr &MI, 1622 unsigned *PredCost = nullptr) const; 1623 1624 virtual unsigned getPredicationCost(const MachineInstr &MI) const; 1625 1626 virtual int getInstrLatency(const InstrItineraryData *ItinData, 1627 SDNode *Node) const; 1628 1629 /// Return the default expected latency for a def based on its opcode. 1630 unsigned defaultDefLatency(const MCSchedModel &SchedModel, 1631 const MachineInstr &DefMI) const; 1632 1633 /// Return true if this opcode has high latency to its result. 1634 virtual bool isHighLatencyDef(int opc) const { return false; } 1635 1636 /// Compute operand latency between a def of 'Reg' 1637 /// and a use in the current loop. Return true if the target considered 1638 /// it 'high'. This is used by optimization passes such as machine LICM to 1639 /// determine whether it makes sense to hoist an instruction out even in a 1640 /// high register pressure situation. 1641 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 1642 const MachineRegisterInfo *MRI, 1643 const MachineInstr &DefMI, unsigned DefIdx, 1644 const MachineInstr &UseMI, 1645 unsigned UseIdx) const { 1646 return false; 1647 } 1648 1649 /// Compute operand latency of a def of 'Reg'. Return true 1650 /// if the target considered it 'low'. 1651 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, 1652 const MachineInstr &DefMI, 1653 unsigned DefIdx) const; 1654 1655 /// Perform target-specific instruction verification. 1656 virtual bool verifyInstruction(const MachineInstr &MI, 1657 StringRef &ErrInfo) const { 1658 return true; 1659 } 1660 1661 /// Return the current execution domain and bit mask of 1662 /// possible domains for instruction. 1663 /// 1664 /// Some micro-architectures have multiple execution domains, and multiple 1665 /// opcodes that perform the same operation in different domains. For 1666 /// example, the x86 architecture provides the por, orps, and orpd 1667 /// instructions that all do the same thing. There is a latency penalty if a 1668 /// register is written in one domain and read in another. 1669 /// 1670 /// This function returns a pair (domain, mask) containing the execution 1671 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain 1672 /// function can be used to change the opcode to one of the domains in the 1673 /// bit mask. Instructions whose execution domain can't be changed should 1674 /// return a 0 mask. 1675 /// 1676 /// The execution domain numbers don't have any special meaning except domain 1677 /// 0 is used for instructions that are not associated with any interesting 1678 /// execution domain. 1679 /// 1680 virtual std::pair<uint16_t, uint16_t> 1681 getExecutionDomain(const MachineInstr &MI) const { 1682 return std::make_pair(0, 0); 1683 } 1684 1685 /// Change the opcode of MI to execute in Domain. 1686 /// 1687 /// The bit (1 << Domain) must be set in the mask returned from 1688 /// getExecutionDomain(MI). 1689 virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {} 1690 1691 /// Returns the preferred minimum clearance 1692 /// before an instruction with an unwanted partial register update. 1693 /// 1694 /// Some instructions only write part of a register, and implicitly need to 1695 /// read the other parts of the register. This may cause unwanted stalls 1696 /// preventing otherwise unrelated instructions from executing in parallel in 1697 /// an out-of-order CPU. 1698 /// 1699 /// For example, the x86 instruction cvtsi2ss writes its result to bits 1700 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so 1701 /// the instruction needs to wait for the old value of the register to become 1702 /// available: 1703 /// 1704 /// addps %xmm1, %xmm0 1705 /// movaps %xmm0, (%rax) 1706 /// cvtsi2ss %rbx, %xmm0 1707 /// 1708 /// In the code above, the cvtsi2ss instruction needs to wait for the addps 1709 /// instruction before it can issue, even though the high bits of %xmm0 1710 /// probably aren't needed. 1711 /// 1712 /// This hook returns the preferred clearance before MI, measured in 1713 /// instructions. Other defs of MI's operand OpNum are avoided in the last N 1714 /// instructions before MI. It should only return a positive value for 1715 /// unwanted dependencies. If the old bits of the defined register have 1716 /// useful values, or if MI is determined to otherwise read the dependency, 1717 /// the hook should return 0. 1718 /// 1719 /// The unwanted dependency may be handled by: 1720 /// 1721 /// 1. Allocating the same register for an MI def and use. That makes the 1722 /// unwanted dependency identical to a required dependency. 1723 /// 1724 /// 2. Allocating a register for the def that has no defs in the previous N 1725 /// instructions. 1726 /// 1727 /// 3. Calling breakPartialRegDependency() with the same arguments. This 1728 /// allows the target to insert a dependency breaking instruction. 1729 /// 1730 virtual unsigned 1731 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, 1732 const TargetRegisterInfo *TRI) const { 1733 // The default implementation returns 0 for no partial register dependency. 1734 return 0; 1735 } 1736 1737 /// Return the minimum clearance before an instruction that reads an 1738 /// unused register. 1739 /// 1740 /// For example, AVX instructions may copy part of a register operand into 1741 /// the unused high bits of the destination register. 1742 /// 1743 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14 1744 /// 1745 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a 1746 /// false dependence on any previous write to %xmm0. 1747 /// 1748 /// This hook works similarly to getPartialRegUpdateClearance, except that it 1749 /// does not take an operand index. Instead sets \p OpNum to the index of the 1750 /// unused register. 1751 virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, 1752 const TargetRegisterInfo *TRI) const { 1753 // The default implementation returns 0 for no undef register dependency. 1754 return 0; 1755 } 1756 1757 /// Insert a dependency-breaking instruction 1758 /// before MI to eliminate an unwanted dependency on OpNum. 1759 /// 1760 /// If it wasn't possible to avoid a def in the last N instructions before MI 1761 /// (see getPartialRegUpdateClearance), this hook will be called to break the 1762 /// unwanted dependency. 1763 /// 1764 /// On x86, an xorps instruction can be used as a dependency breaker: 1765 /// 1766 /// addps %xmm1, %xmm0 1767 /// movaps %xmm0, (%rax) 1768 /// xorps %xmm0, %xmm0 1769 /// cvtsi2ss %rbx, %xmm0 1770 /// 1771 /// An <imp-kill> operand should be added to MI if an instruction was 1772 /// inserted. This ties the instructions together in the post-ra scheduler. 1773 /// 1774 virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, 1775 const TargetRegisterInfo *TRI) const {} 1776 1777 /// Create machine specific model for scheduling. 1778 virtual DFAPacketizer * 1779 CreateTargetScheduleState(const TargetSubtargetInfo &) const { 1780 return nullptr; 1781 } 1782 1783 /// Sometimes, it is possible for the target 1784 /// to tell, even without aliasing information, that two MIs access different 1785 /// memory addresses. This function returns true if two MIs access different 1786 /// memory addresses and false otherwise. 1787 /// 1788 /// Assumes any physical registers used to compute addresses have the same 1789 /// value for both instructions. (This is the most useful assumption for 1790 /// post-RA scheduling.) 1791 /// 1792 /// See also MachineInstr::mayAlias, which is implemented on top of this 1793 /// function. 1794 virtual bool 1795 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 1796 const MachineInstr &MIb) const { 1797 assert(MIa.mayLoadOrStore() && 1798 "MIa must load from or modify a memory location"); 1799 assert(MIb.mayLoadOrStore() && 1800 "MIb must load from or modify a memory location"); 1801 return false; 1802 } 1803 1804 /// Return the value to use for the MachineCSE's LookAheadLimit, 1805 /// which is a heuristic used for CSE'ing phys reg defs. 1806 virtual unsigned getMachineCSELookAheadLimit() const { 1807 // The default lookahead is small to prevent unprofitable quadratic 1808 // behavior. 1809 return 5; 1810 } 1811 1812 /// Return the maximal number of alias checks on memory operands. For 1813 /// instructions with more than one memory operands, the alias check on a 1814 /// single MachineInstr pair has quadratic overhead and results in 1815 /// unacceptable performance in the worst case. The limit here is to clamp 1816 /// that maximal checks performed. Usually, that's the product of memory 1817 /// operand numbers from that pair of MachineInstr to be checked. For 1818 /// instance, with two MachineInstrs with 4 and 5 memory operands 1819 /// correspondingly, a total of 20 checks are required. With this limit set to 1820 /// 16, their alias check is skipped. We choose to limit the product instead 1821 /// of the individual instruction as targets may have special MachineInstrs 1822 /// with a considerably high number of memory operands, such as `ldm` in ARM. 1823 /// Setting this limit per MachineInstr would result in either too high 1824 /// overhead or too rigid restriction. 1825 virtual unsigned getMemOperandAACheckLimit() const { return 16; } 1826 1827 /// Return an array that contains the ids of the target indices (used for the 1828 /// TargetIndex machine operand) and their names. 1829 /// 1830 /// MIR Serialization is able to serialize only the target indices that are 1831 /// defined by this method. 1832 virtual ArrayRef<std::pair<int, const char *>> 1833 getSerializableTargetIndices() const { 1834 return None; 1835 } 1836 1837 /// Decompose the machine operand's target flags into two values - the direct 1838 /// target flag value and any of bit flags that are applied. 1839 virtual std::pair<unsigned, unsigned> 1840 decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const { 1841 return std::make_pair(0u, 0u); 1842 } 1843 1844 /// Return an array that contains the direct target flag values and their 1845 /// names. 1846 /// 1847 /// MIR Serialization is able to serialize only the target flags that are 1848 /// defined by this method. 1849 virtual ArrayRef<std::pair<unsigned, const char *>> 1850 getSerializableDirectMachineOperandTargetFlags() const { 1851 return None; 1852 } 1853 1854 /// Return an array that contains the bitmask target flag values and their 1855 /// names. 1856 /// 1857 /// MIR Serialization is able to serialize only the target flags that are 1858 /// defined by this method. 1859 virtual ArrayRef<std::pair<unsigned, const char *>> 1860 getSerializableBitmaskMachineOperandTargetFlags() const { 1861 return None; 1862 } 1863 1864 /// Return an array that contains the MMO target flag values and their 1865 /// names. 1866 /// 1867 /// MIR Serialization is able to serialize only the MMO target flags that are 1868 /// defined by this method. 1869 virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>> 1870 getSerializableMachineMemOperandTargetFlags() const { 1871 return None; 1872 } 1873 1874 /// Determines whether \p Inst is a tail call instruction. Override this 1875 /// method on targets that do not properly set MCID::Return and MCID::Call on 1876 /// tail call instructions." 1877 virtual bool isTailCall(const MachineInstr &Inst) const { 1878 return Inst.isReturn() && Inst.isCall(); 1879 } 1880 1881 /// True if the instruction is bound to the top of its basic block and no 1882 /// other instructions shall be inserted before it. This can be implemented 1883 /// to prevent register allocator to insert spills before such instructions. 1884 virtual bool isBasicBlockPrologue(const MachineInstr &MI) const { 1885 return false; 1886 } 1887 1888 /// During PHI eleimination lets target to make necessary checks and 1889 /// insert the copy to the PHI destination register in a target specific 1890 /// manner. 1891 virtual MachineInstr *createPHIDestinationCopy( 1892 MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, 1893 const DebugLoc &DL, Register Src, Register Dst) const { 1894 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst) 1895 .addReg(Src); 1896 } 1897 1898 /// During PHI eleimination lets target to make necessary checks and 1899 /// insert the copy to the PHI destination register in a target specific 1900 /// manner. 1901 virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB, 1902 MachineBasicBlock::iterator InsPt, 1903 const DebugLoc &DL, Register Src, 1904 unsigned SrcSubReg, 1905 Register Dst) const { 1906 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst) 1907 .addReg(Src, 0, SrcSubReg); 1908 } 1909 1910 /// Returns a \p outliner::OutlinedFunction struct containing target-specific 1911 /// information for a set of outlining candidates. 1912 virtual outliner::OutlinedFunction getOutliningCandidateInfo( 1913 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const { 1914 llvm_unreachable( 1915 "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!"); 1916 } 1917 1918 /// Optional target hook to create the LLVM IR attributes for the outlined 1919 /// function. If overridden, the overriding function must call the default 1920 /// implementation. 1921 virtual void mergeOutliningCandidateAttributes( 1922 Function &F, std::vector<outliner::Candidate> &Candidates) const; 1923 1924 /// Returns how or if \p MI should be outlined. 1925 virtual outliner::InstrType 1926 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const { 1927 llvm_unreachable( 1928 "Target didn't implement TargetInstrInfo::getOutliningType!"); 1929 } 1930 1931 /// Optional target hook that returns true if \p MBB is safe to outline from, 1932 /// and returns any target-specific information in \p Flags. 1933 virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 1934 unsigned &Flags) const; 1935 1936 /// Insert a custom frame for outlined functions. 1937 virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 1938 const outliner::OutlinedFunction &OF) const { 1939 llvm_unreachable( 1940 "Target didn't implement TargetInstrInfo::buildOutlinedFrame!"); 1941 } 1942 1943 /// Insert a call to an outlined function into the program. 1944 /// Returns an iterator to the spot where we inserted the call. This must be 1945 /// implemented by the target. 1946 virtual MachineBasicBlock::iterator 1947 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 1948 MachineBasicBlock::iterator &It, MachineFunction &MF, 1949 outliner::Candidate &C) const { 1950 llvm_unreachable( 1951 "Target didn't implement TargetInstrInfo::insertOutlinedCall!"); 1952 } 1953 1954 /// Return true if the function can safely be outlined from. 1955 /// A function \p MF is considered safe for outlining if an outlined function 1956 /// produced from instructions in F will produce a program which produces the 1957 /// same output for any set of given inputs. 1958 virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 1959 bool OutlineFromLinkOnceODRs) const { 1960 llvm_unreachable("Target didn't implement " 1961 "TargetInstrInfo::isFunctionSafeToOutlineFrom!"); 1962 } 1963 1964 /// Return true if the function should be outlined from by default. 1965 virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const { 1966 return false; 1967 } 1968 1969 /// Produce the expression describing the \p MI loading a value into 1970 /// the physical register \p Reg. This hook should only be used with 1971 /// \p MIs belonging to VReg-less functions. 1972 virtual Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, 1973 Register Reg) const; 1974 1975 /// Given the generic extension instruction \p ExtMI, returns true if this 1976 /// extension is a likely candidate for being folded into an another 1977 /// instruction. 1978 virtual bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, 1979 MachineRegisterInfo &MRI) const { 1980 return false; 1981 } 1982 1983 /// Return MIR formatter to format/parse MIR operands. Target can override 1984 /// this virtual function and return target specific MIR formatter. 1985 virtual const MIRFormatter *getMIRFormatter() const { 1986 if (!Formatter.get()) 1987 Formatter = std::make_unique<MIRFormatter>(); 1988 return Formatter.get(); 1989 } 1990 1991 /// Returns the target-specific default value for tail duplication. 1992 /// This value will be used if the tail-dup-placement-threshold argument is 1993 /// not provided. 1994 virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const { 1995 return OptLevel >= CodeGenOpt::Aggressive ? 4 : 2; 1996 } 1997 1998 /// Returns the callee operand from the given \p MI. 1999 virtual const MachineOperand &getCalleeOperand(const MachineInstr &MI) const { 2000 return MI.getOperand(0); 2001 } 2002 2003 private: 2004 mutable std::unique_ptr<MIRFormatter> Formatter; 2005 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode; 2006 unsigned CatchRetOpcode; 2007 unsigned ReturnOpcode; 2008 }; 2009 2010 /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair. 2011 template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> { 2012 using RegInfo = DenseMapInfo<unsigned>; 2013 2014 static inline TargetInstrInfo::RegSubRegPair getEmptyKey() { 2015 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(), 2016 RegInfo::getEmptyKey()); 2017 } 2018 2019 static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() { 2020 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(), 2021 RegInfo::getTombstoneKey()); 2022 } 2023 2024 /// Reuse getHashValue implementation from 2025 /// std::pair<unsigned, unsigned>. 2026 static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) { 2027 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg); 2028 return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal); 2029 } 2030 2031 static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, 2032 const TargetInstrInfo::RegSubRegPair &RHS) { 2033 return RegInfo::isEqual(LHS.Reg, RHS.Reg) && 2034 RegInfo::isEqual(LHS.SubReg, RHS.SubReg); 2035 } 2036 }; 2037 2038 } // end namespace llvm 2039 2040 #endif // LLVM_CODEGEN_TARGETINSTRINFO_H 2041