1 //===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the subtarget options of a Target machine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H
14 #define LLVM_CODEGEN_TARGETSUBTARGETINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/CodeGen/PBQPRAConstraint.h"
20 #include "llvm/CodeGen/SchedulerRegistry.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/CodeGen.h"
23 #include <memory>
24 #include <vector>
25 
26 namespace llvm {
27 
28 class APInt;
29 class MachineFunction;
30 class ScheduleDAGMutation;
31 class CallLowering;
32 class InlineAsmLowering;
33 class InstrItineraryData;
34 struct InstrStage;
35 class InstructionSelector;
36 class LegalizerInfo;
37 class MachineInstr;
38 struct MachineSchedPolicy;
39 struct MCReadAdvanceEntry;
40 struct MCWriteLatencyEntry;
41 struct MCWriteProcResEntry;
42 class RegisterBankInfo;
43 class SDep;
44 class SelectionDAGTargetInfo;
45 class SUnit;
46 class TargetFrameLowering;
47 class TargetInstrInfo;
48 class TargetLowering;
49 class TargetRegisterClass;
50 class TargetRegisterInfo;
51 class TargetSchedModel;
52 class Triple;
53 
54 //===----------------------------------------------------------------------===//
55 ///
56 /// TargetSubtargetInfo - Generic base class for all target subtargets.  All
57 /// Target-specific options that control code generation and printing should
58 /// be exposed through a TargetSubtargetInfo-derived class.
59 ///
60 class TargetSubtargetInfo : public MCSubtargetInfo {
61 protected: // Can only create subclasses...
62   TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
63                       StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
64                       ArrayRef<SubtargetSubTypeKV> PD,
65                       const MCWriteProcResEntry *WPR,
66                       const MCWriteLatencyEntry *WL,
67                       const MCReadAdvanceEntry *RA, const InstrStage *IS,
68                       const unsigned *OC, const unsigned *FP);
69 
70 public:
71   // AntiDepBreakMode - Type of anti-dependence breaking that should
72   // be performed before post-RA scheduling.
73   using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
74   using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>;
75 
76   TargetSubtargetInfo() = delete;
77   TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
78   TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete;
79   ~TargetSubtargetInfo() override;
80 
81   virtual bool isXRaySupported() const { return false; }
82 
83   // Interfaces to the major aspects of target machine information:
84   //
85   // -- Instruction opcode and operand information
86   // -- Pipelines and scheduling information
87   // -- Stack frame information
88   // -- Selection DAG lowering information
89   // -- Call lowering information
90   //
91   // N.B. These objects may change during compilation. It's not safe to cache
92   // them between functions.
93   virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
94   virtual const TargetFrameLowering *getFrameLowering() const {
95     return nullptr;
96   }
97   virtual const TargetLowering *getTargetLowering() const { return nullptr; }
98   virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const {
99     return nullptr;
100   }
101   virtual const CallLowering *getCallLowering() const { return nullptr; }
102 
103   virtual const InlineAsmLowering *getInlineAsmLowering() const {
104     return nullptr;
105   }
106 
107   // FIXME: This lets targets specialize the selector by subtarget (which lets
108   // us do things like a dedicated avx512 selector).  However, we might want
109   // to also specialize selectors by MachineFunction, which would let us be
110   // aware of optsize/optnone and such.
111   virtual InstructionSelector *getInstructionSelector() const {
112     return nullptr;
113   }
114 
115   /// Target can subclass this hook to select a different DAG scheduler.
116   virtual RegisterScheduler::FunctionPassCtor
117       getDAGScheduler(CodeGenOpt::Level) const {
118     return nullptr;
119   }
120 
121   virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
122 
123   /// getRegisterInfo - If register information is available, return it.  If
124   /// not, return null.
125   virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
126 
127   /// If the information for the register banks is available, return it.
128   /// Otherwise return nullptr.
129   virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; }
130 
131   /// getInstrItineraryData - Returns instruction itinerary data for the target
132   /// or specific subtarget.
133   virtual const InstrItineraryData *getInstrItineraryData() const {
134     return nullptr;
135   }
136 
137   /// Resolve a SchedClass at runtime, where SchedClass identifies an
138   /// MCSchedClassDesc with the isVariant property. This may return the ID of
139   /// another variant SchedClass, but repeated invocation must quickly terminate
140   /// in a nonvariant SchedClass.
141   virtual unsigned resolveSchedClass(unsigned SchedClass,
142                                      const MachineInstr *MI,
143                                      const TargetSchedModel *SchedModel) const {
144     return 0;
145   }
146 
147   /// Returns true if MI is a dependency breaking zero-idiom instruction for the
148   /// subtarget.
149   ///
150   /// This function also sets bits in Mask related to input operands that
151   /// are not in a data dependency relationship.  There is one bit for each
152   /// machine operand; implicit operands follow explicit operands in the bit
153   /// representation used for Mask.  An empty (i.e. a mask with all bits
154   /// cleared) means: data dependencies are "broken" for all the explicit input
155   /// machine operands of MI.
156   virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
157     return false;
158   }
159 
160   /// Returns true if MI is a dependency breaking instruction for the subtarget.
161   ///
162   /// Similar in behavior to `isZeroIdiom`. However, it knows how to identify
163   /// all dependency breaking instructions (i.e. not just zero-idioms).
164   ///
165   /// As for `isZeroIdiom`, this method returns a mask of "broken" dependencies.
166   /// (See method `isZeroIdiom` for a detailed description of Mask).
167   virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
168     return isZeroIdiom(MI, Mask);
169   }
170 
171   /// Returns true if MI is a candidate for move elimination.
172   ///
173   /// A candidate for move elimination may be optimized out at register renaming
174   /// stage. Subtargets can specify the set of optimizable moves by
175   /// instantiating tablegen class `IsOptimizableRegisterMove` (see
176   /// llvm/Target/TargetInstrPredicate.td).
177   ///
178   /// SubtargetEmitter is responsible for processing all the definitions of class
179   /// IsOptimizableRegisterMove, and auto-generate an override for this method.
180   virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const {
181     return false;
182   }
183 
184   /// True if the subtarget should run MachineScheduler after aggressive
185   /// coalescing.
186   ///
187   /// This currently replaces the SelectionDAG scheduler with the "source" order
188   /// scheduler (though see below for an option to turn this off and use the
189   /// TargetLowering preference). It does not yet disable the postRA scheduler.
190   virtual bool enableMachineScheduler() const;
191 
192   /// True if the machine scheduler should disable the TLI preference
193   /// for preRA scheduling with the source level scheduler.
194   virtual bool enableMachineSchedDefaultSched() const { return true; }
195 
196   /// True if the subtarget should run MachinePipeliner
197   virtual bool enableMachinePipeliner() const { return true; };
198 
199   /// True if the subtarget should enable joining global copies.
200   ///
201   /// By default this is enabled if the machine scheduler is enabled, but
202   /// can be overridden.
203   virtual bool enableJoinGlobalCopies() const;
204 
205   /// True if the subtarget should run a scheduler after register allocation.
206   ///
207   /// By default this queries the PostRAScheduling bit in the scheduling model
208   /// which is the preferred way to influence this.
209   virtual bool enablePostRAScheduler() const;
210 
211   /// True if the subtarget should run a machine scheduler after register
212   /// allocation.
213   virtual bool enablePostRAMachineScheduler() const;
214 
215   /// True if the subtarget should run the atomic expansion pass.
216   virtual bool enableAtomicExpand() const;
217 
218   /// True if the subtarget should run the indirectbr expansion pass.
219   virtual bool enableIndirectBrExpand() const;
220 
221   /// Override generic scheduling policy within a region.
222   ///
223   /// This is a convenient way for targets that don't provide any custom
224   /// scheduling heuristics (no custom MachineSchedStrategy) to make
225   /// changes to the generic scheduling policy.
226   virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
227                                    unsigned NumRegionInstrs) const {}
228 
229   // Perform target-specific adjustments to the latency of a schedule
230   // dependency.
231   // If a pair of operands is associated with the schedule dependency, DefOpIdx
232   // and UseOpIdx are the indices of the operands in Def and Use, respectively.
233   // Otherwise, either may be -1.
234   virtual void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use,
235                                      int UseOpIdx, SDep &Dep) const {}
236 
237   // For use with PostRAScheduling: get the anti-dependence breaking that should
238   // be performed before post-RA scheduling.
239   virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
240 
241   // For use with PostRAScheduling: in CriticalPathRCs, return any register
242   // classes that should only be considered for anti-dependence breaking if they
243   // are on the critical path.
244   virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
245     return CriticalPathRCs.clear();
246   }
247 
248   // Provide an ordered list of schedule DAG mutations for the post-RA
249   // scheduler.
250   virtual void getPostRAMutations(
251       std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
252   }
253 
254   // Provide an ordered list of schedule DAG mutations for the machine
255   // pipeliner.
256   virtual void getSMSMutations(
257       std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
258   }
259 
260   /// Default to DFA for resource management, return false when target will use
261   /// ProcResource in InstrSchedModel instead.
262   virtual bool useDFAforSMS() const { return true; }
263 
264   // For use with PostRAScheduling: get the minimum optimization level needed
265   // to enable post-RA scheduling.
266   virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
267     return CodeGenOpt::Default;
268   }
269 
270   /// True if the subtarget should run the local reassignment
271   /// heuristic of the register allocator.
272   /// This heuristic may be compile time intensive, \p OptLevel provides
273   /// a finer grain to tune the register allocator.
274   virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
275 
276   /// Enable use of alias analysis during code generation (during MI
277   /// scheduling, DAGCombine, etc.).
278   virtual bool useAA() const;
279 
280   /// \brief Sink addresses into blocks using GEP instructions rather than
281   /// pointer casts and arithmetic.
282   virtual bool addrSinkUsingGEPs() const {
283     return useAA();
284   }
285 
286   /// Enable the use of the early if conversion pass.
287   virtual bool enableEarlyIfConversion() const { return false; }
288 
289   /// Return PBQPConstraint(s) for the target.
290   ///
291   /// Override to provide custom PBQP constraints.
292   virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
293     return nullptr;
294   }
295 
296   /// Enable tracking of subregister liveness in register allocator.
297   /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
298   /// possible.
299   virtual bool enableSubRegLiveness() const { return false; }
300 
301   /// This is called after a .mir file was loaded.
302   virtual void mirFileLoaded(MachineFunction &MF) const;
303 
304   /// True if the register allocator should use the allocation orders exactly as
305   /// written in the tablegen descriptions, false if it should allocate
306   /// the specified physical register later if is it callee-saved.
307   virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
308                                            unsigned PhysReg) const {
309     return false;
310   }
311 };
312 
313 } // end namespace llvm
314 
315 #endif // LLVM_CODEGEN_TARGETSUBTARGETINFO_H
316