1//===- IntrinsicsAMDGPU.td - Defines AMDGPU intrinsics -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines all of the R600-specific intrinsics. 10// 11//===----------------------------------------------------------------------===// 12 13class AMDGPUReadPreloadRegisterIntrinsic 14 : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 15 16class AMDGPUReadPreloadRegisterIntrinsicNamed<string name> 17 : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>, GCCBuiltin<name>; 18 19// Used to tag image and resource intrinsics with information used to generate 20// mem operands. 21class AMDGPURsrcIntrinsic<int rsrcarg, bit isimage = false> { 22 int RsrcArg = rsrcarg; 23 bit IsImage = isimage; 24} 25 26let TargetPrefix = "r600" in { 27 28multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz { 29 def _x : AMDGPUReadPreloadRegisterIntrinsic; 30 def _y : AMDGPUReadPreloadRegisterIntrinsic; 31 def _z : AMDGPUReadPreloadRegisterIntrinsic; 32} 33 34multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz_named<string prefix> { 35 def _x : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_x")>; 36 def _y : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_y")>; 37 def _z : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_z")>; 38} 39 40defm int_r600_read_global_size : AMDGPUReadPreloadRegisterIntrinsic_xyz_named 41 <"__builtin_r600_read_global_size">; 42defm int_r600_read_ngroups : AMDGPUReadPreloadRegisterIntrinsic_xyz_named 43 <"__builtin_r600_read_ngroups">; 44defm int_r600_read_tgid : AMDGPUReadPreloadRegisterIntrinsic_xyz_named 45 <"__builtin_r600_read_tgid">; 46 47defm int_r600_read_local_size : AMDGPUReadPreloadRegisterIntrinsic_xyz; 48defm int_r600_read_tidig : AMDGPUReadPreloadRegisterIntrinsic_xyz; 49 50def int_r600_group_barrier : GCCBuiltin<"__builtin_r600_group_barrier">, 51 Intrinsic<[], [], [IntrConvergent, IntrWillReturn]>; 52 53// AS 7 is PARAM_I_ADDRESS, used for kernel arguments 54def int_r600_implicitarg_ptr : 55 GCCBuiltin<"__builtin_r600_implicitarg_ptr">, 56 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 7>], [], 57 [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 58 59def int_r600_rat_store_typed : 60 // 1st parameter: Data 61 // 2nd parameter: Index 62 // 3rd parameter: Constant RAT ID 63 Intrinsic<[], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], [IntrWillReturn]>, 64 GCCBuiltin<"__builtin_r600_rat_store_typed">; 65 66def int_r600_recipsqrt_ieee : Intrinsic< 67 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 68>; 69 70def int_r600_recipsqrt_clamped : Intrinsic< 71 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 72>; 73 74def int_r600_cube : Intrinsic< 75 [llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 76>; 77 78def int_r600_store_stream_output : Intrinsic< 79 [], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrWillReturn] 80>; 81 82class TextureIntrinsicFloatInput : Intrinsic<[llvm_v4f32_ty], [ 83 llvm_v4f32_ty, // Coord 84 llvm_i32_ty, // offset_x 85 llvm_i32_ty, // offset_y, 86 llvm_i32_ty, // offset_z, 87 llvm_i32_ty, // resource_id 88 llvm_i32_ty, // samplerid 89 llvm_i32_ty, // coord_type_x 90 llvm_i32_ty, // coord_type_y 91 llvm_i32_ty, // coord_type_z 92 llvm_i32_ty], // coord_type_w 93 [IntrNoMem, IntrWillReturn] 94>; 95 96class TextureIntrinsicInt32Input : Intrinsic<[llvm_v4i32_ty], [ 97 llvm_v4i32_ty, // Coord 98 llvm_i32_ty, // offset_x 99 llvm_i32_ty, // offset_y, 100 llvm_i32_ty, // offset_z, 101 llvm_i32_ty, // resource_id 102 llvm_i32_ty, // samplerid 103 llvm_i32_ty, // coord_type_x 104 llvm_i32_ty, // coord_type_y 105 llvm_i32_ty, // coord_type_z 106 llvm_i32_ty], // coord_type_w 107 [IntrNoMem, IntrWillReturn] 108>; 109 110def int_r600_store_swizzle : 111 Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrWillReturn] 112>; 113 114def int_r600_tex : TextureIntrinsicFloatInput; 115def int_r600_texc : TextureIntrinsicFloatInput; 116def int_r600_txl : TextureIntrinsicFloatInput; 117def int_r600_txlc : TextureIntrinsicFloatInput; 118def int_r600_txb : TextureIntrinsicFloatInput; 119def int_r600_txbc : TextureIntrinsicFloatInput; 120def int_r600_txf : TextureIntrinsicInt32Input; 121def int_r600_txq : TextureIntrinsicInt32Input; 122def int_r600_ddx : TextureIntrinsicFloatInput; 123def int_r600_ddy : TextureIntrinsicFloatInput; 124 125def int_r600_dot4 : Intrinsic<[llvm_float_ty], 126 [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 127>; 128 129def int_r600_kill : Intrinsic<[], [llvm_float_ty], [IntrWillReturn]>; 130 131} // End TargetPrefix = "r600" 132 133let TargetPrefix = "amdgcn" in { 134 135//===----------------------------------------------------------------------===// 136// ABI Special Intrinsics 137//===----------------------------------------------------------------------===// 138 139defm int_amdgcn_workitem_id : AMDGPUReadPreloadRegisterIntrinsic_xyz; 140defm int_amdgcn_workgroup_id : AMDGPUReadPreloadRegisterIntrinsic_xyz_named 141 <"__builtin_amdgcn_workgroup_id">; 142 143def int_amdgcn_dispatch_ptr : 144 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [], 145 [Align<RetIndex, 4>, IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 146 147def int_amdgcn_queue_ptr : 148 GCCBuiltin<"__builtin_amdgcn_queue_ptr">, 149 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [], 150 [Align<RetIndex, 4>, IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 151 152def int_amdgcn_kernarg_segment_ptr : 153 GCCBuiltin<"__builtin_amdgcn_kernarg_segment_ptr">, 154 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [], 155 [Align<RetIndex, 4>, IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 156 157def int_amdgcn_implicitarg_ptr : 158 GCCBuiltin<"__builtin_amdgcn_implicitarg_ptr">, 159 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [], 160 [Align<RetIndex, 4>, IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 161 162def int_amdgcn_groupstaticsize : 163 GCCBuiltin<"__builtin_amdgcn_groupstaticsize">, 164 Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 165 166def int_amdgcn_dispatch_id : 167 GCCBuiltin<"__builtin_amdgcn_dispatch_id">, 168 Intrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 169 170def int_amdgcn_implicit_buffer_ptr : 171 GCCBuiltin<"__builtin_amdgcn_implicit_buffer_ptr">, 172 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [], 173 [Align<RetIndex, 4>, IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 174 175// Set EXEC to the 64-bit value given. 176// This is always moved to the beginning of the basic block. 177// FIXME: Should be mangled for wave size. 178def int_amdgcn_init_exec : Intrinsic<[], 179 [llvm_i64_ty], // 64-bit literal constant 180 [IntrConvergent, ImmArg<ArgIndex<0>>]>; 181 182// Set EXEC according to a thread count packed in an SGPR input: 183// thread_count = (input >> bitoffset) & 0x7f; 184// This is always moved to the beginning of the basic block. 185// Note: only inreg arguments to the parent function are valid as 186// inputs to this intrinsic, computed values cannot be used. 187def int_amdgcn_init_exec_from_input : Intrinsic<[], 188 [llvm_i32_ty, // 32-bit SGPR input 189 llvm_i32_ty], // bit offset of the thread count 190 [IntrConvergent, ImmArg<ArgIndex<1>>]>; 191 192def int_amdgcn_wavefrontsize : 193 GCCBuiltin<"__builtin_amdgcn_wavefrontsize">, 194 Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 195 196 197//===----------------------------------------------------------------------===// 198// Instruction Intrinsics 199//===----------------------------------------------------------------------===// 200 201// The first parameter is s_sendmsg immediate (i16), 202// the second one is copied to m0 203def int_amdgcn_s_sendmsg : GCCBuiltin<"__builtin_amdgcn_s_sendmsg">, 204 Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], 205 [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects]>; 206def int_amdgcn_s_sendmsghalt : GCCBuiltin<"__builtin_amdgcn_s_sendmsghalt">, 207 Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], 208 [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects]>; 209 210def int_amdgcn_s_barrier : GCCBuiltin<"__builtin_amdgcn_s_barrier">, 211 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn]>; 212 213def int_amdgcn_wave_barrier : GCCBuiltin<"__builtin_amdgcn_wave_barrier">, 214 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn]>; 215 216def int_amdgcn_s_waitcnt : GCCBuiltin<"__builtin_amdgcn_s_waitcnt">, 217 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 218 219def int_amdgcn_div_scale : Intrinsic< 220 // 1st parameter: Numerator 221 // 2nd parameter: Denominator 222 // 3rd parameter: Select quotient. Must equal Numerator or Denominator. 223 // (0 = Denominator, 1 = Numerator). 224 [llvm_anyfloat_ty, llvm_i1_ty], 225 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty], 226 [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>, IntrWillReturn] 227>; 228 229def int_amdgcn_div_fmas : Intrinsic<[llvm_anyfloat_ty], 230 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty], 231 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 232>; 233 234def int_amdgcn_div_fixup : Intrinsic<[llvm_anyfloat_ty], 235 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 236 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 237>; 238 239// Look Up 2.0 / pi src0 with segment select src1[4:0] 240def int_amdgcn_trig_preop : Intrinsic< 241 [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], 242 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 243>; 244 245def int_amdgcn_sin : Intrinsic< 246 [llvm_anyfloat_ty], [LLVMMatchType<0>], 247 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 248>; 249 250def int_amdgcn_cos : Intrinsic< 251 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 252>; 253 254def int_amdgcn_log_clamp : Intrinsic< 255 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 256>; 257 258def int_amdgcn_fmul_legacy : GCCBuiltin<"__builtin_amdgcn_fmul_legacy">, 259 Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], 260 [IntrNoMem, IntrSpeculatable, IntrWillReturn, Commutative] 261>; 262 263// Fused single-precision multiply-add with legacy behaviour for the multiply, 264// which is that +/- 0.0 * anything (even NaN or infinity) is +0.0. This is 265// intended for use on subtargets that have the v_fma_legacy_f32 and/or 266// v_fmac_legacy_f32 instructions. (Note that v_fma_legacy_f16 is unrelated and 267// has a completely different kind of legacy behaviour.) 268def int_amdgcn_fma_legacy : 269 Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], 270 [IntrNoMem, IntrSpeculatable, IntrWillReturn, Commutative] 271>; 272 273def int_amdgcn_rcp : Intrinsic< 274 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 275>; 276 277def int_amdgcn_rcp_legacy : GCCBuiltin<"__builtin_amdgcn_rcp_legacy">, 278 Intrinsic<[llvm_float_ty], [llvm_float_ty], 279 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 280>; 281 282def int_amdgcn_sqrt : Intrinsic< 283 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 284>; 285 286def int_amdgcn_rsq : Intrinsic< 287 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 288>; 289 290def int_amdgcn_rsq_legacy : GCCBuiltin<"__builtin_amdgcn_rsq_legacy">, 291 Intrinsic< 292 [llvm_float_ty], [llvm_float_ty], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 293>; 294 295// out = 1.0 / sqrt(a) result clamped to +/- max_float. 296def int_amdgcn_rsq_clamp : Intrinsic< 297 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 298 299def int_amdgcn_ldexp : Intrinsic< 300 [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], 301 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 302>; 303 304def int_amdgcn_frexp_mant : Intrinsic< 305 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 306>; 307 308def int_amdgcn_frexp_exp : Intrinsic< 309 [llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 310>; 311 312// v_fract is buggy on SI/CI. It mishandles infinities, may return 1.0 313// and always uses rtz, so is not suitable for implementing the OpenCL 314// fract function. It should be ok on VI. 315def int_amdgcn_fract : Intrinsic< 316 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 317>; 318 319def int_amdgcn_cvt_pkrtz : GCCBuiltin<"__builtin_amdgcn_cvt_pkrtz">, 320 Intrinsic<[llvm_v2f16_ty], [llvm_float_ty, llvm_float_ty], 321 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 322>; 323 324def int_amdgcn_cvt_pknorm_i16 : 325 GCCBuiltin<"__builtin_amdgcn_cvt_pknorm_i16">, 326 Intrinsic<[llvm_v2i16_ty], [llvm_float_ty, llvm_float_ty], 327 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 328>; 329 330def int_amdgcn_cvt_pknorm_u16 : 331 GCCBuiltin<"__builtin_amdgcn_cvt_pknorm_u16">, 332 Intrinsic<[llvm_v2i16_ty], [llvm_float_ty, llvm_float_ty], 333 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 334>; 335 336def int_amdgcn_cvt_pk_i16 : 337 GCCBuiltin<"__builtin_amdgcn_cvt_pk_i16">, 338 Intrinsic< 339 [llvm_v2i16_ty], [llvm_i32_ty, llvm_i32_ty], 340 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 341>; 342 343def int_amdgcn_cvt_pk_u16 : GCCBuiltin<"__builtin_amdgcn_cvt_pk_u16">, 344 Intrinsic<[llvm_v2i16_ty], [llvm_i32_ty, llvm_i32_ty], 345 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 346>; 347 348def int_amdgcn_class : Intrinsic< 349 [llvm_i1_ty], [llvm_anyfloat_ty, llvm_i32_ty], 350 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 351>; 352 353def int_amdgcn_fmed3 : GCCBuiltin<"__builtin_amdgcn_fmed3">, 354 Intrinsic<[llvm_anyfloat_ty], 355 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 356 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 357>; 358 359def int_amdgcn_cubeid : GCCBuiltin<"__builtin_amdgcn_cubeid">, 360 Intrinsic<[llvm_float_ty], 361 [llvm_float_ty, llvm_float_ty, llvm_float_ty], 362 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 363>; 364 365def int_amdgcn_cubema : GCCBuiltin<"__builtin_amdgcn_cubema">, 366 Intrinsic<[llvm_float_ty], 367 [llvm_float_ty, llvm_float_ty, llvm_float_ty], 368 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 369>; 370 371def int_amdgcn_cubesc : GCCBuiltin<"__builtin_amdgcn_cubesc">, 372 Intrinsic<[llvm_float_ty], 373 [llvm_float_ty, llvm_float_ty, llvm_float_ty], 374 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 375>; 376 377def int_amdgcn_cubetc : GCCBuiltin<"__builtin_amdgcn_cubetc">, 378 Intrinsic<[llvm_float_ty], 379 [llvm_float_ty, llvm_float_ty, llvm_float_ty], 380 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 381>; 382 383// v_ffbh_i32, as opposed to v_ffbh_u32. For v_ffbh_u32, llvm.ctlz 384// should be used. 385def int_amdgcn_sffbh : 386 Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], 387 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 388>; 389 390// v_mad_f32|f16/v_mac_f32|f16, selected regardless of denorm support. 391def int_amdgcn_fmad_ftz : 392 Intrinsic<[llvm_anyfloat_ty], 393 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 394 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 395>; 396 397// Fields should mirror atomicrmw 398class AMDGPUAtomicIncIntrin : Intrinsic<[llvm_anyint_ty], 399 [llvm_anyptr_ty, 400 LLVMMatchType<0>, 401 llvm_i32_ty, // ordering 402 llvm_i32_ty, // scope 403 llvm_i1_ty], // isVolatile 404 [IntrArgMemOnly, IntrWillReturn, NoCapture<ArgIndex<0>>, 405 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>], "", 406 [SDNPMemOperand] 407>; 408 409def int_amdgcn_atomic_inc : AMDGPUAtomicIncIntrin; 410def int_amdgcn_atomic_dec : AMDGPUAtomicIncIntrin; 411 412class AMDGPULDSIntrin : 413 Intrinsic<[llvm_any_ty], 414 [LLVMQualPointerType<LLVMMatchType<0>, 3>, 415 LLVMMatchType<0>, 416 llvm_i32_ty, // ordering 417 llvm_i32_ty, // scope 418 llvm_i1_ty], // isVolatile 419 [IntrArgMemOnly, IntrWillReturn, NoCapture<ArgIndex<0>>, 420 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>] 421>; 422 423// FIXME: The m0 argument should be moved after the normal arguments 424class AMDGPUDSOrderedIntrinsic : Intrinsic< 425 [llvm_i32_ty], 426 // M0 = {hi16:address, lo16:waveID}. Allow passing M0 as a pointer, so that 427 // the bit packing can be optimized at the IR level. 428 [LLVMQualPointerType<llvm_i32_ty, 2>, // IntToPtr(M0) 429 llvm_i32_ty, // value to add or swap 430 llvm_i32_ty, // ordering 431 llvm_i32_ty, // scope 432 llvm_i1_ty, // isVolatile 433 llvm_i32_ty, // ordered count index (OA index), also added to the address 434 // gfx10: bits 24-27 indicate the number of active threads/dwords 435 llvm_i1_ty, // wave release, usually set to 1 436 llvm_i1_ty], // wave done, set to 1 for the last ordered instruction 437 [IntrWillReturn, NoCapture<ArgIndex<0>>, 438 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, 439 ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>, ImmArg<ArgIndex<7>> 440 ] 441>; 442 443class AMDGPUDSAppendConsumedIntrinsic : Intrinsic< 444 [llvm_i32_ty], 445 [llvm_anyptr_ty, // LDS or GDS ptr 446 llvm_i1_ty], // isVolatile 447 [IntrConvergent, IntrWillReturn, IntrArgMemOnly, 448 NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>], 449 "", 450 [SDNPMemOperand] 451>; 452 453def int_amdgcn_ds_ordered_add : AMDGPUDSOrderedIntrinsic; 454def int_amdgcn_ds_ordered_swap : AMDGPUDSOrderedIntrinsic; 455 456// The pointer argument is assumed to be dynamically uniform if a VGPR. 457def int_amdgcn_ds_append : AMDGPUDSAppendConsumedIntrinsic; 458def int_amdgcn_ds_consume : AMDGPUDSAppendConsumedIntrinsic; 459 460def int_amdgcn_ds_fadd : AMDGPULDSIntrin; 461def int_amdgcn_ds_fmin : AMDGPULDSIntrin; 462def int_amdgcn_ds_fmax : AMDGPULDSIntrin; 463 464} // TargetPrefix = "amdgcn" 465 466// New-style image intrinsics 467 468////////////////////////////////////////////////////////////////////////// 469// Dimension-aware image intrinsics framework 470////////////////////////////////////////////////////////////////////////// 471 472// Helper class to represent (type, name) combinations of arguments. The 473// argument names are explanatory and used as DAG operand names for codegen 474// pattern matching. 475class AMDGPUArg<LLVMType ty, string name> { 476 LLVMType Type = ty; 477 string Name = name; 478} 479 480// Return [AMDGPUArg<basety, names[0]>, AMDGPUArg<LLVMMatchType<0>, names[1]>, ...] 481class makeArgList<list<string> names, LLVMType basety> { 482 list<AMDGPUArg> ret = 483 !listconcat([AMDGPUArg<basety, names[0]>], 484 !foreach(name, !tail(names), AMDGPUArg<LLVMMatchType<0>, name>)); 485} 486 487// Return arglist, with LLVMMatchType's references shifted by 'shift'. 488class arglistmatchshift<list<AMDGPUArg> arglist, int shift> { 489 list<AMDGPUArg> ret = 490 !foreach(arg, arglist, 491 !if(!isa<LLVMMatchType>(arg.Type), 492 AMDGPUArg<LLVMMatchType<!add(!cast<LLVMMatchType>(arg.Type).Number, shift)>, 493 arg.Name>, 494 arg)); 495} 496 497// Return the concatenation of the given arglists. LLVMMatchType's are adjusted 498// accordingly, and shifted by an additional 'shift'. 499class arglistconcat<list<list<AMDGPUArg>> arglists, int shift = 0> { 500 list<AMDGPUArg> ret = 501 !foldl([]<AMDGPUArg>, arglists, lhs, rhs, 502 !listconcat( 503 lhs, 504 arglistmatchshift<rhs, 505 !add(shift, !foldl(0, lhs, a, b, 506 !add(a, b.Type.isAny)))>.ret)); 507} 508 509// Represent texture/image types / dimensionality. 510class AMDGPUDimProps<bits<3> enc, string name, string asmsuffix, 511 list<string> coord_names, list<string> slice_names, 512 bit msaa = 0> { 513 AMDGPUDimProps Dim = !cast<AMDGPUDimProps>(NAME); 514 string Name = name; // e.g. "2darraymsaa" 515 string AsmSuffix = asmsuffix; // e.g. 2D_MSAA_ARRAY (used in assembly strings) 516 bits<3> Encoding = enc; 517 bit DA = 0; // DA bit in MIMG encoding 518 bit MSAA = msaa; 519 520 list<AMDGPUArg> CoordSliceArgs = 521 makeArgList<!listconcat(coord_names, slice_names), llvm_anyfloat_ty>.ret; 522 list<AMDGPUArg> CoordSliceIntArgs = 523 makeArgList<!listconcat(coord_names, slice_names), llvm_anyint_ty>.ret; 524 list<AMDGPUArg> GradientArgs = 525 makeArgList<!listconcat(!foreach(name, coord_names, "d" # name # "dh"), 526 !foreach(name, coord_names, "d" # name # "dv")), 527 llvm_anyfloat_ty>.ret; 528 529 bits<8> NumCoords = !size(CoordSliceArgs); 530 bits<8> NumGradients = !size(GradientArgs); 531} 532 533def AMDGPUDim1D : AMDGPUDimProps<0x0, "1d", "1D", ["s"], []>; 534def AMDGPUDim2D : AMDGPUDimProps<0x1, "2d", "2D", ["s", "t"], []>; 535def AMDGPUDim3D : AMDGPUDimProps<0x2, "3d", "3D", ["s", "t", "r"], []>; 536let DA = 1 in { 537 def AMDGPUDimCube : AMDGPUDimProps<0x3, "cube", "CUBE", ["s", "t"], ["face"]>; 538 def AMDGPUDim1DArray : AMDGPUDimProps<0x4, "1darray", "1D_ARRAY", ["s"], ["slice"]>; 539 def AMDGPUDim2DArray : AMDGPUDimProps<0x5, "2darray", "2D_ARRAY", ["s", "t"], ["slice"]>; 540} 541def AMDGPUDim2DMsaa : AMDGPUDimProps<0x6, "2dmsaa", "2D_MSAA", ["s", "t"], ["fragid"], 1>; 542let DA = 1 in { 543 def AMDGPUDim2DArrayMsaa : AMDGPUDimProps<0x7, "2darraymsaa", "2D_MSAA_ARRAY", ["s", "t"], ["slice", "fragid"], 1>; 544} 545 546def AMDGPUDims { 547 list<AMDGPUDimProps> NoMsaa = [AMDGPUDim1D, AMDGPUDim2D, AMDGPUDim3D, 548 AMDGPUDimCube, AMDGPUDim1DArray, 549 AMDGPUDim2DArray]; 550 list<AMDGPUDimProps> Msaa = [AMDGPUDim2DMsaa, AMDGPUDim2DArrayMsaa]; 551 list<AMDGPUDimProps> All = !listconcat(NoMsaa, Msaa); 552} 553 554// Represent sample variants, i.e. _C, _O, _B, ... and combinations thereof. 555class AMDGPUSampleVariant<string ucmod, string lcmod, list<AMDGPUArg> extra_addr> { 556 string UpperCaseMod = ucmod; 557 string LowerCaseMod = lcmod; 558 559 // {offset} {bias} {z-compare} 560 list<AMDGPUArg> ExtraAddrArgs = extra_addr; 561 bit Gradients = false; 562 563 // Name of the {lod} or {clamp} argument that is appended to the coordinates, 564 // if any. 565 string LodOrClamp = ""; 566} 567 568// AMDGPUSampleVariants: all variants supported by IMAGE_SAMPLE 569// AMDGPUSampleVariantsNoGradients: variants supported by IMAGE_GATHER4 570defset list<AMDGPUSampleVariant> AMDGPUSampleVariants = { 571 multiclass AMDGPUSampleHelper_Offset<string ucmod, string lcmod, 572 list<AMDGPUArg> extra_addr> { 573 def NAME#lcmod : AMDGPUSampleVariant<ucmod, lcmod, extra_addr>; 574 def NAME#lcmod#_o : AMDGPUSampleVariant< 575 ucmod#"_O", lcmod#"_o", !listconcat([AMDGPUArg<llvm_i32_ty, "offset">], extra_addr)>; 576 } 577 578 multiclass AMDGPUSampleHelper_Compare<string ucmod, string lcmod, 579 list<AMDGPUArg> extra_addr> { 580 defm NAME : AMDGPUSampleHelper_Offset<ucmod, lcmod, extra_addr>; 581 defm NAME : AMDGPUSampleHelper_Offset< 582 "_C"#ucmod, "_c"#lcmod, !listconcat(extra_addr, [AMDGPUArg<llvm_float_ty, "zcompare">])>; 583 } 584 585 multiclass AMDGPUSampleHelper_Clamp<string ucmod, string lcmod, 586 list<AMDGPUArg> extra_addr> { 587 defm NAME : AMDGPUSampleHelper_Compare<ucmod, lcmod, extra_addr>; 588 let LodOrClamp = "clamp" in 589 defm NAME : AMDGPUSampleHelper_Compare<ucmod#"_CL", lcmod#"_cl", extra_addr>; 590 } 591 592 defset list<AMDGPUSampleVariant> AMDGPUSampleVariantsNoGradients = { 593 defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"", "", []>; 594 defm AMDGPUSample : AMDGPUSampleHelper_Clamp< 595 "_B", "_b", [AMDGPUArg<llvm_anyfloat_ty, "bias">]>; 596 let LodOrClamp = "lod" in 597 defm AMDGPUSample : AMDGPUSampleHelper_Compare<"_L", "_l", []>; 598 defm AMDGPUSample : AMDGPUSampleHelper_Compare<"_LZ", "_lz", []>; 599 } 600 601 let Gradients = true in { 602 defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"_D", "_d", []>; 603 defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"_CD", "_cd", []>; 604 } 605} 606 607// Helper class to capture the profile of a dimension-aware image intrinsic. 608// This information is used to generate the intrinsic's type and to inform 609// codegen pattern matching. 610class AMDGPUDimProfile<string opmod, 611 AMDGPUDimProps dim> { 612 AMDGPUDimProps Dim = dim; 613 string OpMod = opmod; // the corresponding instruction is named IMAGE_OpMod 614 615 // These are intended to be overwritten by subclasses 616 bit IsSample = false; 617 bit IsAtomic = false; 618 list<LLVMType> RetTypes = []; 619 list<AMDGPUArg> DataArgs = []; 620 list<AMDGPUArg> ExtraAddrArgs = []; 621 bit Gradients = false; 622 string LodClampMip = ""; 623 624 int NumRetAndDataAnyTypes = 625 !foldl(0, !listconcat(RetTypes, !foreach(arg, DataArgs, arg.Type)), a, b, 626 !add(a, b.isAny)); 627 628 list<AMDGPUArg> AddrArgs = 629 arglistconcat<[ExtraAddrArgs, 630 !if(Gradients, dim.GradientArgs, []), 631 !listconcat(!if(IsSample, dim.CoordSliceArgs, dim.CoordSliceIntArgs), 632 !if(!empty(LodClampMip), 633 []<AMDGPUArg>, 634 [AMDGPUArg<LLVMMatchType<0>, LodClampMip>]))], 635 NumRetAndDataAnyTypes>.ret; 636 list<LLVMType> AddrTypes = !foreach(arg, AddrArgs, arg.Type); 637 list<AMDGPUArg> AddrDefaultArgs = 638 !foreach(arg, AddrArgs, 639 AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), 640 !if(IsSample, llvm_float_ty, llvm_i32_ty), arg.Type), 641 arg.Name>); 642 list<AMDGPUArg> AddrA16Args = 643 !foreach(arg, AddrArgs, 644 AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), 645 !if(IsSample, llvm_half_ty, llvm_i16_ty), arg.Type), 646 arg.Name>); 647} 648 649class AMDGPUDimProfileCopy<AMDGPUDimProfile base> : AMDGPUDimProfile<base.OpMod, base.Dim> { 650 let IsSample = base.IsSample; 651 let IsAtomic = base.IsAtomic; 652 let RetTypes = base.RetTypes; 653 let DataArgs = base.DataArgs; 654 let ExtraAddrArgs = base.ExtraAddrArgs; 655 let Gradients = base.Gradients; 656 let LodClampMip = base.LodClampMip; 657} 658 659class AMDGPUDimSampleProfile<string opmod, 660 AMDGPUDimProps dim, 661 AMDGPUSampleVariant sample> : AMDGPUDimProfile<opmod, dim> { 662 let IsSample = true; 663 let RetTypes = [llvm_any_ty]; 664 let ExtraAddrArgs = sample.ExtraAddrArgs; 665 let Gradients = sample.Gradients; 666 let LodClampMip = sample.LodOrClamp; 667} 668 669class AMDGPUDimNoSampleProfile<string opmod, 670 AMDGPUDimProps dim, 671 list<LLVMType> retty, 672 list<AMDGPUArg> dataargs, 673 bit Mip = false> : AMDGPUDimProfile<opmod, dim> { 674 let RetTypes = retty; 675 let DataArgs = dataargs; 676 let LodClampMip = !if(Mip, "mip", ""); 677} 678 679class AMDGPUDimAtomicProfile<string opmod, 680 AMDGPUDimProps dim, 681 list<AMDGPUArg> dataargs> : AMDGPUDimProfile<opmod, dim> { 682 let RetTypes = [llvm_anyint_ty]; 683 let DataArgs = dataargs; 684 let IsAtomic = true; 685} 686 687class AMDGPUDimGetResInfoProfile<AMDGPUDimProps dim> : AMDGPUDimProfile<"GET_RESINFO", dim> { 688 let RetTypes = [llvm_anyfloat_ty]; 689 let DataArgs = []; 690 let AddrArgs = [AMDGPUArg<llvm_anyint_ty, "mip">]; 691 let LodClampMip = "mip"; 692} 693 694// Helper class for figuring out image intrinsic argument indexes. 695class AMDGPUImageDimIntrinsicEval<AMDGPUDimProfile P_> { 696 int NumDataArgs = !size(P_.DataArgs); 697 int NumDmaskArgs = !not(P_.IsAtomic); 698 int NumExtraAddrArgs = !size(P_.ExtraAddrArgs); 699 int NumVAddrArgs = !size(P_.AddrArgs); 700 int NumGradientArgs = !if(P_.Gradients, !size(P_.Dim.GradientArgs), 0); 701 int NumCoordArgs = !if(P_.IsSample, !size(P_.Dim.CoordSliceArgs), !size(P_.Dim.CoordSliceIntArgs)); 702 int NumRSrcArgs = 1; 703 int NumSampArgs = !if(P_.IsSample, 2, 0); 704 int DmaskArgIndex = NumDataArgs; 705 int VAddrArgIndex = !add(DmaskArgIndex, NumDmaskArgs); 706 int GradientArgIndex = !add(VAddrArgIndex, NumExtraAddrArgs); 707 int CoordArgIndex = !add(GradientArgIndex, NumGradientArgs); 708 int LodArgIndex = !add(VAddrArgIndex, NumVAddrArgs, -1); 709 int MipArgIndex = LodArgIndex; 710 int RsrcArgIndex = !add(VAddrArgIndex, NumVAddrArgs); 711 int SampArgIndex = !add(RsrcArgIndex, NumRSrcArgs); 712 int UnormArgIndex = !add(SampArgIndex, 1); 713 int TexFailCtrlArgIndex = !add(SampArgIndex, NumSampArgs); 714 int CachePolicyArgIndex = !add(TexFailCtrlArgIndex, 1); 715} 716 717// All dimension-aware intrinsics are derived from this class. 718class AMDGPUImageDimIntrinsic<AMDGPUDimProfile P_, 719 list<IntrinsicProperty> props, 720 list<SDNodeProperty> sdnodeprops> : Intrinsic< 721 P_.RetTypes, // vdata(VGPR) -- for load/atomic-with-return 722 !listconcat( 723 !foreach(arg, P_.DataArgs, arg.Type), // vdata(VGPR) -- for store/atomic 724 !if(P_.IsAtomic, [], [llvm_i32_ty]), // dmask(imm) 725 P_.AddrTypes, // vaddr(VGPR) 726 [llvm_v8i32_ty], // rsrc(SGPR) 727 !if(P_.IsSample, [llvm_v4i32_ty, // samp(SGPR) 728 llvm_i1_ty], []), // unorm(imm) 729 [llvm_i32_ty, // texfailctrl(imm; bit 0 = tfe, bit 1 = lwe) 730 llvm_i32_ty]), // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc) 731 732 !listconcat(props, 733 !if(P_.IsAtomic, [], [ImmArg<ArgIndex<AMDGPUImageDimIntrinsicEval<P_>.DmaskArgIndex>>]), 734 !if(P_.IsSample, [ImmArg<ArgIndex<AMDGPUImageDimIntrinsicEval<P_>.UnormArgIndex>>], []), 735 [IntrWillReturn], 736 [ImmArg<ArgIndex<AMDGPUImageDimIntrinsicEval<P_>.TexFailCtrlArgIndex>>, 737 ImmArg<ArgIndex<AMDGPUImageDimIntrinsicEval<P_>.CachePolicyArgIndex>>]), 738 739 740 "", sdnodeprops>, 741 AMDGPURsrcIntrinsic<!add(!size(P_.DataArgs), !size(P_.AddrTypes), 742 !if(P_.IsAtomic, 0, 1)), 1> { 743 AMDGPUDimProfile P = P_; 744 745 AMDGPUImageDimIntrinsic Intr = !cast<AMDGPUImageDimIntrinsic>(NAME); 746 747 let TargetPrefix = "amdgcn"; 748} 749 750// Marker class for intrinsics with a DMask that determines the returned 751// channels. 752class AMDGPUImageDMaskIntrinsic; 753 754defset list<AMDGPUImageDimIntrinsic> AMDGPUImageDimIntrinsics = { 755 756 ////////////////////////////////////////////////////////////////////////// 757 // Load and store intrinsics 758 ////////////////////////////////////////////////////////////////////////// 759 multiclass AMDGPUImageDimIntrinsicsNoMsaa<string opmod, 760 list<LLVMType> retty, 761 list<AMDGPUArg> dataargs, 762 list<IntrinsicProperty> props, 763 list<SDNodeProperty> sdnodeprops, 764 bit Mip = false> { 765 foreach dim = AMDGPUDims.NoMsaa in { 766 def !strconcat(NAME, "_", dim.Name) 767 : AMDGPUImageDimIntrinsic< 768 AMDGPUDimNoSampleProfile<opmod, dim, retty, dataargs, Mip>, 769 props, sdnodeprops>; 770 } 771 } 772 773 multiclass AMDGPUImageDimIntrinsicsAll<string opmod, 774 list<LLVMType> retty, 775 list<AMDGPUArg> dataargs, 776 list<IntrinsicProperty> props, 777 list<SDNodeProperty> sdnodeprops, 778 bit Mip = false> { 779 foreach dim = AMDGPUDims.All in { 780 def !strconcat(NAME, "_", dim.Name) 781 : AMDGPUImageDimIntrinsic< 782 AMDGPUDimNoSampleProfile<opmod, dim, retty, dataargs, Mip>, 783 props, sdnodeprops>; 784 } 785 } 786 787 defm int_amdgcn_image_load 788 : AMDGPUImageDimIntrinsicsAll<"LOAD", [llvm_any_ty], [], [IntrReadMem], 789 [SDNPMemOperand]>, 790 AMDGPUImageDMaskIntrinsic; 791 defm int_amdgcn_image_load_mip 792 : AMDGPUImageDimIntrinsicsNoMsaa<"LOAD_MIP", [llvm_any_ty], [], 793 [IntrReadMem, IntrWillReturn], [SDNPMemOperand], 1>, 794 AMDGPUImageDMaskIntrinsic; 795 796 defm int_amdgcn_image_store : AMDGPUImageDimIntrinsicsAll< 797 "STORE", [], [AMDGPUArg<llvm_anyfloat_ty, "vdata">], 798 [IntrWriteMem, IntrWillReturn], [SDNPMemOperand]>; 799 defm int_amdgcn_image_store_mip : AMDGPUImageDimIntrinsicsNoMsaa< 800 "STORE_MIP", [], [AMDGPUArg<llvm_anyfloat_ty, "vdata">], 801 [IntrWriteMem, IntrWillReturn], [SDNPMemOperand], 1>; 802 803 ////////////////////////////////////////////////////////////////////////// 804 // MSAA intrinsics 805 ////////////////////////////////////////////////////////////////////////// 806 foreach dim = AMDGPUDims.Msaa in { 807 def int_amdgcn_image_msaa_load_x # _ # dim.Name: 808 AMDGPUImageDimIntrinsic< 809 AMDGPUDimNoSampleProfile<"MSAA_LOAD_X", dim, [llvm_any_ty], []>, 810 [IntrReadMem], [SDNPMemOperand]>; 811 } 812 813 ////////////////////////////////////////////////////////////////////////// 814 // sample and getlod intrinsics 815 ////////////////////////////////////////////////////////////////////////// 816 multiclass AMDGPUImageDimSampleDims<string opmod, 817 AMDGPUSampleVariant sample, 818 bit NoMem = false> { 819 foreach dim = AMDGPUDims.NoMsaa in { 820 def !strconcat(NAME, "_", dim.Name) : AMDGPUImageDimIntrinsic< 821 AMDGPUDimSampleProfile<opmod, dim, sample>, 822 !if(NoMem, [IntrNoMem], [IntrReadMem]), 823 !if(NoMem, [], [SDNPMemOperand])>; 824 } 825 } 826 827 foreach sample = AMDGPUSampleVariants in { 828 defm int_amdgcn_image_sample # sample.LowerCaseMod 829 : AMDGPUImageDimSampleDims<"SAMPLE" # sample.UpperCaseMod, sample>, 830 AMDGPUImageDMaskIntrinsic; 831 } 832 833 defm int_amdgcn_image_getlod 834 : AMDGPUImageDimSampleDims<"GET_LOD", AMDGPUSample, 1>, 835 AMDGPUImageDMaskIntrinsic; 836 837 ////////////////////////////////////////////////////////////////////////// 838 // getresinfo intrinsics 839 ////////////////////////////////////////////////////////////////////////// 840 foreach dim = AMDGPUDims.All in { 841 def !strconcat("int_amdgcn_image_getresinfo_", dim.Name) 842 : AMDGPUImageDimIntrinsic<AMDGPUDimGetResInfoProfile<dim>, [IntrNoMem], []>, 843 AMDGPUImageDMaskIntrinsic; 844 } 845 846 ////////////////////////////////////////////////////////////////////////// 847 // gather4 intrinsics 848 ////////////////////////////////////////////////////////////////////////// 849 foreach sample = AMDGPUSampleVariantsNoGradients in { 850 foreach dim = [AMDGPUDim2D, AMDGPUDimCube, AMDGPUDim2DArray] in { 851 def int_amdgcn_image_gather4 # sample.LowerCaseMod # _ # dim.Name: 852 AMDGPUImageDimIntrinsic< 853 AMDGPUDimSampleProfile<"GATHER4" # sample.UpperCaseMod, dim, sample>, 854 [IntrReadMem], [SDNPMemOperand]>; 855 } 856 } 857} 858 859////////////////////////////////////////////////////////////////////////// 860// atomic intrinsics 861////////////////////////////////////////////////////////////////////////// 862defset list<AMDGPUImageDimIntrinsic> AMDGPUImageDimAtomicIntrinsics = { 863 multiclass AMDGPUImageDimAtomicX<string opmod, list<AMDGPUArg> dataargs> { 864 foreach dim = AMDGPUDims.All in { 865 def !strconcat(NAME, "_", dim.Name) 866 : AMDGPUImageDimIntrinsic< 867 AMDGPUDimAtomicProfile<opmod, dim, dataargs>, 868 [], [SDNPMemOperand]>; 869 } 870 } 871 872 multiclass AMDGPUImageDimAtomic<string opmod> { 873 defm "" : AMDGPUImageDimAtomicX<opmod, [AMDGPUArg<LLVMMatchType<0>, "vdata">]>; 874 } 875 876 defm int_amdgcn_image_atomic_swap : AMDGPUImageDimAtomic<"ATOMIC_SWAP">; 877 defm int_amdgcn_image_atomic_add : AMDGPUImageDimAtomic<"ATOMIC_ADD">; 878 defm int_amdgcn_image_atomic_sub : AMDGPUImageDimAtomic<"ATOMIC_SUB">; 879 defm int_amdgcn_image_atomic_smin : AMDGPUImageDimAtomic<"ATOMIC_SMIN">; 880 defm int_amdgcn_image_atomic_umin : AMDGPUImageDimAtomic<"ATOMIC_UMIN">; 881 defm int_amdgcn_image_atomic_smax : AMDGPUImageDimAtomic<"ATOMIC_SMAX">; 882 defm int_amdgcn_image_atomic_umax : AMDGPUImageDimAtomic<"ATOMIC_UMAX">; 883 defm int_amdgcn_image_atomic_and : AMDGPUImageDimAtomic<"ATOMIC_AND">; 884 defm int_amdgcn_image_atomic_or : AMDGPUImageDimAtomic<"ATOMIC_OR">; 885 defm int_amdgcn_image_atomic_xor : AMDGPUImageDimAtomic<"ATOMIC_XOR">; 886 defm int_amdgcn_image_atomic_inc : AMDGPUImageDimAtomic<"ATOMIC_INC">; 887 defm int_amdgcn_image_atomic_dec : AMDGPUImageDimAtomic<"ATOMIC_DEC">; 888 889 defm int_amdgcn_image_atomic_cmpswap : 890 AMDGPUImageDimAtomicX<"ATOMIC_CMPSWAP", [AMDGPUArg<LLVMMatchType<0>, "src">, 891 AMDGPUArg<LLVMMatchType<0>, "cmp">]>; 892} 893 894////////////////////////////////////////////////////////////////////////// 895// Buffer intrinsics 896////////////////////////////////////////////////////////////////////////// 897 898let TargetPrefix = "amdgcn" in { 899 900defset list<AMDGPURsrcIntrinsic> AMDGPUBufferIntrinsics = { 901 902class AMDGPUBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic < 903 [data_ty], 904 [llvm_v4i32_ty, // rsrc(SGPR) 905 llvm_i32_ty, // vindex(VGPR) 906 llvm_i32_ty, // offset(SGPR/VGPR/imm) 907 llvm_i1_ty, // glc(imm) 908 llvm_i1_ty], // slc(imm) 909 [IntrReadMem, IntrWillReturn, 910 ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>, 911 AMDGPURsrcIntrinsic<0>; 912def int_amdgcn_buffer_load_format : AMDGPUBufferLoad<llvm_anyfloat_ty>; 913def int_amdgcn_buffer_load : AMDGPUBufferLoad; 914 915def int_amdgcn_s_buffer_load : Intrinsic < 916 [llvm_any_ty], 917 [llvm_v4i32_ty, // rsrc(SGPR) 918 llvm_i32_ty, // byte offset(SGPR/imm) 919 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 2 = dlc) 920 [IntrNoMem, IntrWillReturn, ImmArg<ArgIndex<2>>]>, 921 AMDGPURsrcIntrinsic<0>; 922 923class AMDGPUBufferStore<LLVMType data_ty = llvm_any_ty> : Intrinsic < 924 [], 925 [data_ty, // vdata(VGPR) 926 llvm_v4i32_ty, // rsrc(SGPR) 927 llvm_i32_ty, // vindex(VGPR) 928 llvm_i32_ty, // offset(SGPR/VGPR/imm) 929 llvm_i1_ty, // glc(imm) 930 llvm_i1_ty], // slc(imm) 931 [IntrWriteMem, IntrWillReturn, 932 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>, 933 AMDGPURsrcIntrinsic<1>; 934def int_amdgcn_buffer_store_format : AMDGPUBufferStore<llvm_anyfloat_ty>; 935def int_amdgcn_buffer_store : AMDGPUBufferStore; 936 937// New buffer intrinsics with separate raw and struct variants. The raw 938// variant never has an index. The struct variant always has an index, even if 939// it is const 0. A struct intrinsic with constant 0 index is different to the 940// corresponding raw intrinsic on gfx9+ because the behavior of bound checking 941// and swizzling changes depending on whether idxen is set in the instruction. 942// These new instrinsics also keep the offset and soffset arguments separate as 943// they behave differently in bounds checking and swizzling. 944class AMDGPURawBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic < 945 [data_ty], 946 [llvm_v4i32_ty, // rsrc(SGPR) 947 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 948 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 949 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 950 // bit 1 = slc, 951 // bit 2 = dlc on gfx10+), 952 // swizzled buffer (bit 3 = swz)) 953 [IntrReadMem, IntrWillReturn, ImmArg<ArgIndex<3>>], "", [SDNPMemOperand]>, 954 AMDGPURsrcIntrinsic<0>; 955def int_amdgcn_raw_buffer_load_format : AMDGPURawBufferLoad<llvm_anyfloat_ty>; 956def int_amdgcn_raw_buffer_load : AMDGPURawBufferLoad; 957 958class AMDGPUStructBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic < 959 [data_ty], 960 [llvm_v4i32_ty, // rsrc(SGPR) 961 llvm_i32_ty, // vindex(VGPR) 962 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 963 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 964 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 965 // bit 1 = slc, 966 // bit 2 = dlc on gfx10+), 967 // swizzled buffer (bit 3 = swz)) 968 [IntrReadMem, IntrWillReturn, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>, 969 AMDGPURsrcIntrinsic<0>; 970def int_amdgcn_struct_buffer_load_format : AMDGPUStructBufferLoad; 971def int_amdgcn_struct_buffer_load : AMDGPUStructBufferLoad; 972 973class AMDGPURawBufferStore<LLVMType data_ty = llvm_any_ty> : Intrinsic < 974 [], 975 [data_ty, // vdata(VGPR) 976 llvm_v4i32_ty, // rsrc(SGPR) 977 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 978 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 979 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 980 // bit 1 = slc, 981 // bit 2 = dlc on gfx10+), 982 // swizzled buffer (bit 3 = swz)) 983 [IntrWriteMem, IntrWillReturn, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>, 984 AMDGPURsrcIntrinsic<1>; 985def int_amdgcn_raw_buffer_store_format : AMDGPURawBufferStore<llvm_anyfloat_ty>; 986def int_amdgcn_raw_buffer_store : AMDGPURawBufferStore; 987 988class AMDGPUStructBufferStore<LLVMType data_ty = llvm_any_ty> : Intrinsic < 989 [], 990 [data_ty, // vdata(VGPR) 991 llvm_v4i32_ty, // rsrc(SGPR) 992 llvm_i32_ty, // vindex(VGPR) 993 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 994 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 995 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 996 // bit 1 = slc, 997 // bit 2 = dlc on gfx10+), 998 // swizzled buffer (bit 3 = swz)) 999 [IntrWriteMem, IntrWillReturn, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>, 1000 AMDGPURsrcIntrinsic<1>; 1001def int_amdgcn_struct_buffer_store_format : AMDGPUStructBufferStore; 1002def int_amdgcn_struct_buffer_store : AMDGPUStructBufferStore; 1003 1004class AMDGPURawBufferAtomic<LLVMType data_ty = llvm_any_ty, bit NoRtn = false> : Intrinsic < 1005 !if(NoRtn, [], [data_ty]), 1006 [!if(NoRtn, data_ty, LLVMMatchType<0>), // vdata(VGPR) 1007 llvm_v4i32_ty, // rsrc(SGPR) 1008 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1009 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1010 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) 1011 [ImmArg<ArgIndex<4>>, IntrWillReturn], "", [SDNPMemOperand]>, 1012 AMDGPURsrcIntrinsic<1, 0>; 1013def int_amdgcn_raw_buffer_atomic_swap : AMDGPURawBufferAtomic; 1014def int_amdgcn_raw_buffer_atomic_add : AMDGPURawBufferAtomic; 1015def int_amdgcn_raw_buffer_atomic_sub : AMDGPURawBufferAtomic; 1016def int_amdgcn_raw_buffer_atomic_smin : AMDGPURawBufferAtomic; 1017def int_amdgcn_raw_buffer_atomic_umin : AMDGPURawBufferAtomic; 1018def int_amdgcn_raw_buffer_atomic_smax : AMDGPURawBufferAtomic; 1019def int_amdgcn_raw_buffer_atomic_umax : AMDGPURawBufferAtomic; 1020def int_amdgcn_raw_buffer_atomic_and : AMDGPURawBufferAtomic; 1021def int_amdgcn_raw_buffer_atomic_or : AMDGPURawBufferAtomic; 1022def int_amdgcn_raw_buffer_atomic_xor : AMDGPURawBufferAtomic; 1023def int_amdgcn_raw_buffer_atomic_inc : AMDGPURawBufferAtomic; 1024def int_amdgcn_raw_buffer_atomic_dec : AMDGPURawBufferAtomic; 1025def int_amdgcn_raw_buffer_atomic_cmpswap : Intrinsic< 1026 [llvm_anyint_ty], 1027 [LLVMMatchType<0>, // src(VGPR) 1028 LLVMMatchType<0>, // cmp(VGPR) 1029 llvm_v4i32_ty, // rsrc(SGPR) 1030 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1031 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1032 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) 1033 [ImmArg<ArgIndex<5>>, IntrWillReturn], "", [SDNPMemOperand]>, 1034 AMDGPURsrcIntrinsic<2, 0>; 1035 1036// gfx908 intrinsic 1037def int_amdgcn_raw_buffer_atomic_fadd : AMDGPURawBufferAtomic<llvm_anyfloat_ty>; 1038 1039// gfx90a intrinsics 1040def int_amdgcn_raw_buffer_atomic_fmin : AMDGPURawBufferAtomic<llvm_anyfloat_ty>; 1041def int_amdgcn_raw_buffer_atomic_fmax : AMDGPURawBufferAtomic<llvm_anyfloat_ty>; 1042 1043class AMDGPUStructBufferAtomic<LLVMType data_ty = llvm_any_ty, bit NoRtn = false> : Intrinsic < 1044 !if(NoRtn, [], [data_ty]), 1045 [!if(NoRtn, data_ty, LLVMMatchType<0>), // vdata(VGPR) 1046 llvm_v4i32_ty, // rsrc(SGPR) 1047 llvm_i32_ty, // vindex(VGPR) 1048 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1049 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1050 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) 1051 [ImmArg<ArgIndex<5>>, IntrWillReturn], "", [SDNPMemOperand]>, 1052 AMDGPURsrcIntrinsic<1, 0>; 1053def int_amdgcn_struct_buffer_atomic_swap : AMDGPUStructBufferAtomic; 1054def int_amdgcn_struct_buffer_atomic_add : AMDGPUStructBufferAtomic; 1055def int_amdgcn_struct_buffer_atomic_sub : AMDGPUStructBufferAtomic; 1056def int_amdgcn_struct_buffer_atomic_smin : AMDGPUStructBufferAtomic; 1057def int_amdgcn_struct_buffer_atomic_umin : AMDGPUStructBufferAtomic; 1058def int_amdgcn_struct_buffer_atomic_smax : AMDGPUStructBufferAtomic; 1059def int_amdgcn_struct_buffer_atomic_umax : AMDGPUStructBufferAtomic; 1060def int_amdgcn_struct_buffer_atomic_and : AMDGPUStructBufferAtomic; 1061def int_amdgcn_struct_buffer_atomic_or : AMDGPUStructBufferAtomic; 1062def int_amdgcn_struct_buffer_atomic_xor : AMDGPUStructBufferAtomic; 1063def int_amdgcn_struct_buffer_atomic_inc : AMDGPUStructBufferAtomic; 1064def int_amdgcn_struct_buffer_atomic_dec : AMDGPUStructBufferAtomic; 1065def int_amdgcn_struct_buffer_atomic_cmpswap : Intrinsic< 1066 [llvm_anyint_ty], 1067 [LLVMMatchType<0>, // src(VGPR) 1068 LLVMMatchType<0>, // cmp(VGPR) 1069 llvm_v4i32_ty, // rsrc(SGPR) 1070 llvm_i32_ty, // vindex(VGPR) 1071 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1072 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1073 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) 1074 [ImmArg<ArgIndex<6>>, IntrWillReturn], "", [SDNPMemOperand]>, 1075 AMDGPURsrcIntrinsic<2, 0>; 1076 1077// gfx908 intrinsic 1078def int_amdgcn_struct_buffer_atomic_fadd : AMDGPUStructBufferAtomic<llvm_anyfloat_ty>; 1079 1080// gfx90a intrinsics 1081def int_amdgcn_struct_buffer_atomic_fmin : AMDGPUStructBufferAtomic<llvm_anyfloat_ty>; 1082def int_amdgcn_struct_buffer_atomic_fmax : AMDGPUStructBufferAtomic<llvm_anyfloat_ty>; 1083 1084 1085// Obsolescent tbuffer intrinsics. 1086def int_amdgcn_tbuffer_load : Intrinsic < 1087 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1088 [llvm_v4i32_ty, // rsrc(SGPR) 1089 llvm_i32_ty, // vindex(VGPR) 1090 llvm_i32_ty, // voffset(VGPR) 1091 llvm_i32_ty, // soffset(SGPR) 1092 llvm_i32_ty, // offset(imm) 1093 llvm_i32_ty, // dfmt(imm) 1094 llvm_i32_ty, // nfmt(imm) 1095 llvm_i1_ty, // glc(imm) 1096 llvm_i1_ty], // slc(imm) 1097 [IntrReadMem, IntrWillReturn, 1098 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>, 1099 ImmArg<ArgIndex<7>>, ImmArg<ArgIndex<8>>], "", [SDNPMemOperand]>, 1100 AMDGPURsrcIntrinsic<0>; 1101 1102def int_amdgcn_tbuffer_store : Intrinsic < 1103 [], 1104 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1105 llvm_v4i32_ty, // rsrc(SGPR) 1106 llvm_i32_ty, // vindex(VGPR) 1107 llvm_i32_ty, // voffset(VGPR) 1108 llvm_i32_ty, // soffset(SGPR) 1109 llvm_i32_ty, // offset(imm) 1110 llvm_i32_ty, // dfmt(imm) 1111 llvm_i32_ty, // nfmt(imm) 1112 llvm_i1_ty, // glc(imm) 1113 llvm_i1_ty], // slc(imm) 1114 [IntrWriteMem, IntrWillReturn, ImmArg<ArgIndex<5>>, 1115 ImmArg<ArgIndex<6>>, ImmArg<ArgIndex<7>>, 1116 ImmArg<ArgIndex<8>>, ImmArg<ArgIndex<9>>], "", [SDNPMemOperand]>, 1117 AMDGPURsrcIntrinsic<1>; 1118 1119// New tbuffer intrinsics, with: 1120// - raw and struct variants 1121// - joint format field 1122// - joint cachepolicy field 1123def int_amdgcn_raw_tbuffer_load : Intrinsic < 1124 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1125 [llvm_v4i32_ty, // rsrc(SGPR) 1126 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1127 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1128 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) 1129 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 1130 // bit 1 = slc, 1131 // bit 2 = dlc on gfx10+), 1132 // swizzled buffer (bit 3 = swz)) 1133 [IntrReadMem, IntrWillReturn, 1134 ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>, 1135 AMDGPURsrcIntrinsic<0>; 1136 1137def int_amdgcn_raw_tbuffer_store : Intrinsic < 1138 [], 1139 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1140 llvm_v4i32_ty, // rsrc(SGPR) 1141 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1142 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1143 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) 1144 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 1145 // bit 1 = slc, 1146 // bit 2 = dlc on gfx10+), 1147 // swizzled buffer (bit 3 = swz)) 1148 [IntrWriteMem, IntrWillReturn, 1149 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>, 1150 AMDGPURsrcIntrinsic<1>; 1151 1152def int_amdgcn_struct_tbuffer_load : Intrinsic < 1153 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1154 [llvm_v4i32_ty, // rsrc(SGPR) 1155 llvm_i32_ty, // vindex(VGPR) 1156 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1157 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1158 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) 1159 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 1160 // bit 1 = slc, 1161 // bit 2 = dlc on gfx10+), 1162 // swizzled buffer (bit 3 = swz)) 1163 [IntrReadMem, IntrWillReturn, 1164 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>, 1165 AMDGPURsrcIntrinsic<0>; 1166 1167def int_amdgcn_struct_tbuffer_store : Intrinsic < 1168 [], 1169 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1170 llvm_v4i32_ty, // rsrc(SGPR) 1171 llvm_i32_ty, // vindex(VGPR) 1172 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1173 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1174 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) 1175 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 1176 // bit 1 = slc, 1177 // bit 2 = dlc on gfx10+), 1178 // swizzled buffer (bit 3 = swz)) 1179 [IntrWriteMem, IntrWillReturn, 1180 ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>], "", [SDNPMemOperand]>, 1181 AMDGPURsrcIntrinsic<1>; 1182 1183class AMDGPUBufferAtomic : Intrinsic < 1184 [llvm_anyint_ty], 1185 [LLVMMatchType<0>, // vdata(VGPR) 1186 llvm_v4i32_ty, // rsrc(SGPR) 1187 llvm_i32_ty, // vindex(VGPR) 1188 llvm_i32_ty, // offset(SGPR/VGPR/imm) 1189 llvm_i1_ty], // slc(imm) 1190 [ImmArg<ArgIndex<4>>, IntrWillReturn], "", [SDNPMemOperand]>, 1191 AMDGPURsrcIntrinsic<1, 0>; 1192def int_amdgcn_buffer_atomic_swap : AMDGPUBufferAtomic; 1193def int_amdgcn_buffer_atomic_add : AMDGPUBufferAtomic; 1194def int_amdgcn_buffer_atomic_sub : AMDGPUBufferAtomic; 1195def int_amdgcn_buffer_atomic_smin : AMDGPUBufferAtomic; 1196def int_amdgcn_buffer_atomic_umin : AMDGPUBufferAtomic; 1197def int_amdgcn_buffer_atomic_smax : AMDGPUBufferAtomic; 1198def int_amdgcn_buffer_atomic_umax : AMDGPUBufferAtomic; 1199def int_amdgcn_buffer_atomic_and : AMDGPUBufferAtomic; 1200def int_amdgcn_buffer_atomic_or : AMDGPUBufferAtomic; 1201def int_amdgcn_buffer_atomic_xor : AMDGPUBufferAtomic; 1202def int_amdgcn_buffer_atomic_cmpswap : Intrinsic< 1203 [llvm_i32_ty], 1204 [llvm_i32_ty, // src(VGPR) 1205 llvm_i32_ty, // cmp(VGPR) 1206 llvm_v4i32_ty, // rsrc(SGPR) 1207 llvm_i32_ty, // vindex(VGPR) 1208 llvm_i32_ty, // offset(SGPR/VGPR/imm) 1209 llvm_i1_ty], // slc(imm) 1210 [ImmArg<ArgIndex<5>>, IntrWillReturn], "", [SDNPMemOperand]>, 1211 AMDGPURsrcIntrinsic<2, 0>; 1212 1213def int_amdgcn_buffer_atomic_csub : AMDGPUBufferAtomic; 1214 1215class AMDGPUBufferAtomicFP : Intrinsic < 1216 [llvm_anyfloat_ty], 1217 [LLVMMatchType<0>, // vdata(VGPR) 1218 llvm_v4i32_ty, // rsrc(SGPR) 1219 llvm_i32_ty, // vindex(VGPR) 1220 llvm_i32_ty, // offset(SGPR/VGPR/imm) 1221 llvm_i1_ty], // slc(imm) 1222 [ImmArg<ArgIndex<4>>, IntrWillReturn], "", [SDNPMemOperand]>, 1223 AMDGPURsrcIntrinsic<1, 0>; 1224 1225// Legacy form of the intrinsic. raw and struct forms should be preferred. 1226def int_amdgcn_buffer_atomic_fadd : AMDGPUBufferAtomicFP; 1227} // defset AMDGPUBufferIntrinsics 1228 1229// Uses that do not set the done bit should set IntrWriteMem on the 1230// call site. 1231def int_amdgcn_exp : Intrinsic <[], [ 1232 llvm_i32_ty, // tgt, 1233 llvm_i32_ty, // en 1234 llvm_any_ty, // src0 (f32 or i32) 1235 LLVMMatchType<0>, // src1 1236 LLVMMatchType<0>, // src2 1237 LLVMMatchType<0>, // src3 1238 llvm_i1_ty, // done 1239 llvm_i1_ty // vm 1240 ], 1241 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<6>>, 1242 ImmArg<ArgIndex<7>>, IntrWriteMem, IntrInaccessibleMemOnly, 1243 IntrWillReturn] 1244>; 1245 1246// exp with compr bit set. 1247def int_amdgcn_exp_compr : Intrinsic <[], [ 1248 llvm_i32_ty, // tgt, 1249 llvm_i32_ty, // en 1250 llvm_anyvector_ty, // src0 (v2f16 or v2i16) 1251 LLVMMatchType<0>, // src1 1252 llvm_i1_ty, // done 1253 llvm_i1_ty], // vm 1254 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>, 1255 ImmArg<ArgIndex<5>>, IntrWriteMem, IntrInaccessibleMemOnly, 1256 IntrWillReturn] 1257>; 1258 1259def int_amdgcn_buffer_wbinvl1_sc : 1260 GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_sc">, 1261 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1262 1263def int_amdgcn_buffer_wbinvl1 : 1264 GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1">, 1265 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1266 1267def int_amdgcn_s_dcache_inv : 1268 GCCBuiltin<"__builtin_amdgcn_s_dcache_inv">, 1269 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1270 1271def int_amdgcn_s_memtime : 1272 GCCBuiltin<"__builtin_amdgcn_s_memtime">, 1273 Intrinsic<[llvm_i64_ty], [], [IntrWillReturn]>; 1274 1275def int_amdgcn_s_sleep : 1276 GCCBuiltin<"__builtin_amdgcn_s_sleep">, 1277 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, 1278 IntrHasSideEffects, IntrWillReturn]> { 1279} 1280 1281def int_amdgcn_s_incperflevel : 1282 GCCBuiltin<"__builtin_amdgcn_s_incperflevel">, 1283 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, 1284 IntrHasSideEffects, IntrWillReturn]> { 1285} 1286 1287def int_amdgcn_s_decperflevel : 1288 GCCBuiltin<"__builtin_amdgcn_s_decperflevel">, 1289 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, 1290 IntrHasSideEffects, IntrWillReturn]> { 1291} 1292 1293def int_amdgcn_s_sethalt : 1294 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, 1295 IntrHasSideEffects, IntrWillReturn]>; 1296 1297def int_amdgcn_s_getreg : 1298 GCCBuiltin<"__builtin_amdgcn_s_getreg">, 1299 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], 1300 [IntrInaccessibleMemOnly, IntrReadMem, IntrSpeculatable, 1301 IntrWillReturn, ImmArg<ArgIndex<0>>] 1302>; 1303 1304// Note this can be used to set FP environment properties that are 1305// unsafe to change in non-strictfp functions. The register properties 1306// available (and value required to access them) may differ per 1307// subtarget. llvm.amdgcn.s.setreg(hwmode, value) 1308def int_amdgcn_s_setreg : 1309 GCCBuiltin<"__builtin_amdgcn_s_setreg">, 1310 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], 1311 [IntrNoMem, IntrHasSideEffects, IntrWillReturn, ImmArg<ArgIndex<0>>] 1312>; 1313 1314// int_amdgcn_s_getpc is provided to allow a specific style of position 1315// independent code to determine the high part of its address when it is 1316// known (through convention) that the code and any data of interest does 1317// not cross a 4Gb address boundary. Use for any other purpose may not 1318// produce the desired results as optimizations may cause code movement, 1319// especially as we explicitly use IntrNoMem to allow optimizations. 1320def int_amdgcn_s_getpc : 1321 GCCBuiltin<"__builtin_amdgcn_s_getpc">, 1322 Intrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrSpeculatable, 1323 IntrWillReturn]>; 1324 1325// __builtin_amdgcn_interp_mov <param>, <attr_chan>, <attr>, <m0> 1326// param values: 0 = P10, 1 = P20, 2 = P0 1327def int_amdgcn_interp_mov : 1328 GCCBuiltin<"__builtin_amdgcn_interp_mov">, 1329 Intrinsic<[llvm_float_ty], 1330 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1331 [IntrNoMem, IntrSpeculatable, IntrWillReturn, 1332 ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 1333 1334// __builtin_amdgcn_interp_p1 <i>, <attr_chan>, <attr>, <m0> 1335// This intrinsic reads from lds, but the memory values are constant, 1336// so it behaves like IntrNoMem. 1337def int_amdgcn_interp_p1 : 1338 GCCBuiltin<"__builtin_amdgcn_interp_p1">, 1339 Intrinsic<[llvm_float_ty], 1340 [llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1341 [IntrNoMem, IntrSpeculatable, IntrWillReturn, 1342 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 1343 1344// __builtin_amdgcn_interp_p2 <p1>, <j>, <attr_chan>, <attr>, <m0> 1345def int_amdgcn_interp_p2 : 1346 GCCBuiltin<"__builtin_amdgcn_interp_p2">, 1347 Intrinsic<[llvm_float_ty], 1348 [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1349 [IntrNoMem, IntrSpeculatable, IntrWillReturn, 1350 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1351 // See int_amdgcn_v_interp_p1 for why this is IntrNoMem. 1352 1353// __builtin_amdgcn_interp_p1_f16 <i>, <attr_chan>, <attr>, <high>, <m0> 1354// high selects whether high or low 16-bits are loaded from LDS 1355def int_amdgcn_interp_p1_f16 : 1356 GCCBuiltin<"__builtin_amdgcn_interp_p1_f16">, 1357 Intrinsic<[llvm_float_ty], 1358 [llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i32_ty], 1359 [IntrNoMem, IntrSpeculatable, IntrWillReturn, 1360 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1361 1362// __builtin_amdgcn_interp_p2_f16 <p1>, <j>, <attr_chan>, <attr>, <high>, <m0> 1363// high selects whether high or low 16-bits are loaded from LDS 1364def int_amdgcn_interp_p2_f16 : 1365 GCCBuiltin<"__builtin_amdgcn_interp_p2_f16">, 1366 Intrinsic<[llvm_half_ty], 1367 [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i32_ty], 1368 [IntrNoMem, IntrSpeculatable, IntrWillReturn, 1369 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>; 1370 1371// Deprecated: use llvm.amdgcn.live.mask instead. 1372def int_amdgcn_ps_live : Intrinsic < 1373 [llvm_i1_ty], 1374 [], 1375 [IntrNoMem, IntrWillReturn]>; 1376 1377// Query currently live lanes. 1378// Returns true if lane is live (and not a helper lane). 1379def int_amdgcn_live_mask : Intrinsic <[llvm_i1_ty], 1380 [], [IntrReadMem, IntrInaccessibleMemOnly, IntrWillReturn] 1381>; 1382 1383def int_amdgcn_mbcnt_lo : 1384 GCCBuiltin<"__builtin_amdgcn_mbcnt_lo">, 1385 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1386 [IntrNoMem, IntrWillReturn]>; 1387 1388def int_amdgcn_mbcnt_hi : 1389 GCCBuiltin<"__builtin_amdgcn_mbcnt_hi">, 1390 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1391 [IntrNoMem, IntrWillReturn]>; 1392 1393// llvm.amdgcn.ds.swizzle src offset 1394def int_amdgcn_ds_swizzle : 1395 GCCBuiltin<"__builtin_amdgcn_ds_swizzle">, 1396 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1397 [IntrNoMem, IntrConvergent, IntrWillReturn, 1398 ImmArg<ArgIndex<1>>]>; 1399 1400def int_amdgcn_ubfe : Intrinsic<[llvm_anyint_ty], 1401 [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty], 1402 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1403>; 1404 1405def int_amdgcn_sbfe : Intrinsic<[llvm_anyint_ty], 1406 [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty], 1407 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1408>; 1409 1410def int_amdgcn_lerp : 1411 GCCBuiltin<"__builtin_amdgcn_lerp">, 1412 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1413 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1414>; 1415 1416def int_amdgcn_sad_u8 : 1417 GCCBuiltin<"__builtin_amdgcn_sad_u8">, 1418 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1419 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1420>; 1421 1422def int_amdgcn_msad_u8 : 1423 GCCBuiltin<"__builtin_amdgcn_msad_u8">, 1424 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1425 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1426>; 1427 1428def int_amdgcn_sad_hi_u8 : 1429 GCCBuiltin<"__builtin_amdgcn_sad_hi_u8">, 1430 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1431 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1432>; 1433 1434def int_amdgcn_sad_u16 : 1435 GCCBuiltin<"__builtin_amdgcn_sad_u16">, 1436 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1437 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1438>; 1439 1440def int_amdgcn_qsad_pk_u16_u8 : 1441 GCCBuiltin<"__builtin_amdgcn_qsad_pk_u16_u8">, 1442 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty], 1443 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1444>; 1445 1446def int_amdgcn_mqsad_pk_u16_u8 : 1447 GCCBuiltin<"__builtin_amdgcn_mqsad_pk_u16_u8">, 1448 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty], 1449 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1450>; 1451 1452def int_amdgcn_mqsad_u32_u8 : 1453 GCCBuiltin<"__builtin_amdgcn_mqsad_u32_u8">, 1454 Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty, llvm_i32_ty, llvm_v4i32_ty], 1455 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1456>; 1457 1458def int_amdgcn_cvt_pk_u8_f32 : 1459 GCCBuiltin<"__builtin_amdgcn_cvt_pk_u8_f32">, 1460 Intrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty, llvm_i32_ty], 1461 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1462>; 1463 1464def int_amdgcn_icmp : 1465 Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty, LLVMMatchType<1>, llvm_i32_ty], 1466 [IntrNoMem, IntrConvergent, IntrWillReturn, 1467 ImmArg<ArgIndex<2>>]>; 1468 1469def int_amdgcn_fcmp : 1470 Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>, llvm_i32_ty], 1471 [IntrNoMem, IntrConvergent, IntrWillReturn, 1472 ImmArg<ArgIndex<2>>]>; 1473 1474def int_amdgcn_ballot : 1475 Intrinsic<[llvm_anyint_ty], [llvm_i1_ty], 1476 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1477 1478def int_amdgcn_readfirstlane : 1479 GCCBuiltin<"__builtin_amdgcn_readfirstlane">, 1480 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], 1481 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1482 1483// The lane argument must be uniform across the currently active threads of the 1484// current wave. Otherwise, the result is undefined. 1485def int_amdgcn_readlane : 1486 GCCBuiltin<"__builtin_amdgcn_readlane">, 1487 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1488 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1489 1490// The value to write and lane select arguments must be uniform across the 1491// currently active threads of the current wave. Otherwise, the result is 1492// undefined. 1493def int_amdgcn_writelane : 1494 GCCBuiltin<"__builtin_amdgcn_writelane">, 1495 Intrinsic<[llvm_i32_ty], [ 1496 llvm_i32_ty, // uniform value to write: returned by the selected lane 1497 llvm_i32_ty, // uniform lane select 1498 llvm_i32_ty // returned by all lanes other than the selected one 1499 ], 1500 [IntrNoMem, IntrConvergent, IntrWillReturn] 1501>; 1502 1503// FIXME: Deprecated. This is equivalent to llvm.fshr 1504def int_amdgcn_alignbit : Intrinsic<[llvm_i32_ty], 1505 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1506 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1507>; 1508 1509def int_amdgcn_alignbyte : GCCBuiltin<"__builtin_amdgcn_alignbyte">, 1510 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1511 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1512>; 1513 1514def int_amdgcn_mul_i24 : Intrinsic<[llvm_i32_ty], 1515 [llvm_i32_ty, llvm_i32_ty], 1516 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1517>; 1518 1519def int_amdgcn_mul_u24 : Intrinsic<[llvm_i32_ty], 1520 [llvm_i32_ty, llvm_i32_ty], 1521 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1522>; 1523 1524// llvm.amdgcn.ds.gws.init(i32 bar_val, i32 resource_id) 1525// 1526// bar_val is the total number of waves that will wait on this 1527// barrier, minus 1. 1528def int_amdgcn_ds_gws_init : 1529 GCCBuiltin<"__builtin_amdgcn_ds_gws_init">, 1530 Intrinsic<[], 1531 [llvm_i32_ty, llvm_i32_ty], 1532 [IntrConvergent, IntrWriteMem, 1533 IntrInaccessibleMemOnly, IntrWillReturn], "", 1534 [SDNPMemOperand] 1535>; 1536 1537// llvm.amdgcn.ds.gws.barrier(i32 vsrc0, i32 resource_id) 1538// bar_val is the total number of waves that will wait on this 1539// barrier, minus 1. 1540def int_amdgcn_ds_gws_barrier : 1541 GCCBuiltin<"__builtin_amdgcn_ds_gws_barrier">, 1542 Intrinsic<[], 1543 [llvm_i32_ty, llvm_i32_ty], 1544 [IntrConvergent, IntrInaccessibleMemOnly, IntrWillReturn], "", 1545 [SDNPMemOperand] 1546>; 1547 1548// llvm.amdgcn.ds.gws.sema.v(i32 resource_id) 1549def int_amdgcn_ds_gws_sema_v : 1550 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_v">, 1551 Intrinsic<[], 1552 [llvm_i32_ty], 1553 [IntrConvergent, IntrInaccessibleMemOnly, IntrWillReturn], "", 1554 [SDNPMemOperand] 1555>; 1556 1557// llvm.amdgcn.ds.gws.sema.br(i32 vsrc, i32 resource_id) 1558def int_amdgcn_ds_gws_sema_br : 1559 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_br">, 1560 Intrinsic<[], 1561 [llvm_i32_ty, llvm_i32_ty], 1562 [IntrConvergent, IntrInaccessibleMemOnly, IntrWillReturn], "", 1563 [SDNPMemOperand] 1564>; 1565 1566// llvm.amdgcn.ds.gws.sema.p(i32 resource_id) 1567def int_amdgcn_ds_gws_sema_p : 1568 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_p">, 1569 Intrinsic<[], 1570 [llvm_i32_ty], 1571 [IntrConvergent, IntrInaccessibleMemOnly, IntrWillReturn], "", 1572 [SDNPMemOperand] 1573>; 1574 1575// llvm.amdgcn.ds.gws.sema.release.all(i32 resource_id) 1576def int_amdgcn_ds_gws_sema_release_all : 1577 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_release_all">, 1578 Intrinsic<[], 1579 [llvm_i32_ty], 1580 [IntrConvergent, IntrInaccessibleMemOnly, IntrWillReturn], "", 1581 [SDNPMemOperand] 1582>; 1583 1584 1585// Copies the source value to the destination value, with the guarantee that 1586// the source value is computed as if the entire program were executed in WQM. 1587def int_amdgcn_wqm : Intrinsic<[llvm_any_ty], 1588 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1589>; 1590 1591// Copies the source value to the destination value, such that the source 1592// is computed as if the entire program were executed in WQM if any other 1593// program code executes in WQM. 1594def int_amdgcn_softwqm : Intrinsic<[llvm_any_ty], 1595 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1596>; 1597 1598// Return true if at least one thread within the pixel quad passes true into 1599// the function. 1600def int_amdgcn_wqm_vote : Intrinsic<[llvm_i1_ty], 1601 [llvm_i1_ty], [IntrNoMem, IntrConvergent, IntrWillReturn] 1602>; 1603 1604// If false, set EXEC=0 for the current thread until the end of program. 1605// FIXME: Should this be IntrNoMem, IntrHasSideEffects, or IntrWillReturn? 1606def int_amdgcn_kill : Intrinsic<[], [llvm_i1_ty], []>; 1607 1608def int_amdgcn_endpgm : GCCBuiltin<"__builtin_amdgcn_endpgm">, 1609 Intrinsic<[], [], [IntrNoReturn, IntrCold, IntrNoMem, IntrHasSideEffects] 1610>; 1611 1612// If false, mark all active lanes as helper lanes until the end of program. 1613def int_amdgcn_wqm_demote : Intrinsic<[], 1614 [llvm_i1_ty], [IntrWriteMem, IntrInaccessibleMemOnly] 1615>; 1616 1617// Copies the active channels of the source value to the destination value, 1618// with the guarantee that the source value is computed as if the entire 1619// program were executed in Whole Wavefront Mode, i.e. with all channels 1620// enabled, with a few exceptions: - Phi nodes which require WWM return an 1621// undefined value. 1622def int_amdgcn_strict_wwm : Intrinsic<[llvm_any_ty], 1623 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, 1624 IntrConvergent, IntrWillReturn] 1625>; 1626// Deprecated. Use int_amdgcn_strict_wwm instead. 1627def int_amdgcn_wwm : Intrinsic<[llvm_any_ty], 1628 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, 1629 IntrConvergent, IntrWillReturn] 1630>; 1631def int_amdgcn_strict_wqm : Intrinsic<[llvm_any_ty], 1632 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, 1633 IntrConvergent, IntrWillReturn] 1634>; 1635 1636// Given a value, copies it while setting all the inactive lanes to a given 1637// value. Note that OpenGL helper lanes are considered active, so if the 1638// program ever uses WQM, then the instruction and the first source will be 1639// computed in WQM. 1640def int_amdgcn_set_inactive : 1641 Intrinsic<[llvm_anyint_ty], 1642 [LLVMMatchType<0>, // value to be copied 1643 LLVMMatchType<0>], // value for the inactive lanes to take 1644 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1645 1646// Return if the given flat pointer points to a local memory address. 1647def int_amdgcn_is_shared : GCCBuiltin<"__builtin_amdgcn_is_shared">, 1648 Intrinsic<[llvm_i1_ty], [llvm_ptr_ty], 1649 [IntrNoMem, IntrSpeculatable, NoCapture<ArgIndex<0>>, IntrWillReturn] 1650>; 1651 1652// Return if the given flat pointer points to a prvate memory address. 1653def int_amdgcn_is_private : GCCBuiltin<"__builtin_amdgcn_is_private">, 1654 Intrinsic<[llvm_i1_ty], [llvm_ptr_ty], 1655 [IntrNoMem, IntrSpeculatable, NoCapture<ArgIndex<0>>, IntrWillReturn] 1656>; 1657 1658//===----------------------------------------------------------------------===// 1659// CI+ Intrinsics 1660//===----------------------------------------------------------------------===// 1661 1662def int_amdgcn_s_dcache_inv_vol : 1663 GCCBuiltin<"__builtin_amdgcn_s_dcache_inv_vol">, 1664 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1665 1666def int_amdgcn_buffer_wbinvl1_vol : 1667 GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_vol">, 1668 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1669 1670//===----------------------------------------------------------------------===// 1671// VI Intrinsics 1672//===----------------------------------------------------------------------===// 1673 1674// llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl> 1675def int_amdgcn_mov_dpp : 1676 Intrinsic<[llvm_anyint_ty], 1677 [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 1678 llvm_i1_ty], 1679 [IntrNoMem, IntrConvergent, IntrWillReturn, 1680 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, 1681 ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>; 1682 1683// llvm.amdgcn.update.dpp.i32 <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl> 1684// Should be equivalent to: 1685// v_mov_b32 <dest> <old> 1686// v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl> 1687def int_amdgcn_update_dpp : 1688 Intrinsic<[llvm_anyint_ty], 1689 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty, 1690 llvm_i32_ty, llvm_i32_ty, llvm_i1_ty], 1691 [IntrNoMem, IntrConvergent, IntrWillReturn, 1692 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, 1693 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>; 1694 1695def int_amdgcn_s_dcache_wb : 1696 GCCBuiltin<"__builtin_amdgcn_s_dcache_wb">, 1697 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1698 1699def int_amdgcn_s_dcache_wb_vol : 1700 GCCBuiltin<"__builtin_amdgcn_s_dcache_wb_vol">, 1701 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1702 1703def int_amdgcn_s_memrealtime : 1704 GCCBuiltin<"__builtin_amdgcn_s_memrealtime">, 1705 Intrinsic<[llvm_i64_ty], [], [IntrWillReturn]>; 1706 1707// llvm.amdgcn.ds.permute <index> <src> 1708def int_amdgcn_ds_permute : 1709 GCCBuiltin<"__builtin_amdgcn_ds_permute">, 1710 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1711 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1712 1713// llvm.amdgcn.ds.bpermute <index> <src> 1714def int_amdgcn_ds_bpermute : 1715 GCCBuiltin<"__builtin_amdgcn_ds_bpermute">, 1716 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1717 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1718 1719// llvm.amdgcn.perm <src0> <src1> <selector> 1720def int_amdgcn_perm : 1721 GCCBuiltin<"__builtin_amdgcn_perm">, 1722 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1723 [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 1724 1725//===----------------------------------------------------------------------===// 1726// GFX10 Intrinsics 1727//===----------------------------------------------------------------------===// 1728 1729// llvm.amdgcn.permlane16 <old> <src0> <src1> <src2> <fi> <bound_control> 1730def int_amdgcn_permlane16 : GCCBuiltin<"__builtin_amdgcn_permlane16">, 1731 Intrinsic<[llvm_i32_ty], 1732 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty], 1733 [IntrNoMem, IntrConvergent, IntrWillReturn, 1734 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>; 1735 1736// llvm.amdgcn.permlanex16 <old> <src0> <src1> <src2> <fi> <bound_control> 1737def int_amdgcn_permlanex16 : GCCBuiltin<"__builtin_amdgcn_permlanex16">, 1738 Intrinsic<[llvm_i32_ty], 1739 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty], 1740 [IntrNoMem, IntrConvergent, IntrWillReturn, 1741 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>; 1742 1743// llvm.amdgcn.mov.dpp8.i32 <src> <sel> 1744// <sel> is a 32-bit constant whose high 8 bits must be zero which selects 1745// the lanes to read from. 1746def int_amdgcn_mov_dpp8 : 1747 Intrinsic<[llvm_anyint_ty], 1748 [LLVMMatchType<0>, llvm_i32_ty], 1749 [IntrNoMem, IntrConvergent, IntrWillReturn, 1750 ImmArg<ArgIndex<1>>]>; 1751 1752def int_amdgcn_s_get_waveid_in_workgroup : 1753 GCCBuiltin<"__builtin_amdgcn_s_get_waveid_in_workgroup">, 1754 Intrinsic<[llvm_i32_ty], [], 1755 [IntrReadMem, IntrInaccessibleMemOnly, IntrWillReturn]>; 1756 1757class AMDGPUGlobalAtomicRtn<LLVMType vt> : Intrinsic < 1758 [vt], 1759 [llvm_anyptr_ty, // vaddr 1760 vt], // vdata(VGPR) 1761 [IntrArgMemOnly, IntrWillReturn, NoCapture<ArgIndex<0>>], "", 1762 [SDNPMemOperand]>; 1763 1764def int_amdgcn_global_atomic_csub : AMDGPUGlobalAtomicRtn<llvm_i32_ty>; 1765 1766// uint4 llvm.amdgcn.image.bvh.intersect.ray <node_ptr>, <ray_extent>, <ray_origin>, 1767// <ray_dir>, <ray_inv_dir>, <texture_descr> 1768def int_amdgcn_image_bvh_intersect_ray : 1769 Intrinsic<[llvm_v4i32_ty], 1770 [llvm_anyint_ty, llvm_float_ty, llvm_v4f32_ty, llvm_anyvector_ty, 1771 LLVMMatchType<1>, llvm_v4i32_ty], 1772 [IntrReadMem, IntrWillReturn]>; 1773 1774//===----------------------------------------------------------------------===// 1775// Deep learning intrinsics. 1776//===----------------------------------------------------------------------===// 1777 1778// f32 %r = llvm.amdgcn.fdot2(v2f16 %a, v2f16 %b, f32 %c, i1 %clamp) 1779// %r = %a[0] * %b[0] + %a[1] * %b[1] + %c 1780def int_amdgcn_fdot2 : 1781 GCCBuiltin<"__builtin_amdgcn_fdot2">, 1782 Intrinsic< 1783 [llvm_float_ty], // %r 1784 [ 1785 llvm_v2f16_ty, // %a 1786 llvm_v2f16_ty, // %b 1787 llvm_float_ty, // %c 1788 llvm_i1_ty // %clamp 1789 ], 1790 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1791 >; 1792 1793// i32 %r = llvm.amdgcn.sdot2(v2i16 %a, v2i16 %b, i32 %c, i1 %clamp) 1794// %r = %a[0] * %b[0] + %a[1] * %b[1] + %c 1795def int_amdgcn_sdot2 : 1796 GCCBuiltin<"__builtin_amdgcn_sdot2">, 1797 Intrinsic< 1798 [llvm_i32_ty], // %r 1799 [ 1800 llvm_v2i16_ty, // %a 1801 llvm_v2i16_ty, // %b 1802 llvm_i32_ty, // %c 1803 llvm_i1_ty // %clamp 1804 ], 1805 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1806 >; 1807 1808// u32 %r = llvm.amdgcn.udot2(v2u16 %a, v2u16 %b, u32 %c, i1 %clamp) 1809// %r = %a[0] * %b[0] + %a[1] * %b[1] + %c 1810def int_amdgcn_udot2 : 1811 GCCBuiltin<"__builtin_amdgcn_udot2">, 1812 Intrinsic< 1813 [llvm_i32_ty], // %r 1814 [ 1815 llvm_v2i16_ty, // %a 1816 llvm_v2i16_ty, // %b 1817 llvm_i32_ty, // %c 1818 llvm_i1_ty // %clamp 1819 ], 1820 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1821 >; 1822 1823// i32 %r = llvm.amdgcn.sdot4(v4i8 (as i32) %a, v4i8 (as i32) %b, i32 %c, i1 %clamp) 1824// %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + %c 1825def int_amdgcn_sdot4 : 1826 GCCBuiltin<"__builtin_amdgcn_sdot4">, 1827 Intrinsic< 1828 [llvm_i32_ty], // %r 1829 [ 1830 llvm_i32_ty, // %a 1831 llvm_i32_ty, // %b 1832 llvm_i32_ty, // %c 1833 llvm_i1_ty // %clamp 1834 ], 1835 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1836 >; 1837 1838// u32 %r = llvm.amdgcn.udot4(v4u8 (as u32) %a, v4u8 (as u32) %b, u32 %c, i1 %clamp) 1839// %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + %c 1840def int_amdgcn_udot4 : 1841 GCCBuiltin<"__builtin_amdgcn_udot4">, 1842 Intrinsic< 1843 [llvm_i32_ty], // %r 1844 [ 1845 llvm_i32_ty, // %a 1846 llvm_i32_ty, // %b 1847 llvm_i32_ty, // %c 1848 llvm_i1_ty // %clamp 1849 ], 1850 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1851 >; 1852 1853// i32 %r = llvm.amdgcn.sdot8(v8i4 (as i32) %a, v8i4 (as i32) %b, i32 %c, i1 %clamp) 1854// %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + 1855// %a[4] * %b[4] + %a[5] * %b[5] + %a[6] * %b[6] + %a[7] * %b[7] + %c 1856def int_amdgcn_sdot8 : 1857 GCCBuiltin<"__builtin_amdgcn_sdot8">, 1858 Intrinsic< 1859 [llvm_i32_ty], // %r 1860 [ 1861 llvm_i32_ty, // %a 1862 llvm_i32_ty, // %b 1863 llvm_i32_ty, // %c 1864 llvm_i1_ty // %clamp 1865 ], 1866 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1867 >; 1868 1869// u32 %r = llvm.amdgcn.udot8(v8u4 (as u32) %a, v8u4 (as u32) %b, u32 %c, i1 %clamp) 1870// %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + 1871// %a[4] * %b[4] + %a[5] * %b[5] + %a[6] * %b[6] + %a[7] * %b[7] + %c 1872def int_amdgcn_udot8 : 1873 GCCBuiltin<"__builtin_amdgcn_udot8">, 1874 Intrinsic< 1875 [llvm_i32_ty], // %r 1876 [ 1877 llvm_i32_ty, // %a 1878 llvm_i32_ty, // %b 1879 llvm_i32_ty, // %c 1880 llvm_i1_ty // %clamp 1881 ], 1882 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1883 >; 1884 1885//===----------------------------------------------------------------------===// 1886// gfx908 intrinsics 1887// ===----------------------------------------------------------------------===// 1888 1889def int_amdgcn_global_atomic_fadd : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1890 1891// llvm.amdgcn.mfma.*.* vdst, srcA, srcB, srcC, cbsz, abid, blgp 1892class AMDGPUMfmaIntrinsic<LLVMType DestTy, LLVMType SrcABTy> : 1893 GCCBuiltin<!subst("int", "__builtin", NAME)>, 1894 Intrinsic<[DestTy], 1895 [SrcABTy, SrcABTy, DestTy, 1896 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1897 [IntrConvergent, IntrNoMem, IntrWillReturn, 1898 ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>; 1899 1900def int_amdgcn_mfma_f32_32x32x1f32 : AMDGPUMfmaIntrinsic<llvm_v32f32_ty, llvm_float_ty>; 1901def int_amdgcn_mfma_f32_16x16x1f32 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_float_ty>; 1902def int_amdgcn_mfma_f32_4x4x1f32 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_float_ty>; 1903def int_amdgcn_mfma_f32_32x32x2f32 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_float_ty>; 1904def int_amdgcn_mfma_f32_16x16x4f32 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_float_ty>; 1905def int_amdgcn_mfma_f32_32x32x4f16 : AMDGPUMfmaIntrinsic<llvm_v32f32_ty, llvm_v4f16_ty>; 1906def int_amdgcn_mfma_f32_16x16x4f16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v4f16_ty>; 1907def int_amdgcn_mfma_f32_4x4x4f16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v4f16_ty>; 1908def int_amdgcn_mfma_f32_32x32x8f16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v4f16_ty>; 1909def int_amdgcn_mfma_f32_16x16x16f16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v4f16_ty>; 1910def int_amdgcn_mfma_i32_32x32x4i8 : AMDGPUMfmaIntrinsic<llvm_v32i32_ty, llvm_i32_ty>; 1911def int_amdgcn_mfma_i32_16x16x4i8 : AMDGPUMfmaIntrinsic<llvm_v16i32_ty, llvm_i32_ty>; 1912def int_amdgcn_mfma_i32_4x4x4i8 : AMDGPUMfmaIntrinsic<llvm_v4i32_ty, llvm_i32_ty>; 1913def int_amdgcn_mfma_i32_32x32x8i8 : AMDGPUMfmaIntrinsic<llvm_v16i32_ty, llvm_i32_ty>; 1914def int_amdgcn_mfma_i32_16x16x16i8 : AMDGPUMfmaIntrinsic<llvm_v4i32_ty, llvm_i32_ty>; 1915def int_amdgcn_mfma_f32_32x32x2bf16 : AMDGPUMfmaIntrinsic<llvm_v32f32_ty, llvm_v2i16_ty>; 1916def int_amdgcn_mfma_f32_16x16x2bf16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v2i16_ty>; 1917def int_amdgcn_mfma_f32_4x4x2bf16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v2i16_ty>; 1918def int_amdgcn_mfma_f32_32x32x4bf16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v2i16_ty>; 1919def int_amdgcn_mfma_f32_16x16x8bf16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v2i16_ty>; 1920 1921//===----------------------------------------------------------------------===// 1922// gfx90a intrinsics 1923// ===----------------------------------------------------------------------===// 1924 1925def int_amdgcn_global_atomic_fmin : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1926def int_amdgcn_global_atomic_fmax : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1927def int_amdgcn_flat_atomic_fadd : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1928def int_amdgcn_flat_atomic_fmin : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1929def int_amdgcn_flat_atomic_fmax : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1930 1931def int_amdgcn_mfma_f32_32x32x4bf16_1k : AMDGPUMfmaIntrinsic<llvm_v32f32_ty, llvm_v4i16_ty>; 1932def int_amdgcn_mfma_f32_16x16x4bf16_1k : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v4i16_ty>; 1933def int_amdgcn_mfma_f32_4x4x4bf16_1k : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v4i16_ty>; 1934def int_amdgcn_mfma_f32_32x32x8bf16_1k : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v4i16_ty>; 1935def int_amdgcn_mfma_f32_16x16x16bf16_1k : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v4i16_ty>; 1936 1937def int_amdgcn_mfma_f64_16x16x4f64 : AMDGPUMfmaIntrinsic<llvm_v4f64_ty, llvm_double_ty>; 1938def int_amdgcn_mfma_f64_4x4x4f64 : AMDGPUMfmaIntrinsic<llvm_double_ty, llvm_double_ty>; 1939 1940//===----------------------------------------------------------------------===// 1941// Special Intrinsics for backend internal use only. No frontend 1942// should emit calls to these. 1943// ===----------------------------------------------------------------------===// 1944def int_amdgcn_if : Intrinsic<[llvm_i1_ty, llvm_anyint_ty], 1945 [llvm_i1_ty], [IntrConvergent, IntrWillReturn] 1946>; 1947 1948def int_amdgcn_else : Intrinsic<[llvm_i1_ty, llvm_anyint_ty], 1949 [llvm_anyint_ty], [IntrConvergent, IntrWillReturn] 1950>; 1951 1952def int_amdgcn_if_break : Intrinsic<[llvm_anyint_ty], 1953 [llvm_i1_ty, LLVMMatchType<0>], 1954 [IntrNoMem, IntrConvergent, IntrWillReturn] 1955>; 1956 1957def int_amdgcn_loop : Intrinsic<[llvm_i1_ty], 1958 [llvm_anyint_ty], [IntrConvergent, IntrWillReturn] 1959>; 1960 1961def int_amdgcn_end_cf : Intrinsic<[], [llvm_anyint_ty], 1962 [IntrConvergent, IntrWillReturn]>; 1963 1964// Represent unreachable in a divergent region. 1965def int_amdgcn_unreachable : Intrinsic<[], [], [IntrConvergent]>; 1966 1967// Emit 2.5 ulp, no denormal division. Should only be inserted by 1968// pass based on !fpmath metadata. 1969def int_amdgcn_fdiv_fast : Intrinsic< 1970 [llvm_float_ty], [llvm_float_ty, llvm_float_ty], 1971 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1972>; 1973 1974// Represent a relocation constant. 1975def int_amdgcn_reloc_constant : Intrinsic< 1976 [llvm_i32_ty], [llvm_metadata_ty], 1977 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1978>; 1979} 1980