1//===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines all of the ARM-specific intrinsics. 10// 11//===----------------------------------------------------------------------===// 12 13 14//===----------------------------------------------------------------------===// 15// TLS 16 17let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". 18 19// A space-consuming intrinsic primarily for testing ARMConstantIslands. The 20// first argument is the number of bytes this "instruction" takes up, the second 21// and return value are essentially chains, used to force ordering during ISel. 22def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [ImmArg<0>]>; 23 24// 16-bit multiplications 25def int_arm_smulbb : GCCBuiltin<"__builtin_arm_smulbb">, 26 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 27def int_arm_smulbt : GCCBuiltin<"__builtin_arm_smulbt">, 28 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 29def int_arm_smultb : GCCBuiltin<"__builtin_arm_smultb">, 30 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 31def int_arm_smultt : GCCBuiltin<"__builtin_arm_smultt">, 32 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 33def int_arm_smulwb : GCCBuiltin<"__builtin_arm_smulwb">, 34 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 35def int_arm_smulwt : GCCBuiltin<"__builtin_arm_smulwt">, 36 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 37 38//===----------------------------------------------------------------------===// 39// Saturating Arithmetic 40 41def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">, 42 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 43 [Commutative, IntrNoMem]>; 44def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">, 45 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 46def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">, 47 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 48def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">, 49 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 50 51// Accumulating multiplications 52def int_arm_smlabb : GCCBuiltin<"__builtin_arm_smlabb">, 53 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 54 [IntrNoMem]>; 55def int_arm_smlabt : GCCBuiltin<"__builtin_arm_smlabt">, 56 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 57 [IntrNoMem]>; 58def int_arm_smlatb : GCCBuiltin<"__builtin_arm_smlatb">, 59 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 60 [IntrNoMem]>; 61def int_arm_smlatt : GCCBuiltin<"__builtin_arm_smlatt">, 62 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 63 [IntrNoMem]>; 64def int_arm_smlawb : GCCBuiltin<"__builtin_arm_smlawb">, 65 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 66 [IntrNoMem]>; 67def int_arm_smlawt : GCCBuiltin<"__builtin_arm_smlawt">, 68 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 69 [IntrNoMem]>; 70 71// Parallel 16-bit saturation 72def int_arm_ssat16 : GCCBuiltin<"__builtin_arm_ssat16">, 73 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 74def int_arm_usat16 : GCCBuiltin<"__builtin_arm_usat16">, 75 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 76 77// Packing and unpacking 78def int_arm_sxtab16 : GCCBuiltin<"__builtin_arm_sxtab16">, 79 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 80def int_arm_sxtb16 : GCCBuiltin<"__builtin_arm_sxtb16">, 81 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; 82def int_arm_uxtab16 : GCCBuiltin<"__builtin_arm_uxtab16">, 83 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 84def int_arm_uxtb16 : GCCBuiltin<"__builtin_arm_uxtb16">, 85 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; 86 87// Parallel selection, reads the GE flags. 88def int_arm_sel : GCCBuiltin<"__builtin_arm_sel">, 89 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadMem]>; 90 91// Parallel 8-bit addition and subtraction 92def int_arm_qadd8 : GCCBuiltin<"__builtin_arm_qadd8">, 93 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 94def int_arm_qsub8 : GCCBuiltin<"__builtin_arm_qsub8">, 95 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 96// Writes to the GE bits. 97def int_arm_sadd8 : GCCBuiltin<"__builtin_arm_sadd8">, 98 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 99def int_arm_shadd8 : GCCBuiltin<"__builtin_arm_shadd8">, 100 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 101def int_arm_shsub8 : GCCBuiltin<"__builtin_arm_shsub8">, 102 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 103// Writes to the GE bits. 104def int_arm_ssub8 : GCCBuiltin<"__builtin_arm_ssub8">, 105 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 106// Writes to the GE bits. 107def int_arm_uadd8 : GCCBuiltin<"__builtin_arm_uadd8">, 108 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 109def int_arm_uhadd8 : GCCBuiltin<"__builtin_arm_uhadd8">, 110 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 111def int_arm_uhsub8 : GCCBuiltin<"__builtin_arm_uhsub8">, 112 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 113def int_arm_uqadd8 : GCCBuiltin<"__builtin_arm_uqadd8">, 114 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 115def int_arm_uqsub8 : GCCBuiltin<"__builtin_arm_uqsub8">, 116 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 117// Writes to the GE bits. 118def int_arm_usub8 : GCCBuiltin<"__builtin_arm_usub8">, 119 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 120 121// Sum of 8-bit absolute differences 122def int_arm_usad8 : GCCBuiltin<"__builtin_arm_usad8">, 123 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 124def int_arm_usada8 : GCCBuiltin<"__builtin_arm_usada8">, 125 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 126 [IntrNoMem]>; 127 128// Parallel 16-bit addition and subtraction 129def int_arm_qadd16 : GCCBuiltin<"__builtin_arm_qadd16">, 130 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 131def int_arm_qasx : GCCBuiltin<"__builtin_arm_qasx">, 132 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 133def int_arm_qsax : GCCBuiltin<"__builtin_arm_qsax">, 134 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 135def int_arm_qsub16 : GCCBuiltin<"__builtin_arm_qsub16">, 136 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 137// Writes to the GE bits. 138def int_arm_sadd16 : GCCBuiltin<"__builtin_arm_sadd16">, 139 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 140// Writes to the GE bits. 141def int_arm_sasx : GCCBuiltin<"__builtin_arm_sasx">, 142 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 143def int_arm_shadd16 : GCCBuiltin<"__builtin_arm_shadd16">, 144 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 145def int_arm_shasx : GCCBuiltin<"__builtin_arm_shasx">, 146 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 147def int_arm_shsax : GCCBuiltin<"__builtin_arm_shsax">, 148 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 149def int_arm_shsub16 : GCCBuiltin<"__builtin_arm_shsub16">, 150 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 151// Writes to the GE bits. 152def int_arm_ssax : GCCBuiltin<"__builtin_arm_ssax">, 153 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 154// Writes to the GE bits. 155def int_arm_ssub16 : GCCBuiltin<"__builtin_arm_ssub16">, 156 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 157// Writes to the GE bits. 158def int_arm_uadd16 : GCCBuiltin<"__builtin_arm_uadd16">, 159 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 160// Writes to the GE bits. 161def int_arm_uasx : GCCBuiltin<"__builtin_arm_uasx">, 162 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 163def int_arm_uhadd16 : GCCBuiltin<"__builtin_arm_uhadd16">, 164 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 165def int_arm_uhasx : GCCBuiltin<"__builtin_arm_uhasx">, 166 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 167def int_arm_uhsax : GCCBuiltin<"__builtin_arm_uhsax">, 168 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 169def int_arm_uhsub16 : GCCBuiltin<"__builtin_arm_uhsub16">, 170 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 171def int_arm_uqadd16 : GCCBuiltin<"__builtin_arm_uqadd16">, 172 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 173def int_arm_uqasx : GCCBuiltin<"__builtin_arm_uqasx">, 174 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 175def int_arm_uqsax : GCCBuiltin<"__builtin_arm_uqsax">, 176 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 177def int_arm_uqsub16 : GCCBuiltin<"__builtin_arm_uqsub16">, 178 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 179// Writes to the GE bits. 180def int_arm_usax : GCCBuiltin<"__builtin_arm_usax">, 181 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 182// Writes to the GE bits. 183def int_arm_usub16 : GCCBuiltin<"__builtin_arm_usub16">, 184 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; 185 186// Parallel 16-bit multiplication 187def int_arm_smlad : GCCBuiltin<"__builtin_arm_smlad">, 188 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 189 [IntrNoMem]>; 190def int_arm_smladx : GCCBuiltin<"__builtin_arm_smladx">, 191 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 192 [IntrNoMem]>; 193def int_arm_smlald : GCCBuiltin<"__builtin_arm_smlald">, 194 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty], 195 [IntrNoMem]>; 196def int_arm_smlaldx : GCCBuiltin<"__builtin_arm_smlaldx">, 197 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty], 198 [IntrNoMem]>; 199def int_arm_smlsd : GCCBuiltin<"__builtin_arm_smlsd">, 200 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 201 [IntrNoMem]>; 202def int_arm_smlsdx : GCCBuiltin<"__builtin_arm_smlsdx">, 203 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 204 [IntrNoMem]>; 205def int_arm_smlsld : GCCBuiltin<"__builtin_arm_smlsld">, 206 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty], 207 [IntrNoMem]>; 208def int_arm_smlsldx : GCCBuiltin<"__builtin_arm_smlsldx">, 209 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty], 210 [IntrNoMem]>; 211def int_arm_smuad : GCCBuiltin<"__builtin_arm_smuad">, 212 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 213def int_arm_smuadx : GCCBuiltin<"__builtin_arm_smuadx">, 214 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 215def int_arm_smusd : GCCBuiltin<"__builtin_arm_smusd">, 216 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 217def int_arm_smusdx : GCCBuiltin<"__builtin_arm_smusdx">, 218 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 219 220 221//===----------------------------------------------------------------------===// 222// Load, Store and Clear exclusive 223 224def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>; 225def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>; 226 227def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>; 228def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>; 229 230def int_arm_clrex : Intrinsic<[]>; 231 232def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, 233 llvm_ptr_ty]>; 234def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>; 235 236def int_arm_stlexd : Intrinsic<[llvm_i32_ty], 237 [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>; 238def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>; 239 240//===----------------------------------------------------------------------===// 241// Data barrier instructions 242def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">, 243 Intrinsic<[], [llvm_i32_ty]>; 244def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">, 245 Intrinsic<[], [llvm_i32_ty]>; 246def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">, 247 Intrinsic<[], [llvm_i32_ty]>; 248 249//===----------------------------------------------------------------------===// 250// VFP 251 252def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">, 253 Intrinsic<[llvm_i32_ty], [], []>; 254def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">, 255 Intrinsic<[], [llvm_i32_ty], []>; 256def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], 257 [IntrNoMem]>; 258def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], 259 [IntrNoMem]>; 260 261//===----------------------------------------------------------------------===// 262// Coprocessor 263 264def int_arm_ldc : GCCBuiltin<"__builtin_arm_ldc">, 265 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>; 266def int_arm_ldcl : GCCBuiltin<"__builtin_arm_ldcl">, 267 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>; 268def int_arm_ldc2 : GCCBuiltin<"__builtin_arm_ldc2">, 269 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>; 270def int_arm_ldc2l : GCCBuiltin<"__builtin_arm_ldc2l">, 271 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>; 272 273def int_arm_stc : GCCBuiltin<"__builtin_arm_stc">, 274 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>; 275def int_arm_stcl : GCCBuiltin<"__builtin_arm_stcl">, 276 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>; 277def int_arm_stc2 : GCCBuiltin<"__builtin_arm_stc2">, 278 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>; 279def int_arm_stc2l : GCCBuiltin<"__builtin_arm_stc2l">, 280 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>; 281 282// Move to coprocessor 283def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">, 284 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 285 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<3>, ImmArg<4>, ImmArg<5>]>; 286def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">, 287 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 288 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<3>, ImmArg<4>, ImmArg<5>]>; 289 290// Move from coprocessor 291def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">, 292 MSBuiltin<"_MoveFromCoprocessor">, 293 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 294 llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>, ImmArg<3>, ImmArg<4>]>; 295def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">, 296 MSBuiltin<"_MoveFromCoprocessor2">, 297 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 298 llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>, ImmArg<3>, ImmArg<4>]>; 299 300// Coprocessor data processing 301def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">, 302 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 303 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>, ImmArg<3>, ImmArg<4>, ImmArg<5>]>; 304def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">, 305 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 306 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>, ImmArg<3>, ImmArg<4>, ImmArg<5>]>; 307 308// Move from two registers to coprocessor 309def int_arm_mcrr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 310 llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<4>]>; 311def int_arm_mcrr2 : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 312 llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<4>]>; 313 314def int_arm_mrrc : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty, 315 llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>]>; 316def int_arm_mrrc2 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty, 317 llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>]>; 318 319//===----------------------------------------------------------------------===// 320// CRC32 321 322def int_arm_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 323 [IntrNoMem]>; 324def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 325 [IntrNoMem]>; 326def int_arm_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 327 [IntrNoMem]>; 328def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 329 [IntrNoMem]>; 330def int_arm_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 331 [IntrNoMem]>; 332def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 333 [IntrNoMem]>; 334 335//===----------------------------------------------------------------------===// 336// CMSE 337 338def int_arm_cmse_tt : GCCBuiltin<"__builtin_arm_cmse_TT">, 339 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; 340def int_arm_cmse_ttt : GCCBuiltin<"__builtin_arm_cmse_TTT">, 341 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; 342def int_arm_cmse_tta : GCCBuiltin<"__builtin_arm_cmse_TTA">, 343 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; 344def int_arm_cmse_ttat : GCCBuiltin<"__builtin_arm_cmse_TTAT">, 345 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; 346 347//===----------------------------------------------------------------------===// 348// HINT 349 350def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>; 351def int_arm_dbg : Intrinsic<[], [llvm_i32_ty]>; 352 353//===----------------------------------------------------------------------===// 354// UND (reserved undefined sequence) 355 356def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>; 357 358//===----------------------------------------------------------------------===// 359// Advanced SIMD (NEON) 360 361// The following classes do not correspond directly to GCC builtins. 362class Neon_1Arg_Intrinsic 363 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; 364class Neon_1Arg_Narrow_Intrinsic 365 : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>; 366class Neon_2Arg_Intrinsic 367 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 368 [IntrNoMem]>; 369class Neon_2Arg_Narrow_Intrinsic 370 : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>], 371 [IntrNoMem]>; 372class Neon_2Arg_Long_Intrinsic 373 : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>], 374 [IntrNoMem]>; 375class Neon_3Arg_Intrinsic 376 : Intrinsic<[llvm_anyvector_ty], 377 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 378 [IntrNoMem]>; 379class Neon_3Arg_Long_Intrinsic 380 : Intrinsic<[llvm_anyvector_ty], 381 [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>], 382 [IntrNoMem]>; 383 384class Neon_1FloatArg_Intrinsic 385 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; 386 387class Neon_CvtFxToFP_Intrinsic 388 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; 389class Neon_CvtFPToFx_Intrinsic 390 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>; 391class Neon_CvtFPtoInt_1Arg_Intrinsic 392 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; 393 394class Neon_Compare_Intrinsic 395 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>], 396 [IntrNoMem]>; 397 398// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors. 399// Besides the table, VTBL has one other v8i8 argument and VTBX has two. 400// Overall, the classes range from 2 to 6 v8i8 arguments. 401class Neon_Tbl2Arg_Intrinsic 402 : Intrinsic<[llvm_v8i8_ty], 403 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; 404class Neon_Tbl3Arg_Intrinsic 405 : Intrinsic<[llvm_v8i8_ty], 406 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; 407class Neon_Tbl4Arg_Intrinsic 408 : Intrinsic<[llvm_v8i8_ty], 409 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], 410 [IntrNoMem]>; 411class Neon_Tbl5Arg_Intrinsic 412 : Intrinsic<[llvm_v8i8_ty], 413 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, 414 llvm_v8i8_ty], [IntrNoMem]>; 415class Neon_Tbl6Arg_Intrinsic 416 : Intrinsic<[llvm_v8i8_ty], 417 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, 418 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; 419 420// Arithmetic ops 421 422let IntrProperties = [IntrNoMem, Commutative] in { 423 424 // Vector Add. 425 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic; 426 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic; 427 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic; 428 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic; 429 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic; 430 431 // Vector Multiply. 432 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic; 433 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic; 434 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic; 435 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic; 436 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic; 437 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic; 438 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic; 439 440 // Vector Maximum. 441 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic; 442 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic; 443 def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic; 444 445 // Vector Minimum. 446 def int_arm_neon_vmins : Neon_2Arg_Intrinsic; 447 def int_arm_neon_vminu : Neon_2Arg_Intrinsic; 448 def int_arm_neon_vminnm : Neon_2Arg_Intrinsic; 449 450 // Vector Reciprocal Step. 451 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic; 452 453 // Vector Reciprocal Square Root Step. 454 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic; 455} 456 457// Vector Subtract. 458def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic; 459def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic; 460def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic; 461 462// Vector Absolute Compare. 463def int_arm_neon_vacge : Neon_Compare_Intrinsic; 464def int_arm_neon_vacgt : Neon_Compare_Intrinsic; 465 466// Vector Absolute Differences. 467def int_arm_neon_vabds : Neon_2Arg_Intrinsic; 468def int_arm_neon_vabdu : Neon_2Arg_Intrinsic; 469 470// Vector Pairwise Add. 471def int_arm_neon_vpadd : Neon_2Arg_Intrinsic; 472 473// Vector Pairwise Add Long. 474// Note: This is different than the other "long" NEON intrinsics because 475// the result vector has half as many elements as the source vector. 476// The source and destination vector types must be specified separately. 477def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], 478 [IntrNoMem]>; 479def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], 480 [IntrNoMem]>; 481 482// Vector Pairwise Add and Accumulate Long. 483// Note: This is similar to vpaddl but the destination vector also appears 484// as the first argument. 485def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty], 486 [LLVMMatchType<0>, llvm_anyvector_ty], 487 [IntrNoMem]>; 488def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty], 489 [LLVMMatchType<0>, llvm_anyvector_ty], 490 [IntrNoMem]>; 491 492// Vector Pairwise Maximum and Minimum. 493def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic; 494def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic; 495def int_arm_neon_vpmins : Neon_2Arg_Intrinsic; 496def int_arm_neon_vpminu : Neon_2Arg_Intrinsic; 497 498// Vector Shifts: 499// 500// The various saturating and rounding vector shift operations need to be 501// represented by intrinsics in LLVM, and even the basic VSHL variable shift 502// operation cannot be safely translated to LLVM's shift operators. VSHL can 503// be used for both left and right shifts, or even combinations of the two, 504// depending on the signs of the shift amounts. It also has well-defined 505// behavior for shift amounts that LLVM leaves undefined. Only basic shifts 506// by constants can be represented with LLVM's shift operators. 507// 508// The shift counts for these intrinsics are always vectors, even for constant 509// shifts, where the constant is replicated. For consistency with VSHL (and 510// other variable shift instructions), left shifts have positive shift counts 511// and right shifts have negative shift counts. This convention is also used 512// for constant right shift intrinsics, and to help preserve sanity, the 513// intrinsic names use "shift" instead of either "shl" or "shr". Where 514// applicable, signed and unsigned versions of the intrinsics are 515// distinguished with "s" and "u" suffixes. A few NEON shift instructions, 516// such as VQSHLU, take signed operands but produce unsigned results; these 517// use a "su" suffix. 518 519// Vector Shift. 520def int_arm_neon_vshifts : Neon_2Arg_Intrinsic; 521def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic; 522 523// Vector Rounding Shift. 524def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic; 525def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic; 526def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic; 527 528// Vector Saturating Shift. 529def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic; 530def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic; 531def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic; 532def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic; 533def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic; 534def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic; 535 536// Vector Saturating Rounding Shift. 537def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic; 538def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic; 539def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic; 540def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic; 541def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic; 542 543// Vector Shift and Insert. 544def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic; 545 546// Vector Absolute Value and Saturating Absolute Value. 547def int_arm_neon_vabs : Neon_1Arg_Intrinsic; 548def int_arm_neon_vqabs : Neon_1Arg_Intrinsic; 549 550// Vector Saturating Negate. 551def int_arm_neon_vqneg : Neon_1Arg_Intrinsic; 552 553// Vector Count Leading Sign/Zero Bits. 554def int_arm_neon_vcls : Neon_1Arg_Intrinsic; 555 556// Vector Reciprocal Estimate. 557def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic; 558 559// Vector Reciprocal Square Root Estimate. 560def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic; 561 562// Vector Conversions Between Floating-point and Integer 563def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic; 564def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic; 565def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic; 566def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic; 567def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic; 568def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic; 569def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic; 570def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic; 571 572// Vector Conversions Between Floating-point and Fixed-point. 573def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic; 574def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic; 575def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic; 576def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic; 577 578// Vector Conversions Between Half-Precision and Single-Precision. 579def int_arm_neon_vcvtfp2hf 580 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>; 581def int_arm_neon_vcvthf2fp 582 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>; 583 584// Narrowing Saturating Vector Moves. 585def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic; 586def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic; 587def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic; 588 589// Vector Table Lookup. 590// The first 1-4 arguments are the table. 591def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic; 592def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic; 593def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic; 594def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic; 595 596// Vector Table Extension. 597// Some elements of the destination vector may not be updated, so the original 598// value of that vector is passed as the first argument. The next 1-4 599// arguments after that are the table. 600def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic; 601def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic; 602def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic; 603def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic; 604 605// Vector and Scalar Rounding. 606def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic; 607def int_arm_neon_vrintx : Neon_1Arg_Intrinsic; 608def int_arm_neon_vrinta : Neon_1Arg_Intrinsic; 609def int_arm_neon_vrintz : Neon_1Arg_Intrinsic; 610def int_arm_neon_vrintm : Neon_1Arg_Intrinsic; 611def int_arm_neon_vrintp : Neon_1Arg_Intrinsic; 612 613// De-interleaving vector loads from N-element structures. 614// Source operands are the address and alignment. 615def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty], 616 [llvm_anyptr_ty, llvm_i32_ty], 617 [IntrReadMem, IntrArgMemOnly]>; 618def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 619 [llvm_anyptr_ty, llvm_i32_ty], 620 [IntrReadMem, IntrArgMemOnly]>; 621def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 622 LLVMMatchType<0>], 623 [llvm_anyptr_ty, llvm_i32_ty], 624 [IntrReadMem, IntrArgMemOnly]>; 625def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 626 LLVMMatchType<0>, LLVMMatchType<0>], 627 [llvm_anyptr_ty, llvm_i32_ty], 628 [IntrReadMem, IntrArgMemOnly]>; 629 630def int_arm_neon_vld1x2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 631 [LLVMAnyPointerType<LLVMMatchType<0>>], 632 [IntrReadMem, IntrArgMemOnly]>; 633def int_arm_neon_vld1x3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 634 LLVMMatchType<0>], 635 [LLVMAnyPointerType<LLVMMatchType<0>>], 636 [IntrReadMem, IntrArgMemOnly]>; 637def int_arm_neon_vld1x4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 638 LLVMMatchType<0>, LLVMMatchType<0>], 639 [LLVMAnyPointerType<LLVMMatchType<0>>], 640 [IntrReadMem, IntrArgMemOnly]>; 641 642// Vector load N-element structure to one lane. 643// Source operands are: the address, the N input vectors (since only one 644// lane is assigned), the lane number, and the alignment. 645def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 646 [llvm_anyptr_ty, LLVMMatchType<0>, 647 LLVMMatchType<0>, llvm_i32_ty, 648 llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>; 649def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 650 LLVMMatchType<0>], 651 [llvm_anyptr_ty, LLVMMatchType<0>, 652 LLVMMatchType<0>, LLVMMatchType<0>, 653 llvm_i32_ty, llvm_i32_ty], 654 [IntrReadMem, IntrArgMemOnly]>; 655def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 656 LLVMMatchType<0>, LLVMMatchType<0>], 657 [llvm_anyptr_ty, LLVMMatchType<0>, 658 LLVMMatchType<0>, LLVMMatchType<0>, 659 LLVMMatchType<0>, llvm_i32_ty, 660 llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>; 661 662// Vector load N-element structure to all lanes. 663// Source operands are the address and alignment. 664def int_arm_neon_vld2dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 665 [llvm_anyptr_ty, llvm_i32_ty], 666 [IntrReadMem, IntrArgMemOnly]>; 667def int_arm_neon_vld3dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 668 LLVMMatchType<0>], 669 [llvm_anyptr_ty, llvm_i32_ty], 670 [IntrReadMem, IntrArgMemOnly]>; 671def int_arm_neon_vld4dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 672 LLVMMatchType<0>, LLVMMatchType<0>], 673 [llvm_anyptr_ty, llvm_i32_ty], 674 [IntrReadMem, IntrArgMemOnly]>; 675 676// Interleaving vector stores from N-element structures. 677// Source operands are: the address, the N vectors, and the alignment. 678def int_arm_neon_vst1 : Intrinsic<[], 679 [llvm_anyptr_ty, llvm_anyvector_ty, 680 llvm_i32_ty], [IntrArgMemOnly]>; 681def int_arm_neon_vst2 : Intrinsic<[], 682 [llvm_anyptr_ty, llvm_anyvector_ty, 683 LLVMMatchType<1>, llvm_i32_ty], 684 [IntrArgMemOnly]>; 685def int_arm_neon_vst3 : Intrinsic<[], 686 [llvm_anyptr_ty, llvm_anyvector_ty, 687 LLVMMatchType<1>, LLVMMatchType<1>, 688 llvm_i32_ty], [IntrArgMemOnly]>; 689def int_arm_neon_vst4 : Intrinsic<[], 690 [llvm_anyptr_ty, llvm_anyvector_ty, 691 LLVMMatchType<1>, LLVMMatchType<1>, 692 LLVMMatchType<1>, llvm_i32_ty], 693 [IntrArgMemOnly]>; 694 695def int_arm_neon_vst1x2 : Intrinsic<[], 696 [llvm_anyptr_ty, llvm_anyvector_ty, 697 LLVMMatchType<1>], 698 [IntrArgMemOnly, NoCapture<0>]>; 699def int_arm_neon_vst1x3 : Intrinsic<[], 700 [llvm_anyptr_ty, llvm_anyvector_ty, 701 LLVMMatchType<1>, LLVMMatchType<1>], 702 [IntrArgMemOnly, NoCapture<0>]>; 703def int_arm_neon_vst1x4 : Intrinsic<[], 704 [llvm_anyptr_ty, llvm_anyvector_ty, 705 LLVMMatchType<1>, LLVMMatchType<1>, 706 LLVMMatchType<1>], 707 [IntrArgMemOnly, NoCapture<0>]>; 708 709// Vector store N-element structure from one lane. 710// Source operands are: the address, the N vectors, the lane number, and 711// the alignment. 712def int_arm_neon_vst2lane : Intrinsic<[], 713 [llvm_anyptr_ty, llvm_anyvector_ty, 714 LLVMMatchType<1>, llvm_i32_ty, 715 llvm_i32_ty], [IntrArgMemOnly]>; 716def int_arm_neon_vst3lane : Intrinsic<[], 717 [llvm_anyptr_ty, llvm_anyvector_ty, 718 LLVMMatchType<1>, LLVMMatchType<1>, 719 llvm_i32_ty, llvm_i32_ty], 720 [IntrArgMemOnly]>; 721def int_arm_neon_vst4lane : Intrinsic<[], 722 [llvm_anyptr_ty, llvm_anyvector_ty, 723 LLVMMatchType<1>, LLVMMatchType<1>, 724 LLVMMatchType<1>, llvm_i32_ty, 725 llvm_i32_ty], [IntrArgMemOnly]>; 726 727// Vector bitwise select. 728def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty], 729 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 730 [IntrNoMem]>; 731 732 733// Crypto instructions 734class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty], 735 [llvm_v16i8_ty], [IntrNoMem]>; 736class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty], 737 [llvm_v16i8_ty, llvm_v16i8_ty], 738 [IntrNoMem]>; 739 740class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], 741 [IntrNoMem]>; 742class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty], 743 [llvm_v4i32_ty, llvm_v4i32_ty], 744 [IntrNoMem]>; 745class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty], 746 [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty], 747 [IntrNoMem]>; 748class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty], 749 [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty], 750 [IntrNoMem]>; 751 752def int_arm_neon_aesd : AES_2Arg_Intrinsic; 753def int_arm_neon_aese : AES_2Arg_Intrinsic; 754def int_arm_neon_aesimc : AES_1Arg_Intrinsic; 755def int_arm_neon_aesmc : AES_1Arg_Intrinsic; 756def int_arm_neon_sha1h : SHA_1Arg_Intrinsic; 757def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic; 758def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic; 759def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic; 760def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic; 761def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic; 762def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic; 763def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic; 764def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic; 765def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic; 766 767// Armv8.2-A dot product instructions 768class Neon_Dot_Intrinsic 769 : Intrinsic<[llvm_anyvector_ty], 770 [LLVMMatchType<0>, llvm_anyvector_ty, 771 LLVMMatchType<1>], 772 [IntrNoMem]>; 773def int_arm_neon_udot : Neon_Dot_Intrinsic; 774def int_arm_neon_sdot : Neon_Dot_Intrinsic; 775 776def int_arm_cls: Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; 777def int_arm_cls64: Intrinsic<[llvm_i32_ty], [llvm_i64_ty], [IntrNoMem]>; 778 779def int_arm_mve_vctp8 : Intrinsic<[llvm_v16i1_ty], [llvm_i32_ty], [IntrNoMem]>; 780def int_arm_mve_vctp16 : Intrinsic<[llvm_v8i1_ty], [llvm_i32_ty], [IntrNoMem]>; 781def int_arm_mve_vctp32 : Intrinsic<[llvm_v4i1_ty], [llvm_i32_ty], [IntrNoMem]>; 782// vctp64 takes v4i1, to work around v2i1 not being a legal MVE type 783def int_arm_mve_vctp64 : Intrinsic<[llvm_v4i1_ty], [llvm_i32_ty], [IntrNoMem]>; 784 785// v8.3-A Floating-point complex add 786def int_arm_neon_vcadd_rot90 : Neon_2Arg_Intrinsic; 787def int_arm_neon_vcadd_rot270 : Neon_2Arg_Intrinsic; 788 789// GNU eabi mcount 790def int_arm_gnu_eabi_mcount : Intrinsic<[], 791 [], 792 [IntrReadMem, IntrWriteMem]>; 793 794def int_arm_mve_pred_i2v : Intrinsic< 795 [llvm_anyvector_ty], [llvm_i32_ty], [IntrNoMem]>; 796def int_arm_mve_pred_v2i : Intrinsic< 797 [llvm_i32_ty], [llvm_anyvector_ty], [IntrNoMem]>; 798 799multiclass IntrinsicSignSuffix<list<LLVMType> rets, list<LLVMType> params = [], 800 list<IntrinsicProperty> props = [], 801 string name = "", 802 list<SDNodeProperty> sdprops = []> { 803 def _s: Intrinsic<rets, params, props, name, sdprops>; 804 def _u: Intrinsic<rets, params, props, name, sdprops>; 805} 806 807def int_arm_mve_min_predicated: Intrinsic<[llvm_anyvector_ty], 808 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */, 809 llvm_anyvector_ty, LLVMMatchType<0>], 810 [IntrNoMem]>; 811def int_arm_mve_max_predicated: Intrinsic<[llvm_anyvector_ty], 812 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */, 813 llvm_anyvector_ty, LLVMMatchType<0>], 814 [IntrNoMem]>; 815def int_arm_mve_abd_predicated: Intrinsic<[llvm_anyvector_ty], 816 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */, 817 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; 818def int_arm_mve_add_predicated: Intrinsic<[llvm_anyvector_ty], 819 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], 820 [IntrNoMem]>; 821def int_arm_mve_and_predicated: Intrinsic<[llvm_anyvector_ty], 822 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], 823 [IntrNoMem]>; 824def int_arm_mve_bic_predicated: Intrinsic<[llvm_anyvector_ty], 825 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], 826 [IntrNoMem]>; 827def int_arm_mve_eor_predicated: Intrinsic<[llvm_anyvector_ty], 828 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], 829 [IntrNoMem]>; 830def int_arm_mve_orn_predicated: Intrinsic<[llvm_anyvector_ty], 831 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], 832 [IntrNoMem]>; 833def int_arm_mve_orr_predicated: Intrinsic<[llvm_anyvector_ty], 834 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], 835 [IntrNoMem]>; 836def int_arm_mve_sub_predicated: Intrinsic<[llvm_anyvector_ty], 837 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], 838 [IntrNoMem]>; 839def int_arm_mve_mul_predicated: Intrinsic<[llvm_anyvector_ty], 840 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], 841 [IntrNoMem]>; 842def int_arm_mve_mulh_predicated: Intrinsic<[llvm_anyvector_ty], 843 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */, 844 llvm_anyvector_ty, LLVMMatchType<0>], 845 [IntrNoMem]>; 846def int_arm_mve_qdmulh_predicated: Intrinsic<[llvm_anyvector_ty], 847 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], 848 [IntrNoMem]>; 849def int_arm_mve_rmulh_predicated: Intrinsic<[llvm_anyvector_ty], 850 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */, 851 llvm_anyvector_ty, LLVMMatchType<0>], 852 [IntrNoMem]>; 853def int_arm_mve_qrdmulh_predicated: Intrinsic<[llvm_anyvector_ty], 854 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], 855 [IntrNoMem]>; 856def int_arm_mve_mull_int_predicated: Intrinsic<[llvm_anyvector_ty], 857 [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty /* unsigned */, 858 llvm_i32_ty /* top */, llvm_anyvector_ty, LLVMMatchType<0>], 859 [IntrNoMem]>; 860def int_arm_mve_mull_poly_predicated: Intrinsic<[llvm_anyvector_ty], 861 [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty, 862 LLVMMatchType<0>], 863 [IntrNoMem]>; 864def int_arm_mve_qadd_predicated: Intrinsic<[llvm_anyvector_ty], 865 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */, 866 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; 867def int_arm_mve_hadd_predicated: Intrinsic<[llvm_anyvector_ty], 868 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */, 869 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; 870def int_arm_mve_rhadd_predicated: Intrinsic<[llvm_anyvector_ty], 871 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */, 872 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; 873def int_arm_mve_qsub_predicated: Intrinsic<[llvm_anyvector_ty], 874 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */, 875 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; 876def int_arm_mve_hsub_predicated: Intrinsic<[llvm_anyvector_ty], 877 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */, 878 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; 879 880defm int_arm_mve_minv: IntrinsicSignSuffix<[llvm_i32_ty], 881 [llvm_i32_ty, llvm_anyvector_ty], [IntrNoMem]>; 882defm int_arm_mve_maxv: IntrinsicSignSuffix<[llvm_i32_ty], 883 [llvm_i32_ty, llvm_anyvector_ty], [IntrNoMem]>; 884 885multiclass MVEPredicated<list<LLVMType> rets, list<LLVMType> params, 886 LLVMType pred = llvm_anyvector_ty, 887 list<IntrinsicProperty> props = [IntrNoMem]> { 888 def "": Intrinsic<rets, params, props>; 889 def _predicated: Intrinsic<rets, params # [pred], props>; 890} 891multiclass MVEPredicatedM<list<LLVMType> rets, list<LLVMType> params, 892 LLVMType pred = llvm_anyvector_ty, 893 list<IntrinsicProperty> props = [IntrNoMem]> { 894 def "": Intrinsic<rets, params, props>; 895 def _predicated: Intrinsic<rets, params # [pred, 896 !if(!eq(!cast<string>(rets[0]), "llvm_anyvector_ty"), 897 LLVMMatchType<0>, rets[0])], props>; 898} 899 900defm int_arm_mve_vcvt_narrow: MVEPredicated<[llvm_v8f16_ty], 901 [llvm_v8f16_ty, llvm_v4f32_ty, llvm_i32_ty], llvm_v4i1_ty>; 902 903defm int_arm_mve_vldr_gather_base: MVEPredicated< 904 [llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty], 905 llvm_anyvector_ty, [IntrReadMem]>; 906defm int_arm_mve_vldr_gather_base_wb: MVEPredicated< 907 [llvm_anyvector_ty, llvm_anyvector_ty], 908 [LLVMMatchType<1>, llvm_i32_ty], llvm_anyvector_ty, [IntrReadMem]>; 909defm int_arm_mve_vstr_scatter_base: MVEPredicated< 910 [], [llvm_anyvector_ty, llvm_i32_ty, llvm_anyvector_ty], 911 llvm_anyvector_ty, [IntrWriteMem]>; 912defm int_arm_mve_vstr_scatter_base_wb: MVEPredicated< 913 [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty, llvm_anyvector_ty], 914 llvm_anyvector_ty, [IntrWriteMem]>; 915 916// gather_offset takes three i32 parameters. The first is the size of 917// memory element loaded, in bits. The second is a left bit shift to 918// apply to each offset in the vector parameter (must be either 0, or 919// correspond to the element size of the destination vector type). The 920// last is 1 to indicate zero extension (if the load is widening), or 921// 0 for sign extension. 922// 923// scatter_offset has the first two of those parameters, but since it 924// narrows rather than widening, it doesn't have the last one. 925defm int_arm_mve_vldr_gather_offset: MVEPredicated< 926 [llvm_anyvector_ty], [llvm_anyptr_ty, llvm_anyvector_ty, 927 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], llvm_anyvector_ty, [IntrReadMem]>; 928defm int_arm_mve_vstr_scatter_offset: MVEPredicated< 929 [], [llvm_anyptr_ty, llvm_anyvector_ty, llvm_anyvector_ty, 930 llvm_i32_ty, llvm_i32_ty], llvm_anyvector_ty, [IntrWriteMem]>; 931 932def int_arm_mve_shl_imm_predicated: Intrinsic<[llvm_anyvector_ty], 933 [LLVMMatchType<0>, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>], 934 [IntrNoMem]>; 935def int_arm_mve_shr_imm_predicated: Intrinsic<[llvm_anyvector_ty], 936 [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty, // extra i32 is unsigned flag 937 llvm_anyvector_ty, LLVMMatchType<0>], 938 [IntrNoMem]>; 939 940defm int_arm_mve_vqshl_imm: MVEPredicatedM<[llvm_anyvector_ty], 941 [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*unsigned*/]>; 942defm int_arm_mve_vrshr_imm: MVEPredicatedM<[llvm_anyvector_ty], 943 [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*unsigned*/]>; 944defm int_arm_mve_vqshlu_imm: MVEPredicatedM<[llvm_anyvector_ty], 945 [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/]>; 946defm int_arm_mve_vshll_imm: MVEPredicatedM<[llvm_anyvector_ty], 947 [llvm_anyvector_ty, llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*unsigned*/, 948 llvm_i32_ty /*top-half*/]>; 949 950defm int_arm_mve_vsli: MVEPredicated< 951 [llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty]>; 952defm int_arm_mve_vsri: MVEPredicated< 953 [llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty]>; 954 955defm int_arm_mve_vshrn: MVEPredicated< 956 [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty, 957 llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*saturate*/, llvm_i32_ty /*round*/, 958 llvm_i32_ty /*unsigned-out*/, llvm_i32_ty /*unsigned-in*/, 959 llvm_i32_ty /*top-half*/]>; 960 961defm int_arm_mve_vshl_scalar: MVEPredicated< 962 [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/, 963 llvm_i32_ty /*saturate*/, llvm_i32_ty /*round*/, llvm_i32_ty /*unsigned*/]>; 964defm int_arm_mve_vshl_vector: MVEPredicatedM< 965 [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty /*shiftcounts*/, 966 llvm_i32_ty /*saturate*/, llvm_i32_ty /*round*/, llvm_i32_ty /*unsigned*/]>; 967 968// MVE scalar shifts. 969class ARM_MVE_qrshift_single<list<LLVMType> value, 970 list<LLVMType> saturate = []> : 971 Intrinsic<value, value # [llvm_i32_ty] # saturate, [IntrNoMem]>; 972multiclass ARM_MVE_qrshift<list<LLVMType> saturate = []> { 973 // Most of these shifts come in 32- and 64-bit versions. But only 974 // the 64-bit ones have the extra saturation argument (if any). 975 def "": ARM_MVE_qrshift_single<[llvm_i32_ty]>; 976 def l: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty], saturate>; 977} 978defm int_arm_mve_urshr: ARM_MVE_qrshift; 979defm int_arm_mve_uqshl: ARM_MVE_qrshift; 980defm int_arm_mve_srshr: ARM_MVE_qrshift; 981defm int_arm_mve_sqshl: ARM_MVE_qrshift; 982defm int_arm_mve_uqrshl: ARM_MVE_qrshift<[llvm_i32_ty]>; 983defm int_arm_mve_sqrshr: ARM_MVE_qrshift<[llvm_i32_ty]>; 984// LSLL and ASRL only have 64-bit versions, not 32. 985def int_arm_mve_lsll: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty]>; 986def int_arm_mve_asrl: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty]>; 987 988def int_arm_mve_vabd: Intrinsic< 989 [llvm_anyvector_ty], 990 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */], 991 [IntrNoMem]>; 992def int_arm_mve_vadc: Intrinsic< 993 [llvm_anyvector_ty, llvm_i32_ty], 994 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]>; 995def int_arm_mve_vadc_predicated: Intrinsic< 996 [llvm_anyvector_ty, llvm_i32_ty], 997 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, 998 llvm_i32_ty, llvm_anyvector_ty], [IntrNoMem]>; 999def int_arm_mve_vmulh: Intrinsic< 1000 [llvm_anyvector_ty], 1001 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */], 1002 [IntrNoMem]>; 1003def int_arm_mve_vqdmulh: Intrinsic< 1004 [llvm_anyvector_ty], 1005 [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; 1006def int_arm_mve_vhadd: Intrinsic< 1007 [llvm_anyvector_ty], 1008 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */], 1009 [IntrNoMem]>; 1010def int_arm_mve_vrhadd: Intrinsic< 1011 [llvm_anyvector_ty], 1012 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */], 1013 [IntrNoMem]>; 1014def int_arm_mve_vhsub: Intrinsic< 1015 [llvm_anyvector_ty], 1016 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */], 1017 [IntrNoMem]>; 1018def int_arm_mve_vrmulh: Intrinsic< 1019 [llvm_anyvector_ty], 1020 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */], 1021 [IntrNoMem]>; 1022def int_arm_mve_vqrdmulh: Intrinsic< 1023 [llvm_anyvector_ty], 1024 [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; 1025def int_arm_mve_vmull: Intrinsic< 1026 [llvm_anyvector_ty], 1027 [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty /* unsigned */, 1028 llvm_i32_ty /* top */], [IntrNoMem]>; 1029def int_arm_mve_vmull_poly: Intrinsic< 1030 [llvm_anyvector_ty], 1031 [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty], [IntrNoMem]>; 1032 1033// Intrinsic with a predicated and a non-predicated case. The predicated case 1034// has two additional parameters: inactive (the value for inactive lanes, can 1035// be undef) and predicate. 1036multiclass MVEMXPredicated<list<LLVMType> rets, list<LLVMType> flags, 1037 list<LLVMType> params, LLVMType inactive, 1038 LLVMType predicate, 1039 list<IntrinsicProperty> props = [IntrNoMem]> { 1040 def "": Intrinsic<rets, flags # params, props>; 1041 def _predicated: Intrinsic<rets, flags # [inactive] # params # [predicate], 1042 props>; 1043} 1044 1045// The first two parameters are compile-time constants: 1046// * Halving: 0 means halving (vhcaddq), 1 means non-halving (vcaddq) 1047// instruction. Note: the flag is inverted to match the corresonding 1048// bit in the instruction encoding 1049// * Rotation angle: 0 mean 90 deg, 1 means 180 deg 1050defm int_arm_mve_vcaddq : MVEMXPredicated< 1051 [llvm_anyvector_ty], 1052 [llvm_i32_ty, llvm_i32_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 1053 LLVMMatchType<0>, llvm_anyvector_ty>; 1054 1055// The first operand of the following two intrinsics is the rotation angle 1056// (must be a compile-time constant): 1057// 0 - 0 deg 1058// 1 - 90 deg 1059// 2 - 180 deg 1060// 3 - 270 deg 1061defm int_arm_mve_vcmulq : MVEMXPredicated< 1062 [llvm_anyvector_ty], 1063 [llvm_i32_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 1064 LLVMMatchType<0>, llvm_anyvector_ty>; 1065 1066defm int_arm_mve_vcmlaq : MVEPredicated< 1067 [llvm_anyvector_ty], 1068 [llvm_i32_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 1069 llvm_anyvector_ty>; 1070 1071def int_arm_mve_vld2q: Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_anyptr_ty], [IntrReadMem]>; 1072def int_arm_mve_vld4q: Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [llvm_anyptr_ty], [IntrReadMem]>; 1073 1074def int_arm_mve_vst2q: Intrinsic<[], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty], [IntrWriteMem]>; 1075def int_arm_mve_vst4q: Intrinsic<[], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>, LLVMMatchType<1>, llvm_i32_ty], [IntrWriteMem] 1076>; 1077 1078// MVE vector absolute difference and accumulate across vector 1079// The first operand is an 'unsigned' flag. The remaining operands are: 1080// * accumulator 1081// * first vector operand 1082// * second vector operand 1083// * mask (only in predicated versions) 1084defm int_arm_mve_vabav: MVEPredicated< 1085 [llvm_i32_ty], 1086 [llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>], llvm_anyvector_ty>; 1087 1088// The following 3 instrinsics are MVE vector reductions with two vector 1089// operands. 1090// The first 3 operands are boolean flags (must be compile-time constants): 1091// * unsigned - the instruction operates on vectors of unsigned values and 1092// unsigned scalars 1093// * subtract - the instruction performs subtraction after multiplication of 1094// lane pairs (e.g., vmlsdav vs vmladav) 1095// * exchange - the instruction exchanges successive even and odd lanes of 1096// the first operands before multiplication of lane pairs 1097// (e.g., vmladavx vs vmladav) 1098// The remaining operands are: 1099// * accumulator 1100// * first vector operand 1101// * second vector operand 1102// * mask (only in predicated versions) 1103 1104// Version with 32-bit result, vml{a,s}dav[a][x] 1105defm int_arm_mve_vmldava: MVEPredicated< 1106 [llvm_i32_ty], 1107 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 1108 llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>], 1109 llvm_anyvector_ty>; 1110 1111// Version with 64-bit result, vml{a,s}ldav[a][x] 1112defm int_arm_mve_vmlldava: MVEPredicated< 1113 [llvm_i32_ty, llvm_i32_ty], 1114 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 1115 llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>], 1116 llvm_anyvector_ty>; 1117 1118// Version with 72-bit rounded result, vrml{a,s}ldavh[a][x] 1119defm int_arm_mve_vrmlldavha: MVEPredicated< 1120 [llvm_i32_ty, llvm_i32_ty], 1121 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 1122 llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>], 1123 llvm_anyvector_ty>; 1124} // end TargetPrefix 1125