1//===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===// 2// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 3// See https://llvm.org/LICENSE.txt for license information. 4// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 5// 6//===----------------------------------------------------------------------===// 7// 8// This file defines all of the Hexagon-specific intrinsics. 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Definitions for all Hexagon intrinsics. 14// 15// All Hexagon intrinsics start with "llvm.hexagon.". 16let TargetPrefix = "hexagon" in { 17 /// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics. 18 class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types, 19 list<LLVMType> param_types, 20 list<IntrinsicProperty> properties> 21 : ClangBuiltin<!strconcat("__builtin_", GCCIntSuffix)>, 22 Intrinsic<ret_types, param_types, properties>; 23 24 /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon 25 /// intrinsics. 26 class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types, 27 list<LLVMType> param_types, 28 list<IntrinsicProperty> properties> 29 : Intrinsic<ret_types, param_types, properties>; 30} 31 32class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix> 33 : Hexagon_Intrinsic<GCCIntSuffix, 34 [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty, 35 llvm_i32_ty], 36 [IntrArgMemOnly]>; 37 38class Hexagon_mem_memsisi_Intrinsic<string GCCIntSuffix> 39 : Hexagon_Intrinsic<GCCIntSuffix, 40 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, 41 llvm_i32_ty], 42 [IntrWriteMem]>; 43 44class Hexagon_mem_memdisi_Intrinsic<string GCCIntSuffix> 45 : Hexagon_Intrinsic<GCCIntSuffix, 46 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty, 47 llvm_i32_ty], 48 [IntrWriteMem]>; 49 50class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix> 51 : Hexagon_Intrinsic<GCCIntSuffix, 52 [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty, 53 llvm_i32_ty, llvm_i32_ty], 54 [IntrArgMemOnly, ImmArg<ArgIndex<3>>]>; 55 56class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix> 57 : Hexagon_Intrinsic<GCCIntSuffix, 58 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, 59 llvm_i32_ty, llvm_i32_ty], 60 [IntrWriteMem, ImmArg<ArgIndex<3>>]>; 61 62class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix> 63 : Hexagon_Intrinsic<GCCIntSuffix, 64 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty, 65 llvm_i32_ty, llvm_i32_ty], 66 [IntrWriteMem, ImmArg<ArgIndex<3>>]>; 67 68// 69// BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4) 70// 71def int_hexagon_circ_ldd : 72Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">; 73// 74// BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4) 75// 76def int_hexagon_circ_ldw : 77Hexagon_mem_memmemsisi_Intrinsic<"circ_ldw">; 78// 79// BUILTIN_INFO_NONCONST(circ_ldh,PTR_ftype_PTRPTRSISI,4) 80// 81def int_hexagon_circ_ldh : 82Hexagon_mem_memmemsisi_Intrinsic<"circ_ldh">; 83// 84// BUILTIN_INFO_NONCONST(circ_lduh,PTR_ftype_PTRPTRSISI,4) 85// 86def int_hexagon_circ_lduh : 87Hexagon_mem_memmemsisi_Intrinsic<"circ_lduh">; 88// 89// BUILTIN_INFO_NONCONST(circ_ldb,PTR_ftype_PTRPTRSISI,4) 90// 91def int_hexagon_circ_ldb : 92Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">; 93// 94// BUILTIN_INFO_NONCONST(circ_ldub,PTR_ftype_PTRPTRSISI,4) 95// 96def int_hexagon_circ_ldub : 97Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">; 98 99// 100// BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4) 101// 102def int_hexagon_circ_std : 103Hexagon_mem_memdisisi_Intrinsic<"circ_std">; 104// 105// BUILTIN_INFO_NONCONST(circ_stw,PTR_ftype_PTRSISISI,4) 106// 107def int_hexagon_circ_stw : 108Hexagon_mem_memsisisi_Intrinsic<"circ_stw">; 109// 110// BUILTIN_INFO_NONCONST(circ_sth,PTR_ftype_PTRSISISI,4) 111// 112def int_hexagon_circ_sth : 113Hexagon_mem_memsisisi_Intrinsic<"circ_sth">; 114// 115// BUILTIN_INFO_NONCONST(circ_sthhi,PTR_ftype_PTRSISISI,4) 116// 117def int_hexagon_circ_sthhi : 118Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">; 119// 120// BUILTIN_INFO_NONCONST(circ_stb,PTR_ftype_PTRSISISI,4) 121// 122def int_hexagon_circ_stb : 123Hexagon_mem_memsisisi_Intrinsic<"circ_stb">; 124 125def int_hexagon_prefetch : 126Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>; 127 128def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>; 129def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>; 130 131// Mark locked loads as read/write to prevent any accidental reordering. 132def int_hexagon_L2_loadw_locked : 133Hexagon_Intrinsic<"HEXAGON_L2_loadw_locked", [llvm_i32_ty], [llvm_ptr32_ty], 134 [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; 135def int_hexagon_L4_loadd_locked : 136Hexagon_Intrinsic<"HEXAGON_L4_loadd_locked", [llvm_i64_ty], [llvm_ptr64_ty], 137 [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; 138 139def int_hexagon_S2_storew_locked : 140Hexagon_Intrinsic<"HEXAGON_S2_storew_locked", [llvm_i32_ty], 141 [llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; 142def int_hexagon_S4_stored_locked : 143Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty], 144 [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; 145 146def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy", 147 [], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], 148 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>, WriteOnly<ArgIndex<0>>, ReadOnly<ArgIndex<1>>]>; 149 150def int_hexagon_vmemset : Hexagon_Intrinsic<"hexagon_vmemset", 151 [], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 152 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>]>; 153 154multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> { 155 def NAME#_pci : Hexagon_NonGCC_Intrinsic< 156 [ElTy, llvm_ptr_ty], 157 [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], 158 [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>; 159 def NAME#_pcr : Hexagon_NonGCC_Intrinsic< 160 [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty], 161 [IntrArgMemOnly, NoCapture<ArgIndex<2>>]>; 162} 163 164defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 165defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 166defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 167defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 168defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 169defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>; 170 171multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> { 172 def NAME#_pci : Hexagon_NonGCC_Intrinsic< 173 [llvm_ptr_ty], 174 [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], 175 [IntrArgMemOnly, NoCapture<ArgIndex<4>>]>; 176 def NAME#_pcr : Hexagon_NonGCC_Intrinsic< 177 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], 178 [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>; 179} 180 181defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 182defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 183defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 184defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 185defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>; 186 187// The front-end emits the intrinsic call with only two arguments. The third 188// argument from the builtin is already used by front-end to write to memory 189// by generating a store. 190class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy> 191 : Hexagon_NonGCC_Intrinsic< 192 [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], 193 [IntrReadMem]>; 194 195def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 196def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 197def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 198def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 199def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 200def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>; 201 202def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">; 203def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">; 204def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">; 205def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">; 206def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">; 207 208// tag : V6_vrmpybub_rtt 209class Hexagon_v32i32_v16i32i64_rtt_Intrinsic<string GCCIntSuffix> 210 : Hexagon_Intrinsic<GCCIntSuffix, 211 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty], 212 [IntrNoMem]>; 213 214// tag : V6_vrmpybub_rtt_128B 215class Hexagon_v64i32_v32i32i64_rtt_Intrinsic<string GCCIntSuffix> 216 : Hexagon_Intrinsic<GCCIntSuffix, 217 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty], 218 [IntrNoMem]>; 219 220// tag : V6_vrmpybub_rtt_acc 221class Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<string GCCIntSuffix> 222 : Hexagon_Intrinsic<GCCIntSuffix, 223 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty], 224 [IntrNoMem]>; 225 226// tag : V6_vrmpybub_rtt_acc_128B 227class Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<string GCCIntSuffix> 228 : Hexagon_Intrinsic<GCCIntSuffix, 229 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty], 230 [IntrNoMem]>; 231 232def int_hexagon_V6_vrmpybub_rtt : 233Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">; 234 235def int_hexagon_V6_vrmpybub_rtt_128B : 236Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">; 237 238def int_hexagon_V6_vrmpybub_rtt_acc : 239Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">; 240 241def int_hexagon_V6_vrmpybub_rtt_acc_128B : 242Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">; 243 244def int_hexagon_V6_vrmpyub_rtt : 245Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">; 246 247def int_hexagon_V6_vrmpyub_rtt_128B : 248Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">; 249 250def int_hexagon_V6_vrmpyub_rtt_acc : 251Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">; 252 253def int_hexagon_V6_vrmpyub_rtt_acc_128B : 254Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">; 255 256// HVX conditional loads/stores 257 258class Hexagon_pred_vload_imm<LLVMType ValTy> 259 : Hexagon_NonGCC_Intrinsic< 260 [ValTy], 261 [llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty], 262 [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, 263 ImmArg<ArgIndex<2>>]>; 264 265class Hexagon_pred_vload_imm_64B: Hexagon_pred_vload_imm<llvm_v16i32_ty>; 266class Hexagon_pred_vload_imm_128B: Hexagon_pred_vload_imm<llvm_v32i32_ty>; 267 268def int_hexagon_V6_vL32b_pred_ai: Hexagon_pred_vload_imm_64B; 269def int_hexagon_V6_vL32b_npred_ai: Hexagon_pred_vload_imm_64B; 270def int_hexagon_V6_vL32b_nt_pred_ai: Hexagon_pred_vload_imm_64B; 271def int_hexagon_V6_vL32b_nt_npred_ai: Hexagon_pred_vload_imm_64B; 272def int_hexagon_V6_vL32b_pred_ai_128B: Hexagon_pred_vload_imm_128B; 273def int_hexagon_V6_vL32b_npred_ai_128B: Hexagon_pred_vload_imm_128B; 274def int_hexagon_V6_vL32b_nt_pred_ai_128B: Hexagon_pred_vload_imm_128B; 275def int_hexagon_V6_vL32b_nt_npred_ai_128B: Hexagon_pred_vload_imm_128B; 276 277class Hexagom_pred_vload_upd<LLVMType ValTy, bit TakesImm> 278 : Hexagon_NonGCC_Intrinsic< 279 [ValTy, LLVMPointerType<ValTy>], 280 [llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty], 281 !if(TakesImm, 282 [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, 283 ImmArg<ArgIndex<2>>], 284 [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>])>; 285 286class Hexagom_pred_vload_upd_64B<bit TakesImm> 287 : Hexagom_pred_vload_upd<llvm_v16i32_ty, TakesImm>; 288class Hexagom_pred_vload_upd_128B<bit TakesImm> 289 : Hexagom_pred_vload_upd<llvm_v32i32_ty, TakesImm>; 290 291def int_hexagon_V6_vL32b_pred_pi: Hexagom_pred_vload_upd_64B<1>; 292def int_hexagon_V6_vL32b_npred_pi: Hexagom_pred_vload_upd_64B<1>; 293def int_hexagon_V6_vL32b_nt_pred_pi: Hexagom_pred_vload_upd_64B<1>; 294def int_hexagon_V6_vL32b_nt_npred_pi: Hexagom_pred_vload_upd_64B<1>; 295def int_hexagon_V6_vL32b_pred_pi_128B: Hexagom_pred_vload_upd_128B<1>; 296def int_hexagon_V6_vL32b_npred_pi_128B: Hexagom_pred_vload_upd_128B<1>; 297def int_hexagon_V6_vL32b_nt_pred_pi_128B: Hexagom_pred_vload_upd_128B<1>; 298def int_hexagon_V6_vL32b_nt_npred_pi_128B: Hexagom_pred_vload_upd_128B<1>; 299 300def int_hexagon_V6_vL32b_pred_ppu: Hexagom_pred_vload_upd_64B<0>; 301def int_hexagon_V6_vL32b_npred_ppu: Hexagom_pred_vload_upd_64B<0>; 302def int_hexagon_V6_vL32b_nt_pred_ppu: Hexagom_pred_vload_upd_64B<0>; 303def int_hexagon_V6_vL32b_nt_npred_ppu: Hexagom_pred_vload_upd_64B<0>; 304def int_hexagon_V6_vL32b_pred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; 305def int_hexagon_V6_vL32b_npred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; 306def int_hexagon_V6_vL32b_nt_pred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; 307def int_hexagon_V6_vL32b_nt_npred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; 308 309 310class Hexagon_pred_vstore_imm<LLVMType ValTy> 311 : Hexagon_NonGCC_Intrinsic< 312 [], 313 [llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty, ValTy], 314 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, 315 ImmArg<ArgIndex<2>>]>; 316 317class Hexagon_pred_vstore_imm_64B: Hexagon_pred_vstore_imm<llvm_v16i32_ty>; 318class Hexagon_pred_vstore_imm_128B: Hexagon_pred_vstore_imm<llvm_v32i32_ty>; 319 320def int_hexagon_V6_vS32b_pred_ai: Hexagon_pred_vstore_imm_64B; 321def int_hexagon_V6_vS32b_npred_ai: Hexagon_pred_vstore_imm_64B; 322def int_hexagon_V6_vS32Ub_pred_ai: Hexagon_pred_vstore_imm_64B; 323def int_hexagon_V6_vS32Ub_npred_ai: Hexagon_pred_vstore_imm_64B; 324def int_hexagon_V6_vS32b_nt_pred_ai: Hexagon_pred_vstore_imm_64B; 325def int_hexagon_V6_vS32b_nt_npred_ai: Hexagon_pred_vstore_imm_64B; 326def int_hexagon_V6_vS32b_pred_ai_128B: Hexagon_pred_vstore_imm_128B; 327def int_hexagon_V6_vS32b_npred_ai_128B: Hexagon_pred_vstore_imm_128B; 328def int_hexagon_V6_vS32Ub_pred_ai_128B: Hexagon_pred_vstore_imm_128B; 329def int_hexagon_V6_vS32Ub_npred_ai_128B: Hexagon_pred_vstore_imm_128B; 330def int_hexagon_V6_vS32b_nt_pred_ai_128B: Hexagon_pred_vstore_imm_128B; 331def int_hexagon_V6_vS32b_nt_npred_ai_128B: Hexagon_pred_vstore_imm_128B; 332 333class Hexagon_pred_vstore_upd<LLVMType ValTy, bit TakesImm> 334 : Hexagon_NonGCC_Intrinsic< 335 [LLVMPointerType<ValTy>], 336 [llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty, ValTy], 337 !if(TakesImm, 338 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, 339 ImmArg<ArgIndex<2>>], 340 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>])>; 341 342class Hexagon_pred_vstore_upd_64B<bit TakesImm> 343 : Hexagon_pred_vstore_upd<llvm_v16i32_ty, TakesImm>; 344class Hexagon_pred_vstore_upd_128B<bit TakesImm> 345 : Hexagon_pred_vstore_upd<llvm_v32i32_ty, TakesImm>; 346 347def int_hexagon_V6_vS32b_pred_pi: Hexagon_pred_vstore_upd_64B<1>; 348def int_hexagon_V6_vS32b_npred_pi: Hexagon_pred_vstore_upd_64B<1>; 349def int_hexagon_V6_vS32Ub_pred_pi: Hexagon_pred_vstore_upd_64B<1>; 350def int_hexagon_V6_vS32Ub_npred_pi: Hexagon_pred_vstore_upd_64B<1>; 351def int_hexagon_V6_vS32b_nt_pred_pi: Hexagon_pred_vstore_upd_64B<1>; 352def int_hexagon_V6_vS32b_nt_npred_pi: Hexagon_pred_vstore_upd_64B<1>; 353def int_hexagon_V6_vS32b_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 354def int_hexagon_V6_vS32b_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 355def int_hexagon_V6_vS32Ub_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 356def int_hexagon_V6_vS32Ub_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 357def int_hexagon_V6_vS32b_nt_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 358def int_hexagon_V6_vS32b_nt_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 359 360def int_hexagon_V6_vS32b_pred_ppu: Hexagon_pred_vstore_upd_64B<0>; 361def int_hexagon_V6_vS32b_npred_ppu: Hexagon_pred_vstore_upd_64B<0>; 362def int_hexagon_V6_vS32Ub_pred_ppu: Hexagon_pred_vstore_upd_64B<0>; 363def int_hexagon_V6_vS32Ub_npred_ppu: Hexagon_pred_vstore_upd_64B<0>; 364def int_hexagon_V6_vS32b_nt_pred_ppu: Hexagon_pred_vstore_upd_64B<0>; 365def int_hexagon_V6_vS32b_nt_npred_ppu: Hexagon_pred_vstore_upd_64B<0>; 366def int_hexagon_V6_vS32b_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 367def int_hexagon_V6_vS32b_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 368def int_hexagon_V6_vS32Ub_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 369def int_hexagon_V6_vS32Ub_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 370def int_hexagon_V6_vS32b_nt_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 371def int_hexagon_V6_vS32b_nt_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 372 373 374// HVX Vector predicate casts. 375// These intrinsics do not emit (nor do they correspond to) any instructions, 376// they are no-ops. 377 378def int_hexagon_V6_pred_typecast : 379Hexagon_NonGCC_Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; 380 381def int_hexagon_V6_pred_typecast_128B : 382Hexagon_NonGCC_Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; 383 384// Masked vector stores 385// 386// These are all deprecated, the intrinsics matching instruction names 387// should be used instead, e.g. int_hexagon_V6_vS32b_qpred_ai, etc. 388 389class Hexagon_custom_vms_Intrinsic 390 : Hexagon_NonGCC_Intrinsic< 391 [], [llvm_v64i1_ty,llvm_ptr_ty,llvm_v16i32_ty], [IntrWriteMem]>; 392 393class Hexagon_custom_vms_Intrinsic_128B 394 : Hexagon_NonGCC_Intrinsic< 395 [], [llvm_v128i1_ty,llvm_ptr_ty,llvm_v32i32_ty], [IntrWriteMem]>; 396 397def int_hexagon_V6_vmaskedstoreq: Hexagon_custom_vms_Intrinsic; 398def int_hexagon_V6_vmaskedstorenq: Hexagon_custom_vms_Intrinsic; 399def int_hexagon_V6_vmaskedstorentq: Hexagon_custom_vms_Intrinsic; 400def int_hexagon_V6_vmaskedstorentnq: Hexagon_custom_vms_Intrinsic; 401 402def int_hexagon_V6_vmaskedstoreq_128B: Hexagon_custom_vms_Intrinsic_128B; 403def int_hexagon_V6_vmaskedstorenq_128B: Hexagon_custom_vms_Intrinsic_128B; 404def int_hexagon_V6_vmaskedstorentq_128B: Hexagon_custom_vms_Intrinsic_128B; 405def int_hexagon_V6_vmaskedstorentnq_128B: Hexagon_custom_vms_Intrinsic_128B; 406 407 408// Intrinsic for instrumentation based profiling using a custom handler. The 409// name of the handler is passed as the first operand to the intrinsic. The 410// handler can take only one int32 input which is passed as the second 411// operand to the intrinsic. 412def int_hexagon_instrprof_custom 413 : Hexagon_NonGCC_Intrinsic<[], 414 [llvm_ptr_ty, llvm_i32_ty], 415 [IntrInaccessibleMemOnly]>; 416 417 418include "llvm/IR/IntrinsicsHexagonDep.td" 419