1//===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===// 2// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 3// See https://llvm.org/LICENSE.txt for license information. 4// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 5// 6//===----------------------------------------------------------------------===// 7// 8// This file defines all of the Hexagon-specific intrinsics. 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Definitions for all Hexagon intrinsics. 14// 15// All Hexagon intrinsics start with "llvm.hexagon.". 16let TargetPrefix = "hexagon" in { 17 /// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics. 18 class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types, 19 list<LLVMType> param_types, 20 list<IntrinsicProperty> properties> 21 : GCCBuiltin<!strconcat("__builtin_", GCCIntSuffix)>, 22 Intrinsic<ret_types, param_types, properties>; 23 24 /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon 25 /// intrinsics. 26 class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types, 27 list<LLVMType> param_types, 28 list<IntrinsicProperty> properties> 29 : Intrinsic<ret_types, param_types, properties>; 30} 31 32class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix> 33 : Hexagon_Intrinsic<GCCIntSuffix, 34 [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty, 35 llvm_i32_ty], 36 [IntrArgMemOnly]>; 37 38class Hexagon_mem_memsisi_Intrinsic<string GCCIntSuffix> 39 : Hexagon_Intrinsic<GCCIntSuffix, 40 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, 41 llvm_i32_ty], 42 [IntrWriteMem]>; 43 44class Hexagon_mem_memdisi_Intrinsic<string GCCIntSuffix> 45 : Hexagon_Intrinsic<GCCIntSuffix, 46 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty, 47 llvm_i32_ty], 48 [IntrWriteMem]>; 49 50class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix> 51 : Hexagon_Intrinsic<GCCIntSuffix, 52 [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty, 53 llvm_i32_ty, llvm_i32_ty], 54 [IntrArgMemOnly, ImmArg<3>]>; 55 56class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix> 57 : Hexagon_Intrinsic<GCCIntSuffix, 58 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, 59 llvm_i32_ty, llvm_i32_ty], 60 [IntrWriteMem, ImmArg<3>]>; 61 62class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix> 63 : Hexagon_Intrinsic<GCCIntSuffix, 64 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty, 65 llvm_i32_ty, llvm_i32_ty], 66 [IntrWriteMem, ImmArg<3>]>; 67 68// 69// BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4) 70// 71def int_hexagon_circ_ldd : 72Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">; 73// 74// BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4) 75// 76def int_hexagon_circ_ldw : 77Hexagon_mem_memmemsisi_Intrinsic<"circ_ldw">; 78// 79// BUILTIN_INFO_NONCONST(circ_ldh,PTR_ftype_PTRPTRSISI,4) 80// 81def int_hexagon_circ_ldh : 82Hexagon_mem_memmemsisi_Intrinsic<"circ_ldh">; 83// 84// BUILTIN_INFO_NONCONST(circ_lduh,PTR_ftype_PTRPTRSISI,4) 85// 86def int_hexagon_circ_lduh : 87Hexagon_mem_memmemsisi_Intrinsic<"circ_lduh">; 88// 89// BUILTIN_INFO_NONCONST(circ_ldb,PTR_ftype_PTRPTRSISI,4) 90// 91def int_hexagon_circ_ldb : 92Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">; 93// 94// BUILTIN_INFO_NONCONST(circ_ldub,PTR_ftype_PTRPTRSISI,4) 95// 96def int_hexagon_circ_ldub : 97Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">; 98 99// 100// BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4) 101// 102def int_hexagon_circ_std : 103Hexagon_mem_memdisisi_Intrinsic<"circ_std">; 104// 105// BUILTIN_INFO_NONCONST(circ_stw,PTR_ftype_PTRSISISI,4) 106// 107def int_hexagon_circ_stw : 108Hexagon_mem_memsisisi_Intrinsic<"circ_stw">; 109// 110// BUILTIN_INFO_NONCONST(circ_sth,PTR_ftype_PTRSISISI,4) 111// 112def int_hexagon_circ_sth : 113Hexagon_mem_memsisisi_Intrinsic<"circ_sth">; 114// 115// BUILTIN_INFO_NONCONST(circ_sthhi,PTR_ftype_PTRSISISI,4) 116// 117def int_hexagon_circ_sthhi : 118Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">; 119// 120// BUILTIN_INFO_NONCONST(circ_stb,PTR_ftype_PTRSISISI,4) 121// 122def int_hexagon_circ_stb : 123Hexagon_mem_memsisisi_Intrinsic<"circ_stb">; 124 125// 126// BUILTIN_INFO(HEXAGON.dcfetch_A,v_ftype_DI*,1) 127// 128def int_hexagon_prefetch : 129Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>; 130def int_hexagon_Y2_dccleana : 131Hexagon_Intrinsic<"HEXAGON_Y2_dccleana", [], [llvm_ptr_ty], []>; 132def int_hexagon_Y2_dccleaninva : 133Hexagon_Intrinsic<"HEXAGON_Y2_dccleaninva", [], [llvm_ptr_ty], []>; 134def int_hexagon_Y2_dcinva : 135Hexagon_Intrinsic<"HEXAGON_Y2_dcinva", [], [llvm_ptr_ty], []>; 136def int_hexagon_Y2_dczeroa : 137Hexagon_Intrinsic<"HEXAGON_Y2_dczeroa", [], [llvm_ptr_ty], 138 [IntrWriteMem, IntrArgMemOnly, IntrHasSideEffects]>; 139def int_hexagon_Y4_l2fetch : 140Hexagon_Intrinsic<"HEXAGON_Y4_l2fetch", [], [llvm_ptr_ty, llvm_i32_ty], []>; 141def int_hexagon_Y5_l2fetch : 142Hexagon_Intrinsic<"HEXAGON_Y5_l2fetch", [], [llvm_ptr_ty, llvm_i64_ty], []>; 143 144def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>; 145def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>; 146 147// Mark locked loads as read/write to prevent any accidental reordering. 148def int_hexagon_L2_loadw_locked : 149Hexagon_Intrinsic<"HEXAGON_L2_loadw_locked", [llvm_i32_ty], [llvm_ptr32_ty], 150 [IntrArgMemOnly, NoCapture<0>]>; 151def int_hexagon_L4_loadd_locked : 152Hexagon_Intrinsic<"HEXAGON_L4_loadd_locked", [llvm_i64_ty], [llvm_ptr64_ty], 153 [IntrArgMemOnly, NoCapture<0>]>; 154 155def int_hexagon_S2_storew_locked : 156Hexagon_Intrinsic<"HEXAGON_S2_storew_locked", [llvm_i32_ty], 157 [llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<0>]>; 158def int_hexagon_S4_stored_locked : 159Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty], 160 [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<0>]>; 161 162def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy", 163 [], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], 164 [IntrArgMemOnly, NoCapture<0>, NoCapture<1>, WriteOnly<0>, ReadOnly<1>]>; 165 166def int_hexagon_vmemset : Hexagon_Intrinsic<"hexagon_vmemset", 167 [], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 168 [IntrArgMemOnly, NoCapture<0>, WriteOnly<0>]>; 169 170multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> { 171 def NAME#_pci : Hexagon_NonGCC_Intrinsic< 172 [ElTy, llvm_ptr_ty], 173 [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], 174 [IntrArgMemOnly, NoCapture<3>]>; 175 def NAME#_pcr : Hexagon_NonGCC_Intrinsic< 176 [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty], 177 [IntrArgMemOnly, NoCapture<2>]>; 178} 179 180defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 181defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 182defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 183defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 184defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 185defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>; 186 187multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> { 188 def NAME#_pci : Hexagon_NonGCC_Intrinsic< 189 [llvm_ptr_ty], 190 [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], 191 [IntrArgMemOnly, NoCapture<4>]>; 192 def NAME#_pcr : Hexagon_NonGCC_Intrinsic< 193 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], 194 [IntrArgMemOnly, NoCapture<3>]>; 195} 196 197defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 198defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 199defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 200defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 201defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>; 202 203// The front-end emits the intrinsic call with only two arguments. The third 204// argument from the builtin is already used by front-end to write to memory 205// by generating a store. 206class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy> 207 : Hexagon_NonGCC_Intrinsic< 208 [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], 209 [IntrReadMem]>; 210 211def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 212def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 213def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 214def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 215def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 216def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>; 217 218def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">; 219def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">; 220def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">; 221def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">; 222def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">; 223 224// 225// Masked vector stores 226// 227 228// 229// Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix> 230// tag: V6_vS32b_qpred_ai 231class Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix> 232 : Hexagon_Intrinsic<GCCIntSuffix, 233 [], [llvm_v512i1_ty,llvm_ptr_ty,llvm_v16i32_ty], 234 [IntrArgMemOnly]>; 235 236// 237// Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix> 238// tag: V6_vS32b_qpred_ai_128B 239class Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix> 240 : Hexagon_Intrinsic<GCCIntSuffix, 241 [], [llvm_v1024i1_ty,llvm_ptr_ty,llvm_v32i32_ty], 242 [IntrArgMemOnly]>; 243 244def int_hexagon_V6_vS32b_qpred_ai : 245Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">; 246 247def int_hexagon_V6_vS32b_nqpred_ai : 248Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">; 249 250def int_hexagon_V6_vS32b_nt_qpred_ai : 251Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">; 252 253def int_hexagon_V6_vS32b_nt_nqpred_ai : 254Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">; 255 256def int_hexagon_V6_vS32b_qpred_ai_128B : 257Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">; 258 259def int_hexagon_V6_vS32b_nqpred_ai_128B : 260Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">; 261 262def int_hexagon_V6_vS32b_nt_qpred_ai_128B : 263Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">; 264 265def int_hexagon_V6_vS32b_nt_nqpred_ai_128B : 266Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">; 267 268def int_hexagon_V6_vmaskedstoreq : 269Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">; 270 271def int_hexagon_V6_vmaskedstorenq : 272Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorenq">; 273 274def int_hexagon_V6_vmaskedstorentq : 275Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentq">; 276 277def int_hexagon_V6_vmaskedstorentnq : 278Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentnq">; 279 280def int_hexagon_V6_vmaskedstoreq_128B : 281Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstoreq_128B">; 282 283def int_hexagon_V6_vmaskedstorenq_128B : 284Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorenq_128B">; 285 286def int_hexagon_V6_vmaskedstorentq_128B : 287Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentq_128B">; 288 289def int_hexagon_V6_vmaskedstorentnq_128B : 290Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentnq_128B">; 291 292class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix> 293 : Hexagon_Intrinsic<GCCIntSuffix, 294 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, 295 llvm_v16i32_ty], 296 [IntrArgMemOnly]>; 297 298class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix> 299 : Hexagon_Intrinsic<GCCIntSuffix, 300 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, 301 llvm_v32i32_ty], 302 [IntrArgMemOnly]>; 303 304class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix> 305 : Hexagon_Intrinsic<GCCIntSuffix, 306 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, 307 llvm_v64i32_ty], 308 [IntrArgMemOnly]>; 309 310class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix> 311 : Hexagon_Intrinsic<GCCIntSuffix, 312 [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty, 313 llvm_i32_ty,llvm_v16i32_ty], 314 [IntrArgMemOnly]>; 315 316class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix> 317 : Hexagon_Intrinsic<GCCIntSuffix, 318 [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty, 319 llvm_i32_ty,llvm_v32i32_ty], 320 [IntrArgMemOnly]>; 321 322class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix> 323 : Hexagon_Intrinsic<GCCIntSuffix, 324 [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty, 325 llvm_i32_ty,llvm_v32i32_ty], 326 [IntrArgMemOnly]>; 327 328class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix> 329 : Hexagon_Intrinsic<GCCIntSuffix, 330 [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty, 331 llvm_i32_ty,llvm_v64i32_ty], 332 [IntrArgMemOnly]>; 333 334def int_hexagon_V6_vgathermw : 335Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">; 336 337def int_hexagon_V6_vgathermw_128B : 338Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">; 339 340def int_hexagon_V6_vgathermh : 341Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">; 342 343def int_hexagon_V6_vgathermh_128B : 344Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">; 345 346def int_hexagon_V6_vgathermhw : 347Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">; 348 349def int_hexagon_V6_vgathermhw_128B : 350Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">; 351 352def int_hexagon_V6_vgathermwq : 353Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">; 354 355def int_hexagon_V6_vgathermwq_128B : 356Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">; 357 358def int_hexagon_V6_vgathermhq : 359Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">; 360 361def int_hexagon_V6_vgathermhq_128B : 362Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">; 363 364def int_hexagon_V6_vgathermhwq : 365Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">; 366 367def int_hexagon_V6_vgathermhwq_128B : 368Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">; 369 370class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix> 371 : Hexagon_Intrinsic<GCCIntSuffix, 372 [], [llvm_i32_ty,llvm_i32_ty, 373 llvm_v16i32_ty,llvm_v16i32_ty], 374 [IntrWriteMem]>; 375 376class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix> 377 : Hexagon_Intrinsic<GCCIntSuffix, 378 [], [llvm_i32_ty,llvm_i32_ty, 379 llvm_v32i32_ty,llvm_v32i32_ty], 380 [IntrWriteMem]>; 381 382class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix> 383 : Hexagon_Intrinsic<GCCIntSuffix, 384 [], [llvm_v512i1_ty,llvm_i32_ty, 385 llvm_i32_ty,llvm_v16i32_ty, 386 llvm_v16i32_ty], 387 [IntrWriteMem]>; 388 389class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix> 390 : Hexagon_Intrinsic<GCCIntSuffix, 391 [], [llvm_v1024i1_ty,llvm_i32_ty, 392 llvm_i32_ty,llvm_v32i32_ty, 393 llvm_v32i32_ty], 394 [IntrWriteMem]>; 395 396class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix> 397 : Hexagon_Intrinsic<GCCIntSuffix, 398 [], [llvm_i32_ty,llvm_i32_ty, 399 llvm_v32i32_ty,llvm_v16i32_ty], 400 [IntrWriteMem]>; 401 402class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix> 403 : Hexagon_Intrinsic<GCCIntSuffix, 404 [], [llvm_i32_ty,llvm_i32_ty, 405 llvm_v64i32_ty,llvm_v32i32_ty], 406 [IntrWriteMem]>; 407 408class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix> 409 : Hexagon_Intrinsic<GCCIntSuffix, 410 [], [llvm_v512i1_ty,llvm_i32_ty, 411 llvm_i32_ty,llvm_v32i32_ty, 412 llvm_v16i32_ty], 413 [IntrWriteMem]>; 414 415class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix> 416 : Hexagon_Intrinsic<GCCIntSuffix, 417 [], [llvm_v1024i1_ty,llvm_i32_ty, 418 llvm_i32_ty,llvm_v64i32_ty, 419 llvm_v32i32_ty], 420 [IntrWriteMem]>; 421 422class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix> 423 : Hexagon_Intrinsic<GCCIntSuffix, 424 [llvm_v64i32_ty], [], 425 [IntrNoMem]>; 426 427// 428// BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4) 429// tag : V6_vscattermw 430def int_hexagon_V6_vscattermw : 431Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">; 432 433// 434// BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4) 435// tag : V6_vscattermw_128B 436def int_hexagon_V6_vscattermw_128B : 437Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">; 438 439// 440// BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4) 441// tag : V6_vscattermh 442def int_hexagon_V6_vscattermh : 443Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">; 444 445// 446// BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4) 447// tag : V6_vscattermh_128B 448def int_hexagon_V6_vscattermh_128B : 449Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">; 450 451// 452// BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4) 453// tag : V6_vscattermw_add 454def int_hexagon_V6_vscattermw_add : 455Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">; 456 457// 458// BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4) 459// tag : V6_vscattermw_add_128B 460def int_hexagon_V6_vscattermw_add_128B : 461Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">; 462 463// 464// BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4) 465// tag : V6_vscattermh_add 466def int_hexagon_V6_vscattermh_add : 467Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">; 468 469// 470// BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4) 471// tag : V6_vscattermh_add_128B 472def int_hexagon_V6_vscattermh_add_128B : 473Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">; 474 475// 476// BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5) 477// tag : V6_vscattermwq 478def int_hexagon_V6_vscattermwq : 479Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">; 480 481// 482// BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5) 483// tag : V6_vscattermwq_128B 484def int_hexagon_V6_vscattermwq_128B : 485Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">; 486 487// 488// BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5) 489// tag : V6_vscattermhq 490def int_hexagon_V6_vscattermhq : 491Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">; 492 493// 494// BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5) 495// tag : V6_vscattermhq_128B 496def int_hexagon_V6_vscattermhq_128B : 497Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">; 498 499// 500// BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4) 501// tag : V6_vscattermhw 502def int_hexagon_V6_vscattermhw : 503Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">; 504 505// 506// BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4) 507// tag : V6_vscattermhw_128B 508def int_hexagon_V6_vscattermhw_128B : 509Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">; 510 511// 512// BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5) 513// tag : V6_vscattermhwq 514def int_hexagon_V6_vscattermhwq : 515Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">; 516 517// 518// BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5) 519// tag : V6_vscattermhwq_128B 520def int_hexagon_V6_vscattermhwq_128B : 521Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">; 522 523// 524// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4) 525// tag : V6_vscattermhw_add 526def int_hexagon_V6_vscattermhw_add : 527Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">; 528 529// 530// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4) 531// tag : V6_vscattermhw_add_128B 532def int_hexagon_V6_vscattermhw_add_128B : 533Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">; 534 535// Auto-generated intrinsics 536 537// tag : S2_vsatwh 538class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix> 539 : Hexagon_Intrinsic<GCCIntSuffix, 540 [llvm_i32_ty], [llvm_i64_ty], 541 [IntrNoMem]>; 542 543// tag : V6_vrmpybusv 544class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix> 545 : Hexagon_Intrinsic<GCCIntSuffix, 546 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 547 [IntrNoMem]>; 548 549// tag : V6_vrmpybusv 550class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix> 551 : Hexagon_Intrinsic<GCCIntSuffix, 552 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 553 [IntrNoMem]>; 554 555// tag : V6_vaslw_acc 556class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 557 list<IntrinsicProperty> intr_properties = []> 558 : Hexagon_Intrinsic<GCCIntSuffix, 559 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 560 !listconcat([IntrNoMem], intr_properties)>; 561 562// tag : V6_vaslw_acc 563class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 564 list<IntrinsicProperty> intr_properties = []> 565 : Hexagon_Intrinsic<GCCIntSuffix, 566 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 567 !listconcat([IntrNoMem], intr_properties)>; 568 569// tag : V6_vmux 570class Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix> 571 : Hexagon_Intrinsic<GCCIntSuffix, 572 [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 573 [IntrNoMem]>; 574 575// tag : V6_vmux 576class Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix> 577 : Hexagon_Intrinsic<GCCIntSuffix, 578 [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 579 [IntrNoMem]>; 580 581// tag : S2_tableidxd_goodsyntax 582class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix> 583 : Hexagon_Intrinsic<GCCIntSuffix, 584 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], 585 [IntrNoMem, ImmArg<2>, ImmArg<3>]>; 586 587// tag : V6_vandnqrt_acc 588class Hexagon_v16i32_v16i32v512i1i32_Intrinsic<string GCCIntSuffix> 589 : Hexagon_Intrinsic<GCCIntSuffix, 590 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty], 591 [IntrNoMem]>; 592 593// tag : V6_vandnqrt_acc 594class Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<string GCCIntSuffix> 595 : Hexagon_Intrinsic<GCCIntSuffix, 596 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty], 597 [IntrNoMem]>; 598 599// tag : V6_vrmpybusi 600class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix, 601 list<IntrinsicProperty> intr_properties = []> 602 : Hexagon_Intrinsic<GCCIntSuffix, 603 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], 604 !listconcat([IntrNoMem], intr_properties)>; 605 606// tag : V6_vrmpybusi 607class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix, 608 list<IntrinsicProperty> intr_properties = []> 609 : Hexagon_Intrinsic<GCCIntSuffix, 610 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], 611 !listconcat([IntrNoMem], intr_properties)>; 612 613// tag : V6_vsubb_dv 614class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []> 615 : Hexagon_Intrinsic<GCCIntSuffix, 616 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty], 617 !listconcat([IntrNoMem], intr_properties)>; 618 619// tag : M2_mpysu_up 620class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix, 621 list<IntrinsicProperty> intr_properties = []> 622 : Hexagon_Intrinsic<GCCIntSuffix, 623 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty], 624 !listconcat([IntrNoMem], intr_properties)>; 625 626// tag : M2_mpyud_acc_ll_s0 627class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []> 628 : Hexagon_Intrinsic<GCCIntSuffix, 629 [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], 630 !listconcat([IntrNoMem], intr_properties)>; 631 632// tag : S2_lsr_i_r_nac 633class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix, 634 list<IntrinsicProperty> intr_properties = []> 635 : Hexagon_Intrinsic<GCCIntSuffix, 636 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], 637 !listconcat([IntrNoMem], intr_properties)>; 638 639// tag : M2_cmpysc_s0 640class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []> 641 : Hexagon_Intrinsic<GCCIntSuffix, 642 [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty], 643 !listconcat([IntrNoMem], intr_properties)>; 644 645// tag : V6_lo 646class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []> 647 : Hexagon_Intrinsic<GCCIntSuffix, 648 [llvm_v16i32_ty], [llvm_v32i32_ty], 649 !listconcat([IntrNoMem], intr_properties)>; 650 651// tag : V6_lo 652class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []> 653 : Hexagon_Intrinsic<GCCIntSuffix, 654 [llvm_v32i32_ty], [llvm_v64i32_ty], 655 !listconcat([IntrNoMem], intr_properties)>; 656 657// tag : S2_shuffoh 658class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix> 659 : Hexagon_Intrinsic<GCCIntSuffix, 660 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty], 661 [IntrNoMem]>; 662 663// tag : F2_sfmax 664class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix> 665 : Hexagon_Intrinsic<GCCIntSuffix, 666 [llvm_float_ty], [llvm_float_ty,llvm_float_ty], 667 [IntrNoMem, Throws]>; 668 669// tag : A2_vabswsat 670class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix> 671 : Hexagon_Intrinsic<GCCIntSuffix, 672 [llvm_i64_ty], [llvm_i64_ty], 673 [IntrNoMem]>; 674 675// tag : 676class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix> 677 : Hexagon_Intrinsic<GCCIntSuffix, 678 [llvm_v32i32_ty], [llvm_v32i32_ty], 679 [IntrNoMem]>; 680 681// tag : V6_ldnp0 682class Hexagon_v16i32_i32i32_Intrinsic<string GCCIntSuffix> 683 : Hexagon_Intrinsic<GCCIntSuffix, 684 [llvm_v16i32_ty], [llvm_i32_ty,llvm_i32_ty], 685 [IntrNoMem]>; 686 687// tag : V6_ldnp0 688class Hexagon_v32i32_i32i32_Intrinsic<string GCCIntSuffix> 689 : Hexagon_Intrinsic<GCCIntSuffix, 690 [llvm_v32i32_ty], [llvm_i32_ty,llvm_i32_ty], 691 [IntrNoMem]>; 692 693// tag : V6_vdmpyhb 694class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix> 695 : Hexagon_Intrinsic<GCCIntSuffix, 696 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 697 [IntrNoMem]>; 698 699// tag : V6_vdmpyhb 700class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix> 701 : Hexagon_Intrinsic<GCCIntSuffix, 702 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 703 [IntrNoMem]>; 704 705// tag : A4_vcmphgti 706class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []> 707 : Hexagon_Intrinsic<GCCIntSuffix, 708 [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty], 709 !listconcat([IntrNoMem], intr_properties)>; 710 711// tag : 712class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix> 713 : Hexagon_Intrinsic<GCCIntSuffix, 714 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 715 [IntrNoMem]>; 716 717// tag : S6_rol_i_p_or 718class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix, 719 list<IntrinsicProperty> intr_properties = []> 720 : Hexagon_Intrinsic<GCCIntSuffix, 721 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty], 722 !listconcat([IntrNoMem], intr_properties)>; 723 724// tag : V6_vgtuh_and 725class Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix> 726 : Hexagon_Intrinsic<GCCIntSuffix, 727 [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 728 [IntrNoMem]>; 729 730// tag : V6_vgtuh_and 731class Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix> 732 : Hexagon_Intrinsic<GCCIntSuffix, 733 [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 734 [IntrNoMem]>; 735 736// tag : A2_abssat 737class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix, 738 list<IntrinsicProperty> intr_properties = []> 739 : Hexagon_Intrinsic<GCCIntSuffix, 740 [llvm_i32_ty], [llvm_i32_ty], 741 !listconcat([IntrNoMem], intr_properties)>; 742 743// tag : A2_vcmpwgtu 744class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix, 745 list<IntrinsicProperty> intr_properties = []> 746 : Hexagon_Intrinsic<GCCIntSuffix, 747 [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty], 748 !listconcat([IntrNoMem], intr_properties)>; 749 750// tag : V6_vtmpybus_acc 751class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix> 752 : Hexagon_Intrinsic<GCCIntSuffix, 753 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], 754 [IntrNoMem]>; 755 756// tag : F2_conv_df2uw_chop 757class Hexagon_i32_double_Intrinsic<string GCCIntSuffix> 758 : Hexagon_Intrinsic<GCCIntSuffix, 759 [llvm_i32_ty], [llvm_double_ty], 760 [IntrNoMem]>; 761 762// tag : V6_pred_or 763class Hexagon_v512i1_v512i1v512i1_Intrinsic<string GCCIntSuffix> 764 : Hexagon_Intrinsic<GCCIntSuffix, 765 [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty], 766 [IntrNoMem]>; 767 768// tag : V6_pred_or 769class Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<string GCCIntSuffix> 770 : Hexagon_Intrinsic<GCCIntSuffix, 771 [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty], 772 [IntrNoMem]>; 773 774// tag : S2_asr_i_p_rnd_goodsyntax 775class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix, 776 list<IntrinsicProperty> intr_properties = []> 777 : Hexagon_Intrinsic<GCCIntSuffix, 778 [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty], 779 !listconcat([IntrNoMem], intr_properties)>; 780 781// tag : F2_conv_w2df 782class Hexagon_double_i32_Intrinsic<string GCCIntSuffix, 783 list<IntrinsicProperty> intr_properties = []> 784 : Hexagon_Intrinsic<GCCIntSuffix, 785 [llvm_double_ty], [llvm_i32_ty], 786 !listconcat([IntrNoMem], intr_properties)>; 787 788// tag : V6_vunpackuh 789class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix> 790 : Hexagon_Intrinsic<GCCIntSuffix, 791 [llvm_v32i32_ty], [llvm_v16i32_ty], 792 [IntrNoMem]>; 793 794// tag : V6_vunpackuh 795class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix> 796 : Hexagon_Intrinsic<GCCIntSuffix, 797 [llvm_v64i32_ty], [llvm_v32i32_ty], 798 [IntrNoMem]>; 799 800// tag : V6_vadduhw_acc 801class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix> 802 : Hexagon_Intrinsic<GCCIntSuffix, 803 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 804 [IntrNoMem]>; 805 806// tag : V6_vadduhw_acc 807class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix> 808 : Hexagon_Intrinsic<GCCIntSuffix, 809 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 810 [IntrNoMem]>; 811 812// tag : M2_vdmacs_s0 813class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix> 814 : Hexagon_Intrinsic<GCCIntSuffix, 815 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty], 816 [IntrNoMem]>; 817 818// tag : V6_vrmpybub_rtt_acc 819class Hexagon_v32i32_v32i32v16i32i64_Intrinsic<string GCCIntSuffix> 820 : Hexagon_Intrinsic<GCCIntSuffix, 821 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty], 822 [IntrNoMem]>; 823 824// tag : V6_vrmpybub_rtt_acc 825class Hexagon_v64i32_v64i32v32i32i64_Intrinsic<string GCCIntSuffix> 826 : Hexagon_Intrinsic<GCCIntSuffix, 827 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty], 828 [IntrNoMem]>; 829 830// tag : V6_ldu0 831class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix> 832 : Hexagon_Intrinsic<GCCIntSuffix, 833 [llvm_v16i32_ty], [llvm_i32_ty], 834 [IntrNoMem]>; 835 836// tag : V6_ldu0 837class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix> 838 : Hexagon_Intrinsic<GCCIntSuffix, 839 [llvm_v32i32_ty], [llvm_i32_ty], 840 [IntrNoMem]>; 841 842// tag : S4_extract_rp 843class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix> 844 : Hexagon_Intrinsic<GCCIntSuffix, 845 [llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty], 846 [IntrNoMem]>; 847 848// tag : V6_vdmpyhsuisat 849class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix> 850 : Hexagon_Intrinsic<GCCIntSuffix, 851 [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 852 [IntrNoMem]>; 853 854// tag : V6_vdmpyhsuisat 855class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix> 856 : Hexagon_Intrinsic<GCCIntSuffix, 857 [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty], 858 [IntrNoMem]>; 859 860// tag : A2_addsp 861class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix> 862 : Hexagon_Intrinsic<GCCIntSuffix, 863 [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty], 864 [IntrNoMem]>; 865 866// tag : V6_extractw 867class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix> 868 : Hexagon_Intrinsic<GCCIntSuffix, 869 [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 870 [IntrNoMem]>; 871 872// tag : V6_extractw 873class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix> 874 : Hexagon_Intrinsic<GCCIntSuffix, 875 [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 876 [IntrNoMem]>; 877 878// tag : V6_vlutvwhi 879class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 880 list<IntrinsicProperty> intr_properties = []> 881 : Hexagon_Intrinsic<GCCIntSuffix, 882 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 883 !listconcat([IntrNoMem], intr_properties)>; 884 885// tag : V6_vlutvwhi 886class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 887 list<IntrinsicProperty> intr_properties = []> 888 : Hexagon_Intrinsic<GCCIntSuffix, 889 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 890 !listconcat([IntrNoMem], intr_properties)>; 891 892// tag : V6_vgtuh 893class Hexagon_v512i1_v16i32v16i32_Intrinsic<string GCCIntSuffix> 894 : Hexagon_Intrinsic<GCCIntSuffix, 895 [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 896 [IntrNoMem]>; 897 898// tag : V6_vgtuh 899class Hexagon_v1024i1_v32i32v32i32_Intrinsic<string GCCIntSuffix> 900 : Hexagon_Intrinsic<GCCIntSuffix, 901 [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 902 [IntrNoMem]>; 903 904// tag : F2_sffma_lib 905class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix> 906 : Hexagon_Intrinsic<GCCIntSuffix, 907 [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty], 908 [IntrNoMem, Throws]>; 909 910// tag : F2_conv_ud2df 911class Hexagon_double_i64_Intrinsic<string GCCIntSuffix> 912 : Hexagon_Intrinsic<GCCIntSuffix, 913 [llvm_double_ty], [llvm_i64_ty], 914 [IntrNoMem]>; 915 916// tag : S2_vzxthw 917class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix, 918 list<IntrinsicProperty> intr_properties = []> 919 : Hexagon_Intrinsic<GCCIntSuffix, 920 [llvm_i64_ty], [llvm_i32_ty], 921 !listconcat([IntrNoMem], intr_properties)>; 922 923// tag : V6_vtmpyhb 924class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix> 925 : Hexagon_Intrinsic<GCCIntSuffix, 926 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty], 927 [IntrNoMem]>; 928 929// tag : V6_vshufoeh 930class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix> 931 : Hexagon_Intrinsic<GCCIntSuffix, 932 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 933 [IntrNoMem]>; 934 935// tag : V6_vshufoeh 936class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix> 937 : Hexagon_Intrinsic<GCCIntSuffix, 938 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 939 [IntrNoMem]>; 940 941// tag : V6_vlut4 942class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix> 943 : Hexagon_Intrinsic<GCCIntSuffix, 944 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty], 945 [IntrNoMem]>; 946 947// tag : V6_vlut4 948class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix> 949 : Hexagon_Intrinsic<GCCIntSuffix, 950 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty], 951 [IntrNoMem]>; 952 953// tag : 954class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix> 955 : Hexagon_Intrinsic<GCCIntSuffix, 956 [llvm_v16i32_ty], [llvm_v16i32_ty], 957 [IntrNoMem]>; 958 959// tag : F2_conv_uw2sf 960class Hexagon_float_i32_Intrinsic<string GCCIntSuffix, 961 list<IntrinsicProperty> intr_properties = []> 962 : Hexagon_Intrinsic<GCCIntSuffix, 963 [llvm_float_ty], [llvm_i32_ty], 964 !listconcat([IntrNoMem], intr_properties)>; 965 966// tag : V6_vswap 967class Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix> 968 : Hexagon_Intrinsic<GCCIntSuffix, 969 [llvm_v32i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 970 [IntrNoMem]>; 971 972// tag : V6_vswap 973class Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix> 974 : Hexagon_Intrinsic<GCCIntSuffix, 975 [llvm_v64i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 976 [IntrNoMem]>; 977 978// tag : V6_vandnqrt 979class Hexagon_v16i32_v512i1i32_Intrinsic<string GCCIntSuffix> 980 : Hexagon_Intrinsic<GCCIntSuffix, 981 [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty], 982 [IntrNoMem]>; 983 984// tag : V6_vandnqrt 985class Hexagon_v32i32_v1024i1i32_Intrinsic<string GCCIntSuffix> 986 : Hexagon_Intrinsic<GCCIntSuffix, 987 [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty], 988 [IntrNoMem]>; 989 990// tag : V6_vmpyub 991class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix> 992 : Hexagon_Intrinsic<GCCIntSuffix, 993 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 994 [IntrNoMem]>; 995 996// tag : A5_ACS 997class Hexagon_i64i32_i64i64i64_Intrinsic<string GCCIntSuffix> 998 : Hexagon_Intrinsic<GCCIntSuffix, 999 [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty], 1000 [IntrNoMem]>; 1001 1002// tag : V6_vunpackob 1003class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix> 1004 : Hexagon_Intrinsic<GCCIntSuffix, 1005 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty], 1006 [IntrNoMem]>; 1007 1008// tag : V6_vunpackob 1009class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix> 1010 : Hexagon_Intrinsic<GCCIntSuffix, 1011 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty], 1012 [IntrNoMem]>; 1013 1014// tag : V6_vmpyhsat_acc 1015class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix> 1016 : Hexagon_Intrinsic<GCCIntSuffix, 1017 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty], 1018 [IntrNoMem]>; 1019 1020// tag : V6_vmpyhsat_acc 1021class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix> 1022 : Hexagon_Intrinsic<GCCIntSuffix, 1023 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty], 1024 [IntrNoMem]>; 1025 1026// tag : V6_vaddcarrysat 1027class Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<string GCCIntSuffix> 1028 : Hexagon_Intrinsic<GCCIntSuffix, 1029 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty], 1030 [IntrNoMem]>; 1031 1032// tag : V6_vaddcarrysat 1033class Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<string GCCIntSuffix> 1034 : Hexagon_Intrinsic<GCCIntSuffix, 1035 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty], 1036 [IntrNoMem]>; 1037 1038// tag : V6_vlutvvb_oracc 1039class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 1040 list<IntrinsicProperty> intr_properties = []> 1041 : Hexagon_Intrinsic<GCCIntSuffix, 1042 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 1043 !listconcat([IntrNoMem], intr_properties)>; 1044 1045// tag : V6_vlutvvb_oracc 1046class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []> 1047 : Hexagon_Intrinsic<GCCIntSuffix, 1048 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 1049 !listconcat([IntrNoMem], intr_properties)>; 1050 1051// tag : V6_vrmpybub_rtt 1052class Hexagon_v32i32_v16i32i64_Intrinsic<string GCCIntSuffix> 1053 : Hexagon_Intrinsic<GCCIntSuffix, 1054 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty], 1055 [IntrNoMem]>; 1056 1057// tag : V6_vrmpybub_rtt 1058class Hexagon_v64i32_v32i32i64_Intrinsic<string GCCIntSuffix> 1059 : Hexagon_Intrinsic<GCCIntSuffix, 1060 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty], 1061 [IntrNoMem]>; 1062 1063// tag : A4_addp_c 1064class Hexagon_i64i32_i64i64i32_Intrinsic<string GCCIntSuffix> 1065 : Hexagon_Intrinsic<GCCIntSuffix, 1066 [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty], 1067 [IntrNoMem]>; 1068 1069// tag : V6_vrsadubi_acc 1070class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix, 1071 list<IntrinsicProperty> intr_properties = []> 1072 : Hexagon_Intrinsic<GCCIntSuffix, 1073 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], 1074 !listconcat([IntrNoMem], intr_properties)>; 1075 1076// tag : V6_vrsadubi_acc 1077class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix, 1078 list<IntrinsicProperty> intr_properties = []> 1079 : Hexagon_Intrinsic<GCCIntSuffix, 1080 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], 1081 !listconcat([IntrNoMem], intr_properties)>; 1082 1083// tag : F2_conv_df2sf 1084class Hexagon_float_double_Intrinsic<string GCCIntSuffix> 1085 : Hexagon_Intrinsic<GCCIntSuffix, 1086 [llvm_float_ty], [llvm_double_ty], 1087 [IntrNoMem]>; 1088 1089// tag : V6_vandvqv 1090class Hexagon_v16i32_v512i1v16i32_Intrinsic<string GCCIntSuffix> 1091 : Hexagon_Intrinsic<GCCIntSuffix, 1092 [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty], 1093 [IntrNoMem]>; 1094 1095// tag : V6_vandvqv 1096class Hexagon_v32i32_v1024i1v32i32_Intrinsic<string GCCIntSuffix> 1097 : Hexagon_Intrinsic<GCCIntSuffix, 1098 [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty], 1099 [IntrNoMem]>; 1100 1101// tag : C2_vmux 1102class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix> 1103 : Hexagon_Intrinsic<GCCIntSuffix, 1104 [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty], 1105 [IntrNoMem]>; 1106 1107// tag : F2_sfcmpeq 1108class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix> 1109 : Hexagon_Intrinsic<GCCIntSuffix, 1110 [llvm_i32_ty], [llvm_float_ty,llvm_float_ty], 1111 [IntrNoMem, Throws]>; 1112 1113// tag : V6_vmpahhsat 1114class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix> 1115 : Hexagon_Intrinsic<GCCIntSuffix, 1116 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty], 1117 [IntrNoMem]>; 1118 1119// tag : V6_vmpahhsat 1120class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix> 1121 : Hexagon_Intrinsic<GCCIntSuffix, 1122 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty], 1123 [IntrNoMem]>; 1124 1125// tag : V6_vandvrt 1126class Hexagon_v512i1_v16i32i32_Intrinsic<string GCCIntSuffix> 1127 : Hexagon_Intrinsic<GCCIntSuffix, 1128 [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_i32_ty], 1129 [IntrNoMem]>; 1130 1131// tag : V6_vandvrt 1132class Hexagon_v1024i1_v32i32i32_Intrinsic<string GCCIntSuffix> 1133 : Hexagon_Intrinsic<GCCIntSuffix, 1134 [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_i32_ty], 1135 [IntrNoMem]>; 1136 1137// tag : V6_vsubcarry 1138class Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic 1139 : Hexagon_NonGCC_Intrinsic< 1140 [llvm_v16i32_ty,llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty], 1141 [IntrNoMem]>; 1142 1143// tag : V6_vsubcarry 1144class Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B 1145 : Hexagon_NonGCC_Intrinsic< 1146 [llvm_v32i32_ty,llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty], 1147 [IntrNoMem]>; 1148 1149// tag : F2_sffixupr 1150class Hexagon_float_float_Intrinsic<string GCCIntSuffix> 1151 : Hexagon_Intrinsic<GCCIntSuffix, 1152 [llvm_float_ty], [llvm_float_ty], 1153 [IntrNoMem, Throws]>; 1154 1155// tag : V6_vandvrt_acc 1156class Hexagon_v512i1_v512i1v16i32i32_Intrinsic<string GCCIntSuffix> 1157 : Hexagon_Intrinsic<GCCIntSuffix, 1158 [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_i32_ty], 1159 [IntrNoMem]>; 1160 1161// tag : V6_vandvrt_acc 1162class Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<string GCCIntSuffix> 1163 : Hexagon_Intrinsic<GCCIntSuffix, 1164 [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_i32_ty], 1165 [IntrNoMem]>; 1166 1167// tag : F2_dfsub 1168class Hexagon_double_doubledouble_Intrinsic<string GCCIntSuffix> 1169 : Hexagon_Intrinsic<GCCIntSuffix, 1170 [llvm_double_ty], [llvm_double_ty,llvm_double_ty], 1171 [IntrNoMem, Throws]>; 1172 1173// tag : V6_vmpyowh_sacc 1174class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix> 1175 : Hexagon_Intrinsic<GCCIntSuffix, 1176 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 1177 [IntrNoMem]>; 1178 1179// tag : V6_vmpyowh_sacc 1180class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix> 1181 : Hexagon_Intrinsic<GCCIntSuffix, 1182 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 1183 [IntrNoMem]>; 1184 1185// tag : S2_insertp 1186class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix, 1187 list<IntrinsicProperty> intr_properties = []> 1188 : Hexagon_Intrinsic<GCCIntSuffix, 1189 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], 1190 !listconcat([IntrNoMem], intr_properties)>; 1191 1192// tag : F2_sfinvsqrta 1193class Hexagon_floati32_float_Intrinsic<string GCCIntSuffix> 1194 : Hexagon_Intrinsic<GCCIntSuffix, 1195 [llvm_float_ty,llvm_i32_ty], [llvm_float_ty], 1196 [IntrNoMem, Throws]>; 1197 1198// tag : V6_vtran2x2_map 1199class Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix> 1200 : Hexagon_Intrinsic<GCCIntSuffix, 1201 [llvm_v16i32_ty,llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 1202 [IntrNoMem]>; 1203 1204// tag : V6_vtran2x2_map 1205class Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix> 1206 : Hexagon_Intrinsic<GCCIntSuffix, 1207 [llvm_v32i32_ty,llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 1208 [IntrNoMem]>; 1209 1210// tag : V6_vlutvwh_oracc 1211class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 1212 list<IntrinsicProperty> intr_properties = []> 1213 : Hexagon_Intrinsic<GCCIntSuffix, 1214 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 1215 !listconcat([IntrNoMem], intr_properties)>; 1216 1217// tag : V6_vlutvwh_oracc 1218class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 1219 list<IntrinsicProperty> intr_properties = []> 1220 : Hexagon_Intrinsic<GCCIntSuffix, 1221 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 1222 !listconcat([IntrNoMem], intr_properties)>; 1223 1224// tag : F2_dfcmpge 1225class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix> 1226 : Hexagon_Intrinsic<GCCIntSuffix, 1227 [llvm_i32_ty], [llvm_double_ty,llvm_double_ty], 1228 [IntrNoMem, Throws]>; 1229 1230// tag : F2_conv_df2d_chop 1231class Hexagon_i64_double_Intrinsic<string GCCIntSuffix> 1232 : Hexagon_Intrinsic<GCCIntSuffix, 1233 [llvm_i64_ty], [llvm_double_ty], 1234 [IntrNoMem]>; 1235 1236// tag : F2_conv_sf2w 1237class Hexagon_i32_float_Intrinsic<string GCCIntSuffix> 1238 : Hexagon_Intrinsic<GCCIntSuffix, 1239 [llvm_i32_ty], [llvm_float_ty], 1240 [IntrNoMem]>; 1241 1242// tag : F2_sfclass 1243class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix> 1244 : Hexagon_Intrinsic<GCCIntSuffix, 1245 [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty], 1246 [IntrNoMem, Throws, ImmArg<1>]>; 1247 1248// tag : F2_conv_sf2ud_chop 1249class Hexagon_i64_float_Intrinsic<string GCCIntSuffix> 1250 : Hexagon_Intrinsic<GCCIntSuffix, 1251 [llvm_i64_ty], [llvm_float_ty], 1252 [IntrNoMem]>; 1253 1254// tag : V6_pred_scalar2v2 1255class Hexagon_v512i1_i32_Intrinsic<string GCCIntSuffix> 1256 : Hexagon_Intrinsic<GCCIntSuffix, 1257 [llvm_v512i1_ty], [llvm_i32_ty], 1258 [IntrNoMem]>; 1259 1260// tag : V6_pred_scalar2v2 1261class Hexagon_v1024i1_i32_Intrinsic<string GCCIntSuffix> 1262 : Hexagon_Intrinsic<GCCIntSuffix, 1263 [llvm_v1024i1_ty], [llvm_i32_ty], 1264 [IntrNoMem]>; 1265 1266// tag : F2_sfrecipa 1267class Hexagon_floati32_floatfloat_Intrinsic<string GCCIntSuffix> 1268 : Hexagon_Intrinsic<GCCIntSuffix, 1269 [llvm_float_ty,llvm_i32_ty], [llvm_float_ty,llvm_float_ty], 1270 [IntrNoMem, Throws]>; 1271 1272// tag : V6_vprefixqh 1273class Hexagon_v16i32_v512i1_Intrinsic<string GCCIntSuffix> 1274 : Hexagon_Intrinsic<GCCIntSuffix, 1275 [llvm_v16i32_ty], [llvm_v512i1_ty], 1276 [IntrNoMem]>; 1277 1278// tag : V6_vprefixqh 1279class Hexagon_v32i32_v1024i1_Intrinsic<string GCCIntSuffix> 1280 : Hexagon_Intrinsic<GCCIntSuffix, 1281 [llvm_v32i32_ty], [llvm_v1024i1_ty], 1282 [IntrNoMem]>; 1283 1284// tag : V6_vdmpyhisat_acc 1285class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix> 1286 : Hexagon_Intrinsic<GCCIntSuffix, 1287 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty], 1288 [IntrNoMem]>; 1289 1290// tag : V6_vdmpyhisat_acc 1291class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix> 1292 : Hexagon_Intrinsic<GCCIntSuffix, 1293 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty], 1294 [IntrNoMem]>; 1295 1296// tag : F2_conv_ud2sf 1297class Hexagon_float_i64_Intrinsic<string GCCIntSuffix> 1298 : Hexagon_Intrinsic<GCCIntSuffix, 1299 [llvm_float_ty], [llvm_i64_ty], 1300 [IntrNoMem]>; 1301 1302// tag : F2_conv_sf2df 1303class Hexagon_double_float_Intrinsic<string GCCIntSuffix> 1304 : Hexagon_Intrinsic<GCCIntSuffix, 1305 [llvm_double_ty], [llvm_float_ty], 1306 [IntrNoMem]>; 1307 1308// tag : F2_sffma_sc 1309class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix> 1310 : Hexagon_Intrinsic<GCCIntSuffix, 1311 [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty], 1312 [IntrNoMem, Throws]>; 1313 1314// tag : F2_dfclass 1315class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix, 1316 list<IntrinsicProperty> intr_properties = []> 1317 : Hexagon_Intrinsic<GCCIntSuffix, 1318 [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty], 1319 !listconcat([IntrNoMem, Throws], intr_properties)>; 1320 1321// tag : V6_vd0 1322class Hexagon_v16i32__Intrinsic<string GCCIntSuffix> 1323 : Hexagon_Intrinsic<GCCIntSuffix, 1324 [llvm_v16i32_ty], [], 1325 [IntrNoMem]>; 1326 1327// tag : V6_vd0 1328class Hexagon_v32i32__Intrinsic<string GCCIntSuffix> 1329 : Hexagon_Intrinsic<GCCIntSuffix, 1330 [llvm_v32i32_ty], [], 1331 [IntrNoMem]>; 1332 1333// tag : V6_vdd0 1334class Hexagon_v64i32__Intrinsic<string GCCIntSuffix> 1335 : Hexagon_Intrinsic<GCCIntSuffix, 1336 [llvm_v64i32_ty], [], 1337 [IntrNoMem]>; 1338 1339// tag : S2_insert_rp 1340class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix> 1341 : Hexagon_Intrinsic<GCCIntSuffix, 1342 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty], 1343 [IntrNoMem]>; 1344 1345// tag : V6_vassignp 1346class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix> 1347 : Hexagon_Intrinsic<GCCIntSuffix, 1348 [llvm_v64i32_ty], [llvm_v64i32_ty], 1349 [IntrNoMem]>; 1350 1351// tag : A6_vminub_RdP 1352class Hexagon_i64i32_i64i64_Intrinsic<string GCCIntSuffix> 1353 : Hexagon_Intrinsic<GCCIntSuffix, 1354 [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty], 1355 [IntrNoMem]>; 1356 1357// tag : V6_pred_not 1358class Hexagon_v512i1_v512i1_Intrinsic<string GCCIntSuffix> 1359 : Hexagon_Intrinsic<GCCIntSuffix, 1360 [llvm_v512i1_ty], [llvm_v512i1_ty], 1361 [IntrNoMem]>; 1362 1363// tag : V6_pred_not 1364class Hexagon_v1024i1_v1024i1_Intrinsic<string GCCIntSuffix> 1365 : Hexagon_Intrinsic<GCCIntSuffix, 1366 [llvm_v1024i1_ty], [llvm_v1024i1_ty], 1367 [IntrNoMem]>; 1368 1369// V5 Scalar Instructions. 1370 1371def int_hexagon_S2_asr_r_p_or : 1372Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">; 1373 1374def int_hexagon_S2_vsatwh : 1375Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">; 1376 1377def int_hexagon_S2_tableidxd_goodsyntax : 1378Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax">; 1379 1380def int_hexagon_M2_mpysu_up : 1381Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">; 1382 1383def int_hexagon_M2_mpyud_acc_ll_s0 : 1384Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">; 1385 1386def int_hexagon_M2_mpyud_acc_ll_s1 : 1387Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">; 1388 1389def int_hexagon_M2_cmpysc_s1 : 1390Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">; 1391 1392def int_hexagon_M2_cmpysc_s0 : 1393Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">; 1394 1395def int_hexagon_M4_cmpyi_whc : 1396Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">; 1397 1398def int_hexagon_M2_mpy_sat_rnd_lh_s1 : 1399Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">; 1400 1401def int_hexagon_M2_mpy_sat_rnd_lh_s0 : 1402Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">; 1403 1404def int_hexagon_S2_tableidxb_goodsyntax : 1405Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax">; 1406 1407def int_hexagon_S2_shuffoh : 1408Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">; 1409 1410def int_hexagon_F2_sfmax : 1411Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax">; 1412 1413def int_hexagon_A2_vabswsat : 1414Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">; 1415 1416def int_hexagon_S2_asr_i_r : 1417Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [ImmArg<1>]>; 1418 1419def int_hexagon_S2_asr_i_p : 1420Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [ImmArg<1>]>; 1421 1422def int_hexagon_A4_combineri : 1423Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [ImmArg<1>]>; 1424 1425def int_hexagon_M2_mpy_nac_sat_hl_s1 : 1426Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">; 1427 1428def int_hexagon_M4_vpmpyh_acc : 1429Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">; 1430 1431def int_hexagon_M2_vcmpy_s0_sat_i : 1432Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">; 1433 1434def int_hexagon_A2_notp : 1435Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">; 1436 1437def int_hexagon_M2_mpy_hl_s1 : 1438Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">; 1439 1440def int_hexagon_M2_mpy_hl_s0 : 1441Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">; 1442 1443def int_hexagon_C4_or_and : 1444Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">; 1445 1446def int_hexagon_M2_vmac2s_s0 : 1447Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">; 1448 1449def int_hexagon_M2_vmac2s_s1 : 1450Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">; 1451 1452def int_hexagon_S2_brevp : 1453Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">; 1454 1455def int_hexagon_M4_pmpyw_acc : 1456Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">; 1457 1458def int_hexagon_S2_cl1 : 1459Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">; 1460 1461def int_hexagon_C4_cmplte : 1462Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">; 1463 1464def int_hexagon_M2_mmpyul_s0 : 1465Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">; 1466 1467def int_hexagon_A2_vaddws : 1468Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">; 1469 1470def int_hexagon_A2_maxup : 1471Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">; 1472 1473def int_hexagon_A4_vcmphgti : 1474Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [ImmArg<1>]>; 1475 1476def int_hexagon_S2_interleave : 1477Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">; 1478 1479def int_hexagon_M2_vrcmpyi_s0 : 1480Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">; 1481 1482def int_hexagon_A2_abssat : 1483Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">; 1484 1485def int_hexagon_A2_vcmpwgtu : 1486Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">; 1487 1488def int_hexagon_C2_cmpgtu : 1489Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">; 1490 1491def int_hexagon_C2_cmpgtp : 1492Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">; 1493 1494def int_hexagon_A4_cmphgtui : 1495Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [ImmArg<1>]>; 1496 1497def int_hexagon_C2_cmpgti : 1498Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [ImmArg<1>]>; 1499 1500def int_hexagon_M2_mpyi : 1501Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">; 1502 1503def int_hexagon_F2_conv_df2uw_chop : 1504Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">; 1505 1506def int_hexagon_A4_cmpheq : 1507Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">; 1508 1509def int_hexagon_M2_mpy_lh_s1 : 1510Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">; 1511 1512def int_hexagon_M2_mpy_lh_s0 : 1513Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">; 1514 1515def int_hexagon_S2_lsr_i_r_xacc : 1516Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [ImmArg<2>]>; 1517 1518def int_hexagon_S2_vrcnegh : 1519Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">; 1520 1521def int_hexagon_S2_extractup : 1522Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [ImmArg<1>, ImmArg<2>]>; 1523 1524def int_hexagon_S2_asr_i_p_rnd_goodsyntax : 1525Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [ImmArg<1>]>; 1526 1527def int_hexagon_S4_ntstbit_r : 1528Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">; 1529 1530def int_hexagon_F2_conv_w2sf : 1531Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">; 1532 1533def int_hexagon_C2_not : 1534Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">; 1535 1536def int_hexagon_C2_tfrpr : 1537Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">; 1538 1539def int_hexagon_M2_mpy_ll_s1 : 1540Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">; 1541 1542def int_hexagon_M2_mpy_ll_s0 : 1543Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">; 1544 1545def int_hexagon_A4_cmpbgt : 1546Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">; 1547 1548def int_hexagon_S2_asr_r_r_and : 1549Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">; 1550 1551def int_hexagon_A4_rcmpneqi : 1552Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [ImmArg<1>]>; 1553 1554def int_hexagon_S2_asl_i_r_nac : 1555Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [ImmArg<2>]>; 1556 1557def int_hexagon_M2_subacc : 1558Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">; 1559 1560def int_hexagon_A2_orp : 1561Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">; 1562 1563def int_hexagon_M2_mpyu_up : 1564Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">; 1565 1566def int_hexagon_M2_mpy_acc_sat_lh_s1 : 1567Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">; 1568 1569def int_hexagon_S2_asr_i_vh : 1570Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [ImmArg<1>]>; 1571 1572def int_hexagon_S2_asr_i_vw : 1573Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [ImmArg<1>]>; 1574 1575def int_hexagon_A4_cmpbgtu : 1576Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">; 1577 1578def int_hexagon_A4_vcmpbeq_any : 1579Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">; 1580 1581def int_hexagon_A4_cmpbgti : 1582Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [ImmArg<1>]>; 1583 1584def int_hexagon_M2_mpyd_lh_s1 : 1585Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">; 1586 1587def int_hexagon_S2_asl_r_p_nac : 1588Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">; 1589 1590def int_hexagon_S2_lsr_i_r_nac : 1591Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [ImmArg<2>]>; 1592 1593def int_hexagon_A2_addsp : 1594Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">; 1595 1596def int_hexagon_S4_vxsubaddw : 1597Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">; 1598 1599def int_hexagon_A4_vcmpheqi : 1600Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [ImmArg<1>]>; 1601 1602def int_hexagon_S4_vxsubaddh : 1603Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">; 1604 1605def int_hexagon_M4_pmpyw : 1606Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">; 1607 1608def int_hexagon_S2_vsathb : 1609Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">; 1610 1611def int_hexagon_S2_asr_r_p_and : 1612Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">; 1613 1614def int_hexagon_M2_mpyu_acc_lh_s1 : 1615Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">; 1616 1617def int_hexagon_M2_mpyu_acc_lh_s0 : 1618Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">; 1619 1620def int_hexagon_S2_lsl_r_p_acc : 1621Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">; 1622 1623def int_hexagon_A2_pxorf : 1624Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_A2_pxorf">; 1625 1626def int_hexagon_C2_cmpgei : 1627Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [ImmArg<1>]>; 1628 1629def int_hexagon_A2_vsubub : 1630Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">; 1631 1632def int_hexagon_S2_asl_i_p : 1633Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [ImmArg<1>]>; 1634 1635def int_hexagon_S2_asl_i_r : 1636Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [ImmArg<1>]>; 1637 1638def int_hexagon_A4_vrminuw : 1639Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">; 1640 1641def int_hexagon_F2_sffma : 1642Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma">; 1643 1644def int_hexagon_A2_absp : 1645Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">; 1646 1647def int_hexagon_C2_all8 : 1648Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">; 1649 1650def int_hexagon_A4_vrminuh : 1651Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">; 1652 1653def int_hexagon_F2_sffma_lib : 1654Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib">; 1655 1656def int_hexagon_M4_vrmpyoh_s0 : 1657Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">; 1658 1659def int_hexagon_M4_vrmpyoh_s1 : 1660Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">; 1661 1662def int_hexagon_C2_bitsset : 1663Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">; 1664 1665def int_hexagon_M2_mpysip : 1666Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysip", [ImmArg<1>]>; 1667 1668def int_hexagon_M2_mpysin : 1669Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysin", [ImmArg<1>]>; 1670 1671def int_hexagon_A4_boundscheck : 1672Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">; 1673 1674def int_hexagon_M5_vrmpybuu : 1675Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">; 1676 1677def int_hexagon_C4_fastcorner9 : 1678Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">; 1679 1680def int_hexagon_M2_vrcmpys_s1rp : 1681Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">; 1682 1683def int_hexagon_A2_neg : 1684Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">; 1685 1686def int_hexagon_A2_subsat : 1687Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">; 1688 1689def int_hexagon_S2_asl_r_r : 1690Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">; 1691 1692def int_hexagon_S2_asl_r_p : 1693Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">; 1694 1695def int_hexagon_A2_vnavgh : 1696Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">; 1697 1698def int_hexagon_M2_mpy_nac_sat_hl_s0 : 1699Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">; 1700 1701def int_hexagon_F2_conv_ud2df : 1702Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">; 1703 1704def int_hexagon_A2_vnavgw : 1705Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">; 1706 1707def int_hexagon_S2_asl_i_r_acc : 1708Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [ImmArg<2>]>; 1709 1710def int_hexagon_S4_subi_lsr_ri : 1711Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [ImmArg<0>, ImmArg<2>]>; 1712 1713def int_hexagon_S2_vzxthw : 1714Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">; 1715 1716def int_hexagon_F2_sfadd : 1717Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd">; 1718 1719def int_hexagon_A2_sub : 1720Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">; 1721 1722def int_hexagon_M2_vmac2su_s0 : 1723Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">; 1724 1725def int_hexagon_M2_vmac2su_s1 : 1726Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">; 1727 1728def int_hexagon_M2_dpmpyss_s0 : 1729Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">; 1730 1731def int_hexagon_S2_insert : 1732Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert">; 1733 1734def int_hexagon_S2_packhl : 1735Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">; 1736 1737def int_hexagon_A4_vcmpwgti : 1738Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [ImmArg<1>]>; 1739 1740def int_hexagon_A2_vavguwr : 1741Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">; 1742 1743def int_hexagon_S2_asl_r_r_and : 1744Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">; 1745 1746def int_hexagon_A2_svsubhs : 1747Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">; 1748 1749def int_hexagon_A2_addh_l16_hl : 1750Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">; 1751 1752def int_hexagon_M4_and_and : 1753Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">; 1754 1755def int_hexagon_F2_conv_d2df : 1756Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">; 1757 1758def int_hexagon_C2_cmpgtui : 1759Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [ImmArg<1>]>; 1760 1761def int_hexagon_A2_vconj : 1762Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">; 1763 1764def int_hexagon_S2_lsr_r_vw : 1765Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">; 1766 1767def int_hexagon_S2_lsr_r_vh : 1768Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">; 1769 1770def int_hexagon_A2_subh_l16_hl : 1771Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">; 1772 1773def int_hexagon_S4_vxsubaddhr : 1774Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">; 1775 1776def int_hexagon_S2_clbp : 1777Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">; 1778 1779def int_hexagon_S2_deinterleave : 1780Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">; 1781 1782def int_hexagon_C2_any8 : 1783Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">; 1784 1785def int_hexagon_S2_togglebit_r : 1786Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">; 1787 1788def int_hexagon_S2_togglebit_i : 1789Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [ImmArg<1>]>; 1790 1791def int_hexagon_F2_conv_uw2sf : 1792Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">; 1793 1794def int_hexagon_S2_vsathb_nopack : 1795Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">; 1796 1797def int_hexagon_M2_cmacs_s0 : 1798Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">; 1799 1800def int_hexagon_M2_cmacs_s1 : 1801Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">; 1802 1803def int_hexagon_M2_mpy_sat_hh_s0 : 1804Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">; 1805 1806def int_hexagon_M2_mpy_sat_hh_s1 : 1807Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">; 1808 1809def int_hexagon_M2_mmacuhs_s1 : 1810Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">; 1811 1812def int_hexagon_M2_mmacuhs_s0 : 1813Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">; 1814 1815def int_hexagon_S2_clrbit_r : 1816Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">; 1817 1818def int_hexagon_C4_or_andn : 1819Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">; 1820 1821def int_hexagon_S2_asl_r_r_nac : 1822Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">; 1823 1824def int_hexagon_S2_asl_i_p_acc : 1825Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [ImmArg<2>]>; 1826 1827def int_hexagon_A4_vcmpwgtui : 1828Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [ImmArg<1>]>; 1829 1830def int_hexagon_M4_vrmpyoh_acc_s0 : 1831Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">; 1832 1833def int_hexagon_M4_vrmpyoh_acc_s1 : 1834Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">; 1835 1836def int_hexagon_A4_vrmaxh : 1837Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">; 1838 1839def int_hexagon_A2_vcmpbeq : 1840Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">; 1841 1842def int_hexagon_A2_vcmphgt : 1843Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">; 1844 1845def int_hexagon_A2_vnavgwcr : 1846Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">; 1847 1848def int_hexagon_M2_vrcmacr_s0c : 1849Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">; 1850 1851def int_hexagon_A2_vavgwcr : 1852Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">; 1853 1854def int_hexagon_S2_asl_i_p_xacc : 1855Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [ImmArg<2>]>; 1856 1857def int_hexagon_A4_vrmaxw : 1858Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">; 1859 1860def int_hexagon_A2_vnavghr : 1861Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">; 1862 1863def int_hexagon_M4_cmpyi_wh : 1864Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">; 1865 1866def int_hexagon_A2_tfrsi : 1867Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [ImmArg<0>]>; 1868 1869def int_hexagon_S2_asr_i_r_acc : 1870Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [ImmArg<2>]>; 1871 1872def int_hexagon_A2_svnavgh : 1873Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">; 1874 1875def int_hexagon_S2_lsr_i_r : 1876Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [ImmArg<1>]>; 1877 1878def int_hexagon_M2_vmac2 : 1879Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">; 1880 1881def int_hexagon_A4_vcmphgtui : 1882Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [ImmArg<1>]>; 1883 1884def int_hexagon_A2_svavgh : 1885Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">; 1886 1887def int_hexagon_M4_vrmpyeh_acc_s0 : 1888Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">; 1889 1890def int_hexagon_M4_vrmpyeh_acc_s1 : 1891Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">; 1892 1893def int_hexagon_S2_lsr_i_p : 1894Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [ImmArg<1>]>; 1895 1896def int_hexagon_A2_combine_hl : 1897Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">; 1898 1899def int_hexagon_M2_mpy_up : 1900Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">; 1901 1902def int_hexagon_A2_combine_hh : 1903Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">; 1904 1905def int_hexagon_A2_negsat : 1906Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">; 1907 1908def int_hexagon_M2_mpyd_hl_s0 : 1909Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">; 1910 1911def int_hexagon_M2_mpyd_hl_s1 : 1912Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">; 1913 1914def int_hexagon_A4_bitsplit : 1915Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">; 1916 1917def int_hexagon_A2_vabshsat : 1918Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">; 1919 1920def int_hexagon_M2_mpyui : 1921Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">; 1922 1923def int_hexagon_A2_addh_l16_sat_ll : 1924Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">; 1925 1926def int_hexagon_S2_lsl_r_r_and : 1927Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">; 1928 1929def int_hexagon_M2_mmpyul_rs0 : 1930Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">; 1931 1932def int_hexagon_S2_asr_i_r_rnd_goodsyntax : 1933Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [ImmArg<1>]>; 1934 1935def int_hexagon_S2_lsr_r_p_nac : 1936Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">; 1937 1938def int_hexagon_C2_cmplt : 1939Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">; 1940 1941def int_hexagon_M2_cmacr_s0 : 1942Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">; 1943 1944def int_hexagon_M4_or_and : 1945Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">; 1946 1947def int_hexagon_M4_mpyrr_addi : 1948Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [ImmArg<0>]>; 1949 1950def int_hexagon_S4_or_andi : 1951Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [ImmArg<2>]>; 1952 1953def int_hexagon_M2_mpy_sat_hl_s0 : 1954Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">; 1955 1956def int_hexagon_M2_mpy_sat_hl_s1 : 1957Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">; 1958 1959def int_hexagon_M4_mpyrr_addr : 1960Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">; 1961 1962def int_hexagon_M2_mmachs_rs0 : 1963Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">; 1964 1965def int_hexagon_M2_mmachs_rs1 : 1966Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">; 1967 1968def int_hexagon_M2_vrcmpyr_s0c : 1969Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">; 1970 1971def int_hexagon_M2_mpy_acc_sat_hl_s0 : 1972Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">; 1973 1974def int_hexagon_M2_mpyd_acc_ll_s1 : 1975Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">; 1976 1977def int_hexagon_F2_sffixupn : 1978Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn">; 1979 1980def int_hexagon_M2_mpyd_acc_lh_s0 : 1981Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">; 1982 1983def int_hexagon_M2_mpyd_acc_lh_s1 : 1984Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">; 1985 1986def int_hexagon_M2_mpy_rnd_hh_s0 : 1987Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">; 1988 1989def int_hexagon_M2_mpy_rnd_hh_s1 : 1990Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">; 1991 1992def int_hexagon_A2_vadduhs : 1993Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">; 1994 1995def int_hexagon_A2_vsubuhs : 1996Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">; 1997 1998def int_hexagon_A2_subh_h16_hl : 1999Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">; 2000 2001def int_hexagon_A2_subh_h16_hh : 2002Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">; 2003 2004def int_hexagon_A2_xorp : 2005Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">; 2006 2007def int_hexagon_A4_tfrpcp : 2008Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrpcp">; 2009 2010def int_hexagon_A2_addh_h16_lh : 2011Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">; 2012 2013def int_hexagon_A2_addh_h16_sat_hl : 2014Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">; 2015 2016def int_hexagon_A2_addh_h16_ll : 2017Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">; 2018 2019def int_hexagon_A2_addh_h16_sat_hh : 2020Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">; 2021 2022def int_hexagon_A2_zxtb : 2023Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">; 2024 2025def int_hexagon_A2_zxth : 2026Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">; 2027 2028def int_hexagon_A2_vnavgwr : 2029Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">; 2030 2031def int_hexagon_M4_or_xor : 2032Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">; 2033 2034def int_hexagon_M2_mpyud_acc_hh_s0 : 2035Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">; 2036 2037def int_hexagon_M2_mpyud_acc_hh_s1 : 2038Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">; 2039 2040def int_hexagon_M5_vmacbsu : 2041Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">; 2042 2043def int_hexagon_M2_dpmpyuu_acc_s0 : 2044Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">; 2045 2046def int_hexagon_M2_mpy_rnd_hl_s0 : 2047Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">; 2048 2049def int_hexagon_M2_mpy_rnd_hl_s1 : 2050Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">; 2051 2052def int_hexagon_F2_sffms_lib : 2053Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib">; 2054 2055def int_hexagon_C4_cmpneqi : 2056Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [ImmArg<1>]>; 2057 2058def int_hexagon_M4_and_xor : 2059Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">; 2060 2061def int_hexagon_A2_sat : 2062Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">; 2063 2064def int_hexagon_M2_mpyd_nac_lh_s1 : 2065Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">; 2066 2067def int_hexagon_M2_mpyd_nac_lh_s0 : 2068Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">; 2069 2070def int_hexagon_A2_addsat : 2071Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">; 2072 2073def int_hexagon_A2_svavghs : 2074Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">; 2075 2076def int_hexagon_A2_vrsadub_acc : 2077Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">; 2078 2079def int_hexagon_C2_bitsclri : 2080Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [ImmArg<1>]>; 2081 2082def int_hexagon_A2_subh_h16_sat_hh : 2083Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">; 2084 2085def int_hexagon_A2_subh_h16_sat_hl : 2086Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">; 2087 2088def int_hexagon_M2_mmaculs_rs0 : 2089Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">; 2090 2091def int_hexagon_M2_mmaculs_rs1 : 2092Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">; 2093 2094def int_hexagon_M2_vradduh : 2095Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">; 2096 2097def int_hexagon_A4_addp_c : 2098Hexagon_i64i32_i64i64i32_Intrinsic<"HEXAGON_A4_addp_c">; 2099 2100def int_hexagon_C2_xor : 2101Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">; 2102 2103def int_hexagon_S2_lsl_r_r_acc : 2104Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">; 2105 2106def int_hexagon_M2_mmpyh_rs1 : 2107Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">; 2108 2109def int_hexagon_M2_mmpyh_rs0 : 2110Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">; 2111 2112def int_hexagon_F2_conv_df2ud_chop : 2113Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">; 2114 2115def int_hexagon_C4_or_or : 2116Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">; 2117 2118def int_hexagon_S4_vxaddsubhr : 2119Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">; 2120 2121def int_hexagon_S2_vsathub : 2122Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">; 2123 2124def int_hexagon_F2_conv_df2sf : 2125Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">; 2126 2127def int_hexagon_M2_hmmpyh_rs1 : 2128Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">; 2129 2130def int_hexagon_M2_hmmpyh_s1 : 2131Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">; 2132 2133def int_hexagon_A2_vavgwr : 2134Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">; 2135 2136def int_hexagon_S2_tableidxh_goodsyntax : 2137Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax">; 2138 2139def int_hexagon_A2_sxth : 2140Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">; 2141 2142def int_hexagon_A2_sxtb : 2143Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">; 2144 2145def int_hexagon_C4_or_orn : 2146Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">; 2147 2148def int_hexagon_M2_vrcmaci_s0c : 2149Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">; 2150 2151def int_hexagon_A2_sxtw : 2152Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">; 2153 2154def int_hexagon_M2_vabsdiffh : 2155Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">; 2156 2157def int_hexagon_M2_mpy_acc_lh_s1 : 2158Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">; 2159 2160def int_hexagon_M2_mpy_acc_lh_s0 : 2161Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">; 2162 2163def int_hexagon_M2_hmmpyl_s1 : 2164Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">; 2165 2166def int_hexagon_S2_cl1p : 2167Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">; 2168 2169def int_hexagon_M2_vabsdiffw : 2170Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">; 2171 2172def int_hexagon_A4_andnp : 2173Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">; 2174 2175def int_hexagon_C2_vmux : 2176Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">; 2177 2178def int_hexagon_S2_parityp : 2179Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">; 2180 2181def int_hexagon_S2_lsr_i_p_and : 2182Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [ImmArg<2>]>; 2183 2184def int_hexagon_S2_asr_i_r_or : 2185Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [ImmArg<2>]>; 2186 2187def int_hexagon_M2_mpyu_nac_ll_s0 : 2188Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">; 2189 2190def int_hexagon_M2_mpyu_nac_ll_s1 : 2191Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">; 2192 2193def int_hexagon_F2_sfcmpeq : 2194Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq">; 2195 2196def int_hexagon_A2_vaddb_map : 2197Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">; 2198 2199def int_hexagon_S2_lsr_r_r_nac : 2200Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">; 2201 2202def int_hexagon_A2_vcmpheq : 2203Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">; 2204 2205def int_hexagon_S2_clbnorm : 2206Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">; 2207 2208def int_hexagon_M2_cnacsc_s1 : 2209Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">; 2210 2211def int_hexagon_M2_cnacsc_s0 : 2212Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">; 2213 2214def int_hexagon_S4_subaddi : 2215Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [ImmArg<1>]>; 2216 2217def int_hexagon_M2_mpyud_nac_hl_s1 : 2218Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">; 2219 2220def int_hexagon_M2_mpyud_nac_hl_s0 : 2221Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">; 2222 2223def int_hexagon_S5_vasrhrnd_goodsyntax : 2224Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [ImmArg<1>]>; 2225 2226def int_hexagon_S2_tstbit_r : 2227Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">; 2228 2229def int_hexagon_S4_vrcrotate : 2230Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [ImmArg<2>]>; 2231 2232def int_hexagon_M2_mmachs_s1 : 2233Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">; 2234 2235def int_hexagon_M2_mmachs_s0 : 2236Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">; 2237 2238def int_hexagon_S2_tstbit_i : 2239Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [ImmArg<1>]>; 2240 2241def int_hexagon_M2_mpy_up_s1 : 2242Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">; 2243 2244def int_hexagon_S2_extractu_rp : 2245Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">; 2246 2247def int_hexagon_M2_mmpyuh_rs0 : 2248Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">; 2249 2250def int_hexagon_S2_lsr_i_vw : 2251Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [ImmArg<1>]>; 2252 2253def int_hexagon_M2_mpy_rnd_ll_s0 : 2254Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">; 2255 2256def int_hexagon_M2_mpy_rnd_ll_s1 : 2257Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">; 2258 2259def int_hexagon_M4_or_or : 2260Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">; 2261 2262def int_hexagon_M2_mpyu_hh_s1 : 2263Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">; 2264 2265def int_hexagon_M2_mpyu_hh_s0 : 2266Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">; 2267 2268def int_hexagon_S2_asl_r_p_acc : 2269Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">; 2270 2271def int_hexagon_M2_mpyu_nac_lh_s0 : 2272Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">; 2273 2274def int_hexagon_M2_mpyu_nac_lh_s1 : 2275Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">; 2276 2277def int_hexagon_M2_mpy_sat_ll_s0 : 2278Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">; 2279 2280def int_hexagon_M2_mpy_sat_ll_s1 : 2281Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">; 2282 2283def int_hexagon_F2_conv_w2df : 2284Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">; 2285 2286def int_hexagon_A2_subh_l16_sat_hl : 2287Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">; 2288 2289def int_hexagon_C2_cmpeqi : 2290Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [ImmArg<1>]>; 2291 2292def int_hexagon_S2_asl_i_r_and : 2293Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [ImmArg<2>]>; 2294 2295def int_hexagon_S2_vcnegh : 2296Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">; 2297 2298def int_hexagon_A4_vcmpweqi : 2299Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [ImmArg<1>]>; 2300 2301def int_hexagon_M2_vdmpyrs_s0 : 2302Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">; 2303 2304def int_hexagon_M2_vdmpyrs_s1 : 2305Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">; 2306 2307def int_hexagon_M4_xor_xacc : 2308Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">; 2309 2310def int_hexagon_M2_vdmpys_s1 : 2311Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">; 2312 2313def int_hexagon_M2_vdmpys_s0 : 2314Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">; 2315 2316def int_hexagon_A2_vavgubr : 2317Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">; 2318 2319def int_hexagon_M2_mpyu_hl_s1 : 2320Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">; 2321 2322def int_hexagon_M2_mpyu_hl_s0 : 2323Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">; 2324 2325def int_hexagon_S2_asl_r_r_acc : 2326Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">; 2327 2328def int_hexagon_S2_cl0p : 2329Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">; 2330 2331def int_hexagon_S2_valignib : 2332Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [ImmArg<2>]>; 2333 2334def int_hexagon_F2_sffixupd : 2335Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd">; 2336 2337def int_hexagon_M2_mpy_sat_rnd_hl_s1 : 2338Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">; 2339 2340def int_hexagon_M2_mpy_sat_rnd_hl_s0 : 2341Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">; 2342 2343def int_hexagon_M2_cmacsc_s0 : 2344Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">; 2345 2346def int_hexagon_M2_cmacsc_s1 : 2347Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">; 2348 2349def int_hexagon_S2_ct1 : 2350Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">; 2351 2352def int_hexagon_S2_ct0 : 2353Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">; 2354 2355def int_hexagon_M2_dpmpyuu_nac_s0 : 2356Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">; 2357 2358def int_hexagon_M2_mmpyul_rs1 : 2359Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">; 2360 2361def int_hexagon_S4_ntstbit_i : 2362Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [ImmArg<1>]> ; 2363 2364def int_hexagon_F2_sffixupr : 2365Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr">; 2366 2367def int_hexagon_S2_asr_r_p_xor : 2368Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">; 2369 2370def int_hexagon_M2_mpyud_acc_hl_s0 : 2371Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">; 2372 2373def int_hexagon_M2_mpyud_acc_hl_s1 : 2374Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">; 2375 2376def int_hexagon_A2_vcmphgtu : 2377Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">; 2378 2379def int_hexagon_C2_andn : 2380Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">; 2381 2382def int_hexagon_M2_vmpy2s_s0pack : 2383Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">; 2384 2385def int_hexagon_S4_addaddi : 2386Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [ImmArg<2>]>; 2387 2388def int_hexagon_M2_mpyd_acc_ll_s0 : 2389Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">; 2390 2391def int_hexagon_M2_mpy_acc_sat_hl_s1 : 2392Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">; 2393 2394def int_hexagon_A4_rcmpeqi : 2395Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [ImmArg<1>]>; 2396 2397def int_hexagon_M4_xor_and : 2398Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">; 2399 2400def int_hexagon_S2_asl_i_p_and : 2401Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [ImmArg<2>]>; 2402 2403def int_hexagon_M2_mmpyuh_rs1 : 2404Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">; 2405 2406def int_hexagon_S2_asr_r_r_or : 2407Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">; 2408 2409def int_hexagon_A4_round_ri : 2410Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [ImmArg<1>]>; 2411 2412def int_hexagon_A2_max : 2413Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">; 2414 2415def int_hexagon_A4_round_rr : 2416Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">; 2417 2418def int_hexagon_A4_combineii : 2419Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineii", [ImmArg<0>, ImmArg<1>]>; 2420 2421def int_hexagon_A4_combineir : 2422Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [ImmArg<0>]>; 2423 2424def int_hexagon_C4_and_orn : 2425Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">; 2426 2427def int_hexagon_M5_vmacbuu : 2428Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">; 2429 2430def int_hexagon_A4_rcmpeq : 2431Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">; 2432 2433def int_hexagon_M4_cmpyr_whc : 2434Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">; 2435 2436def int_hexagon_S2_lsr_i_r_acc : 2437Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [ImmArg<2>]>; 2438 2439def int_hexagon_S2_vzxtbh : 2440Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">; 2441 2442def int_hexagon_M2_mmacuhs_rs1 : 2443Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">; 2444 2445def int_hexagon_S2_asr_r_r_sat : 2446Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">; 2447 2448def int_hexagon_A2_combinew : 2449Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">; 2450 2451def int_hexagon_M2_mpy_acc_ll_s1 : 2452Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">; 2453 2454def int_hexagon_M2_mpy_acc_ll_s0 : 2455Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">; 2456 2457def int_hexagon_M2_cmpyi_s0 : 2458Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">; 2459 2460def int_hexagon_S2_asl_r_p_or : 2461Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">; 2462 2463def int_hexagon_S4_ori_asl_ri : 2464Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [ImmArg<0>, ImmArg<2>]>; 2465 2466def int_hexagon_C4_nbitsset : 2467Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">; 2468 2469def int_hexagon_M2_mpyu_acc_hh_s1 : 2470Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">; 2471 2472def int_hexagon_M2_mpyu_acc_hh_s0 : 2473Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">; 2474 2475def int_hexagon_M2_mpyu_ll_s1 : 2476Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">; 2477 2478def int_hexagon_M2_mpyu_ll_s0 : 2479Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">; 2480 2481def int_hexagon_A2_addh_l16_ll : 2482Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">; 2483 2484def int_hexagon_S2_lsr_r_r_and : 2485Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">; 2486 2487def int_hexagon_A4_modwrapu : 2488Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">; 2489 2490def int_hexagon_A4_rcmpneq : 2491Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">; 2492 2493def int_hexagon_M2_mpyd_acc_hh_s0 : 2494Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">; 2495 2496def int_hexagon_M2_mpyd_acc_hh_s1 : 2497Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">; 2498 2499def int_hexagon_F2_sfimm_p : 2500Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [ImmArg<0>]>; 2501 2502def int_hexagon_F2_sfimm_n : 2503Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [ImmArg<0>]>; 2504 2505def int_hexagon_M4_cmpyr_wh : 2506Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">; 2507 2508def int_hexagon_S2_lsl_r_p_and : 2509Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">; 2510 2511def int_hexagon_A2_vavgub : 2512Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">; 2513 2514def int_hexagon_F2_conv_d2sf : 2515Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">; 2516 2517def int_hexagon_A2_vavguh : 2518Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">; 2519 2520def int_hexagon_A4_cmpbeqi : 2521Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [ImmArg<1>]>; 2522 2523def int_hexagon_F2_sfcmpuo : 2524Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo">; 2525 2526def int_hexagon_A2_vavguw : 2527Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">; 2528 2529def int_hexagon_S2_asr_i_p_nac : 2530Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [ImmArg<2>]>; 2531 2532def int_hexagon_S2_vsatwh_nopack : 2533Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">; 2534 2535def int_hexagon_M2_mpyd_hh_s0 : 2536Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">; 2537 2538def int_hexagon_M2_mpyd_hh_s1 : 2539Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">; 2540 2541def int_hexagon_S2_lsl_r_p_or : 2542Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">; 2543 2544def int_hexagon_A2_minu : 2545Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">; 2546 2547def int_hexagon_M2_mpy_sat_lh_s1 : 2548Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">; 2549 2550def int_hexagon_M4_or_andn : 2551Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">; 2552 2553def int_hexagon_A2_minp : 2554Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">; 2555 2556def int_hexagon_S4_or_andix : 2557Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [ImmArg<2>]>; 2558 2559def int_hexagon_M2_mpy_rnd_lh_s0 : 2560Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">; 2561 2562def int_hexagon_M2_mpy_rnd_lh_s1 : 2563Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">; 2564 2565def int_hexagon_M2_mmpyuh_s0 : 2566Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">; 2567 2568def int_hexagon_M2_mmpyuh_s1 : 2569Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">; 2570 2571def int_hexagon_M2_mpy_acc_sat_lh_s0 : 2572Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">; 2573 2574def int_hexagon_F2_sfcmpge : 2575Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge">; 2576 2577def int_hexagon_F2_sfmin : 2578Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin">; 2579 2580def int_hexagon_F2_sfcmpgt : 2581Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt">; 2582 2583def int_hexagon_M4_vpmpyh : 2584Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">; 2585 2586def int_hexagon_M2_mmacuhs_rs0 : 2587Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">; 2588 2589def int_hexagon_M2_mpyd_rnd_lh_s1 : 2590Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">; 2591 2592def int_hexagon_M2_mpyd_rnd_lh_s0 : 2593Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">; 2594 2595def int_hexagon_A2_roundsat : 2596Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">; 2597 2598def int_hexagon_S2_ct1p : 2599Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">; 2600 2601def int_hexagon_S4_extract_rp : 2602Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">; 2603 2604def int_hexagon_S2_lsl_r_r_or : 2605Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">; 2606 2607def int_hexagon_C4_cmplteui : 2608Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [ImmArg<1>]>; 2609 2610def int_hexagon_S4_addi_lsr_ri : 2611Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [ImmArg<0>, ImmArg<2>]>; 2612 2613def int_hexagon_A4_tfrcpp : 2614Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrcpp">; 2615 2616def int_hexagon_S2_asr_i_svw_trun : 2617Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [ImmArg<1>]>; 2618 2619def int_hexagon_A4_cmphgti : 2620Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [ImmArg<1>]>; 2621 2622def int_hexagon_A4_vrminh : 2623Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">; 2624 2625def int_hexagon_A4_vrminw : 2626Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">; 2627 2628def int_hexagon_A4_cmphgtu : 2629Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">; 2630 2631def int_hexagon_S2_insertp_rp : 2632Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">; 2633 2634def int_hexagon_A2_vnavghcr : 2635Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">; 2636 2637def int_hexagon_S4_subi_asl_ri : 2638Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [ImmArg<0>, ImmArg<2>]>; 2639 2640def int_hexagon_S2_lsl_r_vh : 2641Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">; 2642 2643def int_hexagon_M2_mpy_hh_s0 : 2644Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">; 2645 2646def int_hexagon_A2_vsubws : 2647Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">; 2648 2649def int_hexagon_A2_sath : 2650Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">; 2651 2652def int_hexagon_S2_asl_r_p_xor : 2653Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">; 2654 2655def int_hexagon_A2_satb : 2656Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">; 2657 2658def int_hexagon_C2_cmpltu : 2659Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">; 2660 2661def int_hexagon_S2_insertp : 2662Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [ImmArg<2>, ImmArg<3>]>; 2663 2664def int_hexagon_M2_mpyd_rnd_ll_s1 : 2665Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">; 2666 2667def int_hexagon_M2_mpyd_rnd_ll_s0 : 2668Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">; 2669 2670def int_hexagon_S2_lsr_i_p_nac : 2671Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [ImmArg<2>]>; 2672 2673def int_hexagon_S2_extractup_rp : 2674Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">; 2675 2676def int_hexagon_S4_vxaddsubw : 2677Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">; 2678 2679def int_hexagon_S4_vxaddsubh : 2680Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">; 2681 2682def int_hexagon_A2_asrh : 2683Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">; 2684 2685def int_hexagon_S4_extractp_rp : 2686Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">; 2687 2688def int_hexagon_S2_lsr_r_r_acc : 2689Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">; 2690 2691def int_hexagon_M2_mpyd_nac_ll_s1 : 2692Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">; 2693 2694def int_hexagon_M2_mpyd_nac_ll_s0 : 2695Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">; 2696 2697def int_hexagon_C2_or : 2698Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">; 2699 2700def int_hexagon_M2_mmpyul_s1 : 2701Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">; 2702 2703def int_hexagon_M2_vrcmacr_s0 : 2704Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">; 2705 2706def int_hexagon_A2_xor : 2707Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">; 2708 2709def int_hexagon_A2_add : 2710Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">; 2711 2712def int_hexagon_A2_vsububs : 2713Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">; 2714 2715def int_hexagon_M2_vmpy2s_s1 : 2716Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">; 2717 2718def int_hexagon_M2_vmpy2s_s0 : 2719Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">; 2720 2721def int_hexagon_A2_vraddub_acc : 2722Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">; 2723 2724def int_hexagon_F2_sfinvsqrta : 2725Hexagon_floati32_float_Intrinsic<"HEXAGON_F2_sfinvsqrta">; 2726 2727def int_hexagon_S2_ct0p : 2728Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">; 2729 2730def int_hexagon_A2_svaddh : 2731Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">; 2732 2733def int_hexagon_S2_vcrotate : 2734Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">; 2735 2736def int_hexagon_A2_aslh : 2737Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">; 2738 2739def int_hexagon_A2_subh_h16_lh : 2740Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">; 2741 2742def int_hexagon_A2_subh_h16_ll : 2743Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">; 2744 2745def int_hexagon_M2_hmmpyl_rs1 : 2746Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">; 2747 2748def int_hexagon_S2_asr_r_p : 2749Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">; 2750 2751def int_hexagon_S2_vsplatrh : 2752Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">; 2753 2754def int_hexagon_S2_asr_r_r : 2755Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">; 2756 2757def int_hexagon_A2_addh_h16_hl : 2758Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">; 2759 2760def int_hexagon_S2_vsplatrb : 2761Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">; 2762 2763def int_hexagon_A2_addh_h16_hh : 2764Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">; 2765 2766def int_hexagon_M2_cmpyr_s0 : 2767Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">; 2768 2769def int_hexagon_M2_dpmpyss_rnd_s0 : 2770Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">; 2771 2772def int_hexagon_C2_muxri : 2773Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri", [ImmArg<1>]>; 2774 2775def int_hexagon_M2_vmac2es_s0 : 2776Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">; 2777 2778def int_hexagon_M2_vmac2es_s1 : 2779Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">; 2780 2781def int_hexagon_C2_pxfer_map : 2782Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">; 2783 2784def int_hexagon_M2_mpyu_lh_s1 : 2785Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">; 2786 2787def int_hexagon_M2_mpyu_lh_s0 : 2788Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">; 2789 2790def int_hexagon_S2_asl_i_r_or : 2791Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [ImmArg<2>]>; 2792 2793def int_hexagon_M2_mpyd_acc_hl_s0 : 2794Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">; 2795 2796def int_hexagon_M2_mpyd_acc_hl_s1 : 2797Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">; 2798 2799def int_hexagon_S2_asr_r_p_nac : 2800Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">; 2801 2802def int_hexagon_A2_vaddw : 2803Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">; 2804 2805def int_hexagon_S2_asr_i_r_and : 2806Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [ImmArg<2>]>; 2807 2808def int_hexagon_A2_vaddh : 2809Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">; 2810 2811def int_hexagon_M2_mpy_nac_sat_lh_s1 : 2812Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">; 2813 2814def int_hexagon_M2_mpy_nac_sat_lh_s0 : 2815Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">; 2816 2817def int_hexagon_C2_cmpeqp : 2818Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">; 2819 2820def int_hexagon_M4_mpyri_addi : 2821Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [ImmArg<0>, ImmArg<2>]>; 2822 2823def int_hexagon_A2_not : 2824Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">; 2825 2826def int_hexagon_S4_andi_lsr_ri : 2827Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [ImmArg<0>, ImmArg<2>]>; 2828 2829def int_hexagon_M2_macsip : 2830Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [ImmArg<2>]>; 2831 2832def int_hexagon_A2_tfrcrr : 2833Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrcrr">; 2834 2835def int_hexagon_M2_macsin : 2836Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [ImmArg<2>]>; 2837 2838def int_hexagon_C2_orn : 2839Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">; 2840 2841def int_hexagon_M4_and_andn : 2842Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">; 2843 2844def int_hexagon_F2_sfmpy : 2845Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy">; 2846 2847def int_hexagon_M2_mpyud_nac_hh_s1 : 2848Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">; 2849 2850def int_hexagon_M2_mpyud_nac_hh_s0 : 2851Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">; 2852 2853def int_hexagon_S2_lsr_r_p_acc : 2854Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">; 2855 2856def int_hexagon_S2_asr_r_vw : 2857Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">; 2858 2859def int_hexagon_M4_and_or : 2860Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">; 2861 2862def int_hexagon_S2_asr_r_vh : 2863Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">; 2864 2865def int_hexagon_C2_mask : 2866Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">; 2867 2868def int_hexagon_M2_mpy_nac_hh_s0 : 2869Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">; 2870 2871def int_hexagon_M2_mpy_nac_hh_s1 : 2872Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">; 2873 2874def int_hexagon_M2_mpy_up_s1_sat : 2875Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">; 2876 2877def int_hexagon_A4_vcmpbgt : 2878Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">; 2879 2880def int_hexagon_M5_vrmacbsu : 2881Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">; 2882 2883def int_hexagon_S2_tableidxw_goodsyntax : 2884Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax">; 2885 2886def int_hexagon_A2_vrsadub : 2887Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">; 2888 2889def int_hexagon_A2_tfrrcr : 2890Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrrcr">; 2891 2892def int_hexagon_M2_vrcmpys_acc_s1 : 2893Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">; 2894 2895def int_hexagon_F2_dfcmpge : 2896Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge">; 2897 2898def int_hexagon_M2_accii : 2899Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [ImmArg<2>]>; 2900 2901def int_hexagon_A5_vaddhubs : 2902Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">; 2903 2904def int_hexagon_A2_vmaxw : 2905Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">; 2906 2907def int_hexagon_A2_vmaxb : 2908Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">; 2909 2910def int_hexagon_A2_vmaxh : 2911Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">; 2912 2913def int_hexagon_S2_vsxthw : 2914Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">; 2915 2916def int_hexagon_S4_andi_asl_ri : 2917Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [ImmArg<0>, ImmArg<2>]>; 2918 2919def int_hexagon_S2_asl_i_p_nac : 2920Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [ImmArg<2>]>; 2921 2922def int_hexagon_S2_lsl_r_p_xor : 2923Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">; 2924 2925def int_hexagon_C2_cmpgt : 2926Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">; 2927 2928def int_hexagon_F2_conv_df2d_chop : 2929Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">; 2930 2931def int_hexagon_M2_mpyu_nac_hl_s0 : 2932Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">; 2933 2934def int_hexagon_M2_mpyu_nac_hl_s1 : 2935Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">; 2936 2937def int_hexagon_F2_conv_sf2w : 2938Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">; 2939 2940def int_hexagon_S2_lsr_r_p_or : 2941Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">; 2942 2943def int_hexagon_F2_sfclass : 2944Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass">; 2945 2946def int_hexagon_M2_mpyud_acc_lh_s0 : 2947Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">; 2948 2949def int_hexagon_M4_xor_andn : 2950Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">; 2951 2952def int_hexagon_S2_addasl_rrri : 2953Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [ImmArg<2>]>; 2954 2955def int_hexagon_M5_vdmpybsu : 2956Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">; 2957 2958def int_hexagon_M2_mpyu_nac_hh_s0 : 2959Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">; 2960 2961def int_hexagon_M2_mpyu_nac_hh_s1 : 2962Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">; 2963 2964def int_hexagon_A2_addi : 2965Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [ImmArg<1>]>; 2966 2967def int_hexagon_A2_addp : 2968Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">; 2969 2970def int_hexagon_M2_vmpy2s_s1pack : 2971Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">; 2972 2973def int_hexagon_S4_clbpnorm : 2974Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">; 2975 2976def int_hexagon_A4_round_rr_sat : 2977Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">; 2978 2979def int_hexagon_M2_nacci : 2980Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">; 2981 2982def int_hexagon_S2_shuffeh : 2983Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">; 2984 2985def int_hexagon_S2_lsr_i_r_and : 2986Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [ImmArg<2>]>; 2987 2988def int_hexagon_M2_mpy_sat_rnd_hh_s1 : 2989Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">; 2990 2991def int_hexagon_M2_mpy_sat_rnd_hh_s0 : 2992Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">; 2993 2994def int_hexagon_F2_conv_sf2uw : 2995Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">; 2996 2997def int_hexagon_A2_vsubh : 2998Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">; 2999 3000def int_hexagon_F2_conv_sf2ud : 3001Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">; 3002 3003def int_hexagon_A2_vsubw : 3004Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">; 3005 3006def int_hexagon_A2_vcmpwgt : 3007Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">; 3008 3009def int_hexagon_M4_xor_or : 3010Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">; 3011 3012def int_hexagon_F2_conv_sf2uw_chop : 3013Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">; 3014 3015def int_hexagon_S2_asl_r_vw : 3016Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">; 3017 3018def int_hexagon_S2_vsatwuh_nopack : 3019Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">; 3020 3021def int_hexagon_S2_asl_r_vh : 3022Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">; 3023 3024def int_hexagon_A2_svsubuhs : 3025Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">; 3026 3027def int_hexagon_M5_vmpybsu : 3028Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">; 3029 3030def int_hexagon_A2_subh_l16_sat_ll : 3031Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">; 3032 3033def int_hexagon_C4_and_and : 3034Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">; 3035 3036def int_hexagon_M2_mpyu_acc_hl_s1 : 3037Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">; 3038 3039def int_hexagon_M2_mpyu_acc_hl_s0 : 3040Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">; 3041 3042def int_hexagon_S2_lsr_r_p : 3043Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">; 3044 3045def int_hexagon_S2_lsr_r_r : 3046Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">; 3047 3048def int_hexagon_A4_subp_c : 3049Hexagon_i64i32_i64i64i32_Intrinsic<"HEXAGON_A4_subp_c">; 3050 3051def int_hexagon_A2_vsubhs : 3052Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">; 3053 3054def int_hexagon_C2_vitpack : 3055Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">; 3056 3057def int_hexagon_A2_vavguhr : 3058Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">; 3059 3060def int_hexagon_S2_vsplicerb : 3061Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">; 3062 3063def int_hexagon_C4_nbitsclr : 3064Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">; 3065 3066def int_hexagon_A2_vcmpbgtu : 3067Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">; 3068 3069def int_hexagon_M2_cmpys_s1 : 3070Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s1">; 3071 3072def int_hexagon_M2_cmpys_s0 : 3073Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">; 3074 3075def int_hexagon_F2_dfcmpuo : 3076Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo">; 3077 3078def int_hexagon_S2_shuffob : 3079Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">; 3080 3081def int_hexagon_C2_and : 3082Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">; 3083 3084def int_hexagon_S5_popcountp : 3085Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">; 3086 3087def int_hexagon_S4_extractp : 3088Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [ImmArg<1>, ImmArg<2>]>; 3089 3090def int_hexagon_S2_cl0 : 3091Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">; 3092 3093def int_hexagon_A4_vcmpbgti : 3094Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [ImmArg<1>]>; 3095 3096def int_hexagon_M2_mmacls_s1 : 3097Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">; 3098 3099def int_hexagon_M2_mmacls_s0 : 3100Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">; 3101 3102def int_hexagon_C4_cmpneq : 3103Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">; 3104 3105def int_hexagon_M2_vmac2es : 3106Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">; 3107 3108def int_hexagon_M2_vdmacs_s0 : 3109Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">; 3110 3111def int_hexagon_M2_vdmacs_s1 : 3112Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">; 3113 3114def int_hexagon_M2_mpyud_ll_s0 : 3115Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">; 3116 3117def int_hexagon_M2_mpyud_ll_s1 : 3118Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">; 3119 3120def int_hexagon_S2_clb : 3121Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">; 3122 3123def int_hexagon_M2_mpy_nac_ll_s0 : 3124Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">; 3125 3126def int_hexagon_M2_mpy_nac_ll_s1 : 3127Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">; 3128 3129def int_hexagon_M2_mpyd_nac_hl_s1 : 3130Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">; 3131 3132def int_hexagon_M2_mpyd_nac_hl_s0 : 3133Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">; 3134 3135def int_hexagon_M2_maci : 3136Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">; 3137 3138def int_hexagon_A2_vmaxuh : 3139Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">; 3140 3141def int_hexagon_A4_bitspliti : 3142Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [ImmArg<1>]>; 3143 3144def int_hexagon_A2_vmaxub : 3145Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">; 3146 3147def int_hexagon_M2_mpyud_hh_s0 : 3148Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">; 3149 3150def int_hexagon_M2_mpyud_hh_s1 : 3151Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">; 3152 3153def int_hexagon_M2_vrmac_s0 : 3154Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">; 3155 3156def int_hexagon_M2_mpy_sat_lh_s0 : 3157Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">; 3158 3159def int_hexagon_S2_asl_r_r_sat : 3160Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">; 3161 3162def int_hexagon_F2_conv_sf2d : 3163Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">; 3164 3165def int_hexagon_S2_asr_r_r_nac : 3166Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">; 3167 3168def int_hexagon_F2_dfimm_n : 3169Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [ImmArg<0>]>; 3170 3171def int_hexagon_A4_cmphgt : 3172Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">; 3173 3174def int_hexagon_F2_dfimm_p : 3175Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [ImmArg<0>]>; 3176 3177def int_hexagon_M2_mpyud_acc_lh_s1 : 3178Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">; 3179 3180def int_hexagon_M2_vcmpy_s1_sat_r : 3181Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">; 3182 3183def int_hexagon_M4_mpyri_addr_u2 : 3184Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [ImmArg<1>]>; 3185 3186def int_hexagon_M2_vcmpy_s1_sat_i : 3187Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">; 3188 3189def int_hexagon_S2_lsl_r_p_nac : 3190Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">; 3191 3192def int_hexagon_M5_vrmacbuu : 3193Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">; 3194 3195def int_hexagon_S5_asrhub_rnd_sat_goodsyntax : 3196Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [ImmArg<1>]>; 3197 3198def int_hexagon_S2_vspliceib : 3199Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [ImmArg<2>]>; 3200 3201def int_hexagon_M2_dpmpyss_acc_s0 : 3202Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">; 3203 3204def int_hexagon_M2_cnacs_s1 : 3205Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">; 3206 3207def int_hexagon_M2_cnacs_s0 : 3208Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">; 3209 3210def int_hexagon_A2_maxu : 3211Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">; 3212 3213def int_hexagon_A2_maxp : 3214Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">; 3215 3216def int_hexagon_A2_andir : 3217Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [ImmArg<1>]>; 3218 3219def int_hexagon_F2_sfrecipa : 3220Hexagon_floati32_floatfloat_Intrinsic<"HEXAGON_F2_sfrecipa">; 3221 3222def int_hexagon_A2_combineii : 3223Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [ImmArg<0>, ImmArg<1>]>; 3224 3225def int_hexagon_A4_orn : 3226Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">; 3227 3228def int_hexagon_A4_cmpbgtui : 3229Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [ImmArg<1>]>; 3230 3231def int_hexagon_S2_lsr_r_r_or : 3232Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">; 3233 3234def int_hexagon_A4_vcmpbeqi : 3235Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [ImmArg<1>]>; 3236 3237def int_hexagon_S2_lsl_r_r : 3238Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">; 3239 3240def int_hexagon_S2_lsl_r_p : 3241Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">; 3242 3243def int_hexagon_A2_or : 3244Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">; 3245 3246def int_hexagon_F2_dfcmpeq : 3247Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq">; 3248 3249def int_hexagon_C2_cmpeq : 3250Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">; 3251 3252def int_hexagon_A2_tfrp : 3253Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">; 3254 3255def int_hexagon_C4_and_andn : 3256Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">; 3257 3258def int_hexagon_S2_vsathub_nopack : 3259Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">; 3260 3261def int_hexagon_A2_satuh : 3262Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">; 3263 3264def int_hexagon_A2_satub : 3265Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">; 3266 3267def int_hexagon_M2_vrcmpys_s1 : 3268Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">; 3269 3270def int_hexagon_S4_or_ori : 3271Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [ImmArg<2>]>; 3272 3273def int_hexagon_C4_fastcorner9_not : 3274Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">; 3275 3276def int_hexagon_A2_tfrih : 3277Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [ImmArg<1>]>; 3278 3279def int_hexagon_A2_tfril : 3280Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [ImmArg<1>]>; 3281 3282def int_hexagon_M4_mpyri_addr : 3283Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [ImmArg<2>]>; 3284 3285def int_hexagon_S2_vtrunehb : 3286Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">; 3287 3288def int_hexagon_A2_vabsw : 3289Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">; 3290 3291def int_hexagon_A2_vabsh : 3292Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">; 3293 3294def int_hexagon_F2_sfsub : 3295Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub">; 3296 3297def int_hexagon_C2_muxii : 3298Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii", [ImmArg<1>, ImmArg<2>]>; 3299 3300def int_hexagon_C2_muxir : 3301Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir", [ImmArg<2>]>; 3302 3303def int_hexagon_A2_swiz : 3304Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">; 3305 3306def int_hexagon_S2_asr_i_p_and : 3307Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [ImmArg<2>]>; 3308 3309def int_hexagon_M2_cmpyrsc_s0 : 3310Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">; 3311 3312def int_hexagon_M2_cmpyrsc_s1 : 3313Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">; 3314 3315def int_hexagon_A2_vraddub : 3316Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">; 3317 3318def int_hexagon_A4_tlbmatch : 3319Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">; 3320 3321def int_hexagon_F2_conv_df2w_chop : 3322Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">; 3323 3324def int_hexagon_A2_and : 3325Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">; 3326 3327def int_hexagon_S2_lsr_r_p_and : 3328Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">; 3329 3330def int_hexagon_M2_mpy_nac_sat_ll_s1 : 3331Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">; 3332 3333def int_hexagon_M2_mpy_nac_sat_ll_s0 : 3334Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">; 3335 3336def int_hexagon_S4_extract : 3337Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [ImmArg<1>, ImmArg<2>]>; 3338 3339def int_hexagon_A2_vcmpweq : 3340Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">; 3341 3342def int_hexagon_M2_acci : 3343Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">; 3344 3345def int_hexagon_S2_lsr_i_p_acc : 3346Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [ImmArg<2>]>; 3347 3348def int_hexagon_S2_lsr_i_p_or : 3349Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [ImmArg<2>]>; 3350 3351def int_hexagon_F2_conv_ud2sf : 3352Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">; 3353 3354def int_hexagon_A2_tfr : 3355Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">; 3356 3357def int_hexagon_S2_asr_i_p_or : 3358Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [ImmArg<2>]>; 3359 3360def int_hexagon_A2_subri : 3361Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [ImmArg<0>]>; 3362 3363def int_hexagon_A4_vrmaxuw : 3364Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">; 3365 3366def int_hexagon_M5_vmpybuu : 3367Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">; 3368 3369def int_hexagon_A4_vrmaxuh : 3370Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">; 3371 3372def int_hexagon_S2_asl_i_vw : 3373Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [ImmArg<1>]>; 3374 3375def int_hexagon_A2_vavgw : 3376Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">; 3377 3378def int_hexagon_S2_brev : 3379Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">; 3380 3381def int_hexagon_A2_vavgh : 3382Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">; 3383 3384def int_hexagon_S2_clrbit_i : 3385Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [ImmArg<1>]>; 3386 3387def int_hexagon_S2_asl_i_vh : 3388Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [ImmArg<1>]>; 3389 3390def int_hexagon_S2_lsr_i_r_or : 3391Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [ImmArg<2>]>; 3392 3393def int_hexagon_S2_lsl_r_r_nac : 3394Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">; 3395 3396def int_hexagon_M2_mmpyl_rs1 : 3397Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">; 3398 3399def int_hexagon_M2_mpyud_hl_s1 : 3400Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">; 3401 3402def int_hexagon_M2_mmpyl_s0 : 3403Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">; 3404 3405def int_hexagon_M2_mmpyl_s1 : 3406Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">; 3407 3408def int_hexagon_M2_naccii : 3409Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [ImmArg<2>]>; 3410 3411def int_hexagon_S2_vrndpackwhs : 3412Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">; 3413 3414def int_hexagon_S2_vtrunewh : 3415Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">; 3416 3417def int_hexagon_M2_dpmpyss_nac_s0 : 3418Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">; 3419 3420def int_hexagon_M2_mpyd_ll_s0 : 3421Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">; 3422 3423def int_hexagon_M2_mpyd_ll_s1 : 3424Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">; 3425 3426def int_hexagon_M4_mac_up_s1_sat : 3427Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">; 3428 3429def int_hexagon_S4_vrcrotate_acc : 3430Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [ImmArg<3>]>; 3431 3432def int_hexagon_F2_conv_uw2df : 3433Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">; 3434 3435def int_hexagon_A2_vaddubs : 3436Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">; 3437 3438def int_hexagon_S2_asr_r_r_acc : 3439Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">; 3440 3441def int_hexagon_A2_orir : 3442Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [ImmArg<1>]>; 3443 3444def int_hexagon_A2_andp : 3445Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">; 3446 3447def int_hexagon_S2_lfsp : 3448Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">; 3449 3450def int_hexagon_A2_min : 3451Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">; 3452 3453def int_hexagon_M2_mpysmi : 3454Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi", [ImmArg<1>]>; 3455 3456def int_hexagon_M2_vcmpy_s0_sat_r : 3457Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">; 3458 3459def int_hexagon_M2_mpyu_acc_ll_s1 : 3460Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">; 3461 3462def int_hexagon_M2_mpyu_acc_ll_s0 : 3463Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">; 3464 3465def int_hexagon_S2_asr_r_svw_trun : 3466Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">; 3467 3468def int_hexagon_M2_mmpyh_s0 : 3469Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">; 3470 3471def int_hexagon_M2_mmpyh_s1 : 3472Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">; 3473 3474def int_hexagon_F2_conv_sf2df : 3475Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">; 3476 3477def int_hexagon_S2_vtrunohb : 3478Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">; 3479 3480def int_hexagon_F2_conv_sf2d_chop : 3481Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">; 3482 3483def int_hexagon_M2_mpyd_lh_s0 : 3484Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">; 3485 3486def int_hexagon_F2_conv_df2w : 3487Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">; 3488 3489def int_hexagon_S5_asrhub_sat : 3490Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [ImmArg<1>]>; 3491 3492def int_hexagon_S2_asl_i_r_xacc : 3493Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [ImmArg<2>]>; 3494 3495def int_hexagon_F2_conv_df2d : 3496Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">; 3497 3498def int_hexagon_M2_mmaculs_s1 : 3499Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">; 3500 3501def int_hexagon_M2_mmaculs_s0 : 3502Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">; 3503 3504def int_hexagon_A2_svadduhs : 3505Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">; 3506 3507def int_hexagon_F2_conv_sf2w_chop : 3508Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">; 3509 3510def int_hexagon_S2_svsathub : 3511Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">; 3512 3513def int_hexagon_M2_mpyd_rnd_hl_s1 : 3514Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">; 3515 3516def int_hexagon_M2_mpyd_rnd_hl_s0 : 3517Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">; 3518 3519def int_hexagon_S2_setbit_r : 3520Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">; 3521 3522def int_hexagon_A2_vavghr : 3523Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">; 3524 3525def int_hexagon_F2_sffma_sc : 3526Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc">; 3527 3528def int_hexagon_F2_dfclass : 3529Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [ImmArg<1>]>; 3530 3531def int_hexagon_F2_conv_df2ud : 3532Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">; 3533 3534def int_hexagon_F2_conv_df2uw : 3535Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">; 3536 3537def int_hexagon_M2_cmpyrs_s0 : 3538Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">; 3539 3540def int_hexagon_M2_cmpyrs_s1 : 3541Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">; 3542 3543def int_hexagon_C4_cmpltei : 3544Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [ImmArg<1>]>; 3545 3546def int_hexagon_C4_cmplteu : 3547Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">; 3548 3549def int_hexagon_A2_vsubb_map : 3550Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">; 3551 3552def int_hexagon_A2_subh_l16_ll : 3553Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">; 3554 3555def int_hexagon_S2_asr_i_r_rnd : 3556Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [ImmArg<1>]>; 3557 3558def int_hexagon_M2_vrmpy_s0 : 3559Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">; 3560 3561def int_hexagon_M2_mpyd_rnd_hh_s1 : 3562Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">; 3563 3564def int_hexagon_M2_mpyd_rnd_hh_s0 : 3565Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">; 3566 3567def int_hexagon_A2_minup : 3568Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">; 3569 3570def int_hexagon_S2_valignrb : 3571Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">; 3572 3573def int_hexagon_S2_asr_r_p_acc : 3574Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">; 3575 3576def int_hexagon_M2_mmpyl_rs0 : 3577Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">; 3578 3579def int_hexagon_M2_vrcmaci_s0 : 3580Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">; 3581 3582def int_hexagon_A2_vaddub : 3583Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">; 3584 3585def int_hexagon_A2_combine_lh : 3586Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">; 3587 3588def int_hexagon_M5_vdmacbsu : 3589Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">; 3590 3591def int_hexagon_A2_combine_ll : 3592Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">; 3593 3594def int_hexagon_M2_mpyud_hl_s0 : 3595Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">; 3596 3597def int_hexagon_M2_vrcmpyi_s0c : 3598Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">; 3599 3600def int_hexagon_S2_asr_i_p_rnd : 3601Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [ImmArg<1>]>; 3602 3603def int_hexagon_A2_addpsat : 3604Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">; 3605 3606def int_hexagon_A2_svaddhs : 3607Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">; 3608 3609def int_hexagon_S4_ori_lsr_ri : 3610Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [ImmArg<0>, ImmArg<2>]>; 3611 3612def int_hexagon_M2_mpy_sat_rnd_ll_s1 : 3613Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">; 3614 3615def int_hexagon_M2_mpy_sat_rnd_ll_s0 : 3616Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">; 3617 3618def int_hexagon_A2_vminw : 3619Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">; 3620 3621def int_hexagon_A2_vminh : 3622Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">; 3623 3624def int_hexagon_M2_vrcmpyr_s0 : 3625Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">; 3626 3627def int_hexagon_A2_vminb : 3628Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">; 3629 3630def int_hexagon_M2_vcmac_s0_sat_i : 3631Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">; 3632 3633def int_hexagon_M2_mpyud_lh_s0 : 3634Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">; 3635 3636def int_hexagon_M2_mpyud_lh_s1 : 3637Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">; 3638 3639def int_hexagon_S2_asl_r_r_or : 3640Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">; 3641 3642def int_hexagon_S4_lsli : 3643Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [ImmArg<0>]>; 3644 3645def int_hexagon_S2_lsl_r_vw : 3646Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">; 3647 3648def int_hexagon_M2_mpy_hh_s1 : 3649Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">; 3650 3651def int_hexagon_M4_vrmpyeh_s0 : 3652Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">; 3653 3654def int_hexagon_M4_vrmpyeh_s1 : 3655Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">; 3656 3657def int_hexagon_M2_mpy_nac_lh_s0 : 3658Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">; 3659 3660def int_hexagon_M2_mpy_nac_lh_s1 : 3661Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">; 3662 3663def int_hexagon_M2_vraddh : 3664Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">; 3665 3666def int_hexagon_C2_tfrrp : 3667Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">; 3668 3669def int_hexagon_M2_mpy_acc_sat_ll_s0 : 3670Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">; 3671 3672def int_hexagon_M2_mpy_acc_sat_ll_s1 : 3673Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">; 3674 3675def int_hexagon_S2_vtrunowh : 3676Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">; 3677 3678def int_hexagon_A2_abs : 3679Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">; 3680 3681def int_hexagon_A4_cmpbeq : 3682Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">; 3683 3684def int_hexagon_A2_negp : 3685Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">; 3686 3687def int_hexagon_S2_asl_i_r_sat : 3688Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat", [ImmArg<1>]>; 3689 3690def int_hexagon_A2_addh_l16_sat_hl : 3691Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">; 3692 3693def int_hexagon_S2_vsatwuh : 3694Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">; 3695 3696def int_hexagon_F2_dfcmpgt : 3697Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt">; 3698 3699def int_hexagon_S2_svsathb : 3700Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">; 3701 3702def int_hexagon_C2_cmpgtup : 3703Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">; 3704 3705def int_hexagon_A4_cround_ri : 3706Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [ImmArg<1>]>; 3707 3708def int_hexagon_S4_clbpaddi : 3709Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [ImmArg<1>]>; 3710 3711def int_hexagon_A4_cround_rr : 3712Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">; 3713 3714def int_hexagon_C2_mux : 3715Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">; 3716 3717def int_hexagon_M2_dpmpyuu_s0 : 3718Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">; 3719 3720def int_hexagon_S2_shuffeb : 3721Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">; 3722 3723def int_hexagon_A2_vminuw : 3724Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">; 3725 3726def int_hexagon_A2_vaddhs : 3727Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">; 3728 3729def int_hexagon_S2_insert_rp : 3730Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">; 3731 3732def int_hexagon_A2_vminuh : 3733Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">; 3734 3735def int_hexagon_A2_vminub : 3736Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">; 3737 3738def int_hexagon_S2_extractu : 3739Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [ImmArg<1>, ImmArg<2>]>; 3740 3741def int_hexagon_A2_svsubh : 3742Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">; 3743 3744def int_hexagon_S4_clbaddi : 3745Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [ImmArg<1>]>; 3746 3747def int_hexagon_F2_sffms : 3748Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms">; 3749 3750def int_hexagon_S2_vsxtbh : 3751Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">; 3752 3753def int_hexagon_M2_mpyud_nac_ll_s1 : 3754Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">; 3755 3756def int_hexagon_M2_mpyud_nac_ll_s0 : 3757Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">; 3758 3759def int_hexagon_A2_subp : 3760Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">; 3761 3762def int_hexagon_M2_vmpy2es_s1 : 3763Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">; 3764 3765def int_hexagon_M2_vmpy2es_s0 : 3766Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">; 3767 3768def int_hexagon_S4_parity : 3769Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">; 3770 3771def int_hexagon_M2_mpy_acc_hh_s1 : 3772Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">; 3773 3774def int_hexagon_M2_mpy_acc_hh_s0 : 3775Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">; 3776 3777def int_hexagon_S4_addi_asl_ri : 3778Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [ImmArg<0>, ImmArg<2>]>; 3779 3780def int_hexagon_M2_mpyd_nac_hh_s1 : 3781Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">; 3782 3783def int_hexagon_M2_mpyd_nac_hh_s0 : 3784Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">; 3785 3786def int_hexagon_S2_asr_i_r_nac : 3787Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [ImmArg<2>]>; 3788 3789def int_hexagon_A4_cmpheqi : 3790Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [ImmArg<1>]>; 3791 3792def int_hexagon_S2_lsr_r_p_xor : 3793Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">; 3794 3795def int_hexagon_M2_mpy_acc_hl_s1 : 3796Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">; 3797 3798def int_hexagon_M2_mpy_acc_hl_s0 : 3799Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">; 3800 3801def int_hexagon_F2_conv_sf2ud_chop : 3802Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">; 3803 3804def int_hexagon_C2_cmpgeui : 3805Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui", [ImmArg<1>]>; 3806 3807def int_hexagon_M2_mpy_acc_sat_hh_s0 : 3808Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">; 3809 3810def int_hexagon_M2_mpy_acc_sat_hh_s1 : 3811Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">; 3812 3813def int_hexagon_S2_asl_r_p_and : 3814Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">; 3815 3816def int_hexagon_A2_addh_h16_sat_lh : 3817Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">; 3818 3819def int_hexagon_A2_addh_h16_sat_ll : 3820Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">; 3821 3822def int_hexagon_M4_nac_up_s1_sat : 3823Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">; 3824 3825def int_hexagon_M2_mpyud_nac_lh_s1 : 3826Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">; 3827 3828def int_hexagon_M2_mpyud_nac_lh_s0 : 3829Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">; 3830 3831def int_hexagon_A4_round_ri_sat : 3832Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [ImmArg<1>]>; 3833 3834def int_hexagon_M2_mpy_nac_hl_s0 : 3835Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">; 3836 3837def int_hexagon_M2_mpy_nac_hl_s1 : 3838Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">; 3839 3840def int_hexagon_A2_vavghcr : 3841Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">; 3842 3843def int_hexagon_M2_mmacls_rs0 : 3844Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">; 3845 3846def int_hexagon_M2_mmacls_rs1 : 3847Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">; 3848 3849def int_hexagon_M2_cmaci_s0 : 3850Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">; 3851 3852def int_hexagon_S2_setbit_i : 3853Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [ImmArg<1>]>; 3854 3855def int_hexagon_S2_asl_i_p_or : 3856Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [ImmArg<2>]>; 3857 3858def int_hexagon_A4_andn : 3859Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">; 3860 3861def int_hexagon_M5_vrmpybsu : 3862Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">; 3863 3864def int_hexagon_S2_vrndpackwh : 3865Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">; 3866 3867def int_hexagon_M2_vcmac_s0_sat_r : 3868Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">; 3869 3870def int_hexagon_A2_vmaxuw : 3871Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">; 3872 3873def int_hexagon_C2_bitsclr : 3874Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">; 3875 3876def int_hexagon_M2_xor_xacc : 3877Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">; 3878 3879def int_hexagon_A4_vcmpbgtui : 3880Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [ImmArg<1>]>; 3881 3882def int_hexagon_A4_ornp : 3883Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">; 3884 3885def int_hexagon_A2_tfrpi : 3886Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [ImmArg<0>]>; 3887 3888def int_hexagon_C4_and_or : 3889Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">; 3890 3891def int_hexagon_M2_mpy_nac_sat_hh_s1 : 3892Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">; 3893 3894def int_hexagon_M2_mpy_nac_sat_hh_s0 : 3895Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">; 3896 3897def int_hexagon_A2_subh_h16_sat_ll : 3898Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">; 3899 3900def int_hexagon_A2_subh_h16_sat_lh : 3901Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">; 3902 3903def int_hexagon_M2_vmpy2su_s1 : 3904Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">; 3905 3906def int_hexagon_M2_vmpy2su_s0 : 3907Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">; 3908 3909def int_hexagon_S2_asr_i_p_acc : 3910Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [ImmArg<2>]>; 3911 3912def int_hexagon_C4_nbitsclri : 3913Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [ImmArg<1>]>; 3914 3915def int_hexagon_S2_lsr_i_vh : 3916Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [ImmArg<1>]>; 3917 3918def int_hexagon_S2_lsr_i_p_xacc : 3919Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [ImmArg<2>]>; 3920 3921// V55 Scalar Instructions. 3922 3923def int_hexagon_A5_ACS : 3924Hexagon_i64i32_i64i64i64_Intrinsic<"HEXAGON_A5_ACS">; 3925 3926// V60 Scalar Instructions. 3927 3928def int_hexagon_S6_rol_i_p_and : 3929Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [ImmArg<2>]>; 3930 3931def int_hexagon_S6_rol_i_r_xacc : 3932Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [ImmArg<2>]>; 3933 3934def int_hexagon_S6_rol_i_r_and : 3935Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and", [ImmArg<2>]>; 3936 3937def int_hexagon_S6_rol_i_r_acc : 3938Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [ImmArg<2>]>; 3939 3940def int_hexagon_S6_rol_i_p_xacc : 3941Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc", [ImmArg<2>]>; 3942 3943def int_hexagon_S6_rol_i_p : 3944Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p", [ImmArg<1>]>; 3945 3946def int_hexagon_S6_rol_i_p_nac : 3947Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac", [ImmArg<2>]>; 3948 3949def int_hexagon_S6_rol_i_p_acc : 3950Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc", [ImmArg<2>]>; 3951 3952def int_hexagon_S6_rol_i_r_or : 3953Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or", [ImmArg<2>]>; 3954 3955def int_hexagon_S6_rol_i_r : 3956Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [ImmArg<1>]>; 3957 3958def int_hexagon_S6_rol_i_r_nac : 3959Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [ImmArg<2>]>; 3960 3961def int_hexagon_S6_rol_i_p_or : 3962Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [ImmArg<2>]>; 3963 3964// V62 Scalar Instructions. 3965 3966def int_hexagon_S6_vtrunehb_ppp : 3967Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">; 3968 3969def int_hexagon_V6_ldntnt0 : 3970Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldntnt0">; 3971 3972def int_hexagon_M6_vabsdiffub : 3973Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffub">; 3974 3975def int_hexagon_S6_vtrunohb_ppp : 3976Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">; 3977 3978def int_hexagon_M6_vabsdiffb : 3979Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffb">; 3980 3981def int_hexagon_A6_vminub_RdP : 3982Hexagon_i64i32_i64i64_Intrinsic<"HEXAGON_A6_vminub_RdP">; 3983 3984def int_hexagon_S6_vsplatrbp : 3985Hexagon_i64_i32_Intrinsic<"HEXAGON_S6_vsplatrbp">; 3986 3987// V65 Scalar Instructions. 3988 3989def int_hexagon_A6_vcmpbeq_notany : 3990Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">; 3991 3992// V66 Scalar Instructions. 3993 3994def int_hexagon_F2_dfsub : 3995Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub">; 3996 3997def int_hexagon_F2_dfadd : 3998Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd">; 3999 4000def int_hexagon_M2_mnaci : 4001Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">; 4002 4003def int_hexagon_S2_mask : 4004Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [ImmArg<0>, ImmArg<1>]>; 4005 4006// V60 HVX Instructions. 4007 4008def int_hexagon_V6_veqb_or : 4009Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_or">; 4010 4011def int_hexagon_V6_veqb_or_128B : 4012Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_or_128B">; 4013 4014def int_hexagon_V6_vminub : 4015Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">; 4016 4017def int_hexagon_V6_vminub_128B : 4018Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">; 4019 4020def int_hexagon_V6_vaslw_acc : 4021Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">; 4022 4023def int_hexagon_V6_vaslw_acc_128B : 4024Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">; 4025 4026def int_hexagon_V6_vmpyhvsrs : 4027Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">; 4028 4029def int_hexagon_V6_vmpyhvsrs_128B : 4030Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">; 4031 4032def int_hexagon_V6_vsathub : 4033Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">; 4034 4035def int_hexagon_V6_vsathub_128B : 4036Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsathub_128B">; 4037 4038def int_hexagon_V6_vaddh_dv : 4039Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">; 4040 4041def int_hexagon_V6_vaddh_dv_128B : 4042Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">; 4043 4044def int_hexagon_V6_vrmpybusi : 4045Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi", [ImmArg<2>]>; 4046 4047def int_hexagon_V6_vrmpybusi_128B : 4048Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B", [ImmArg<2>]>; 4049 4050def int_hexagon_V6_vshufoh : 4051Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">; 4052 4053def int_hexagon_V6_vshufoh_128B : 4054Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">; 4055 4056def int_hexagon_V6_vasrwv : 4057Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">; 4058 4059def int_hexagon_V6_vasrwv_128B : 4060Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">; 4061 4062def int_hexagon_V6_vdmpyhsuisat : 4063Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">; 4064 4065def int_hexagon_V6_vdmpyhsuisat_128B : 4066Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">; 4067 4068def int_hexagon_V6_vrsadubi_acc : 4069Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [ImmArg<3>]>; 4070 4071def int_hexagon_V6_vrsadubi_acc_128B : 4072Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [ImmArg<3>]>; 4073 4074def int_hexagon_V6_vnavgw : 4075Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">; 4076 4077def int_hexagon_V6_vnavgw_128B : 4078Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">; 4079 4080def int_hexagon_V6_vnavgh : 4081Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">; 4082 4083def int_hexagon_V6_vnavgh_128B : 4084Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">; 4085 4086def int_hexagon_V6_vavgub : 4087Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">; 4088 4089def int_hexagon_V6_vavgub_128B : 4090Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">; 4091 4092def int_hexagon_V6_vsubb : 4093Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">; 4094 4095def int_hexagon_V6_vsubb_128B : 4096Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">; 4097 4098def int_hexagon_V6_vgtw_and : 4099Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_and">; 4100 4101def int_hexagon_V6_vgtw_and_128B : 4102Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_and_128B">; 4103 4104def int_hexagon_V6_vavgubrnd : 4105Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">; 4106 4107def int_hexagon_V6_vavgubrnd_128B : 4108Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">; 4109 4110def int_hexagon_V6_vrmpybusv : 4111Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv">; 4112 4113def int_hexagon_V6_vrmpybusv_128B : 4114Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">; 4115 4116def int_hexagon_V6_vsubbnq : 4117Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbnq">; 4118 4119def int_hexagon_V6_vsubbnq_128B : 4120Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbnq_128B">; 4121 4122def int_hexagon_V6_vroundhb : 4123Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">; 4124 4125def int_hexagon_V6_vroundhb_128B : 4126Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhb_128B">; 4127 4128def int_hexagon_V6_vadduhsat_dv : 4129Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">; 4130 4131def int_hexagon_V6_vadduhsat_dv_128B : 4132Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">; 4133 4134def int_hexagon_V6_vsububsat : 4135Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">; 4136 4137def int_hexagon_V6_vsububsat_128B : 4138Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">; 4139 4140def int_hexagon_V6_vmpabus_acc : 4141Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">; 4142 4143def int_hexagon_V6_vmpabus_acc_128B : 4144Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">; 4145 4146def int_hexagon_V6_vmux : 4147Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vmux">; 4148 4149def int_hexagon_V6_vmux_128B : 4150Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vmux_128B">; 4151 4152def int_hexagon_V6_vmpyhus : 4153Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">; 4154 4155def int_hexagon_V6_vmpyhus_128B : 4156Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">; 4157 4158def int_hexagon_V6_vpackeb : 4159Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">; 4160 4161def int_hexagon_V6_vpackeb_128B : 4162Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">; 4163 4164def int_hexagon_V6_vsubhnq : 4165Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhnq">; 4166 4167def int_hexagon_V6_vsubhnq_128B : 4168Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhnq_128B">; 4169 4170def int_hexagon_V6_vavghrnd : 4171Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">; 4172 4173def int_hexagon_V6_vavghrnd_128B : 4174Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">; 4175 4176def int_hexagon_V6_vtran2x2_map : 4177Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vtran2x2_map">; 4178 4179def int_hexagon_V6_vtran2x2_map_128B : 4180Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtran2x2_map_128B">; 4181 4182def int_hexagon_V6_vdelta : 4183Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">; 4184 4185def int_hexagon_V6_vdelta_128B : 4186Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">; 4187 4188def int_hexagon_V6_vgtuh_and : 4189Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_and">; 4190 4191def int_hexagon_V6_vgtuh_and_128B : 4192Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">; 4193 4194def int_hexagon_V6_vtmpyhb : 4195Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">; 4196 4197def int_hexagon_V6_vtmpyhb_128B : 4198Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">; 4199 4200def int_hexagon_V6_vpackob : 4201Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">; 4202 4203def int_hexagon_V6_vpackob_128B : 4204Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">; 4205 4206def int_hexagon_V6_vmaxh : 4207Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">; 4208 4209def int_hexagon_V6_vmaxh_128B : 4210Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">; 4211 4212def int_hexagon_V6_vtmpybus_acc : 4213Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">; 4214 4215def int_hexagon_V6_vtmpybus_acc_128B : 4216Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">; 4217 4218def int_hexagon_V6_vsubuhsat : 4219Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">; 4220 4221def int_hexagon_V6_vsubuhsat_128B : 4222Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">; 4223 4224def int_hexagon_V6_vasrw_acc : 4225Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">; 4226 4227def int_hexagon_V6_vasrw_acc_128B : 4228Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">; 4229 4230def int_hexagon_V6_pred_or : 4231Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or">; 4232 4233def int_hexagon_V6_pred_or_128B : 4234Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_128B">; 4235 4236def int_hexagon_V6_vrmpyub_acc : 4237Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">; 4238 4239def int_hexagon_V6_vrmpyub_acc_128B : 4240Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">; 4241 4242def int_hexagon_V6_lo : 4243Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">; 4244 4245def int_hexagon_V6_lo_128B : 4246Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">; 4247 4248def int_hexagon_V6_vsubb_dv : 4249Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">; 4250 4251def int_hexagon_V6_vsubb_dv_128B : 4252Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">; 4253 4254def int_hexagon_V6_vsubhsat_dv : 4255Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">; 4256 4257def int_hexagon_V6_vsubhsat_dv_128B : 4258Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">; 4259 4260def int_hexagon_V6_vmpyiwh : 4261Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">; 4262 4263def int_hexagon_V6_vmpyiwh_128B : 4264Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">; 4265 4266def int_hexagon_V6_vmpyiwb : 4267Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">; 4268 4269def int_hexagon_V6_vmpyiwb_128B : 4270Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">; 4271 4272def int_hexagon_V6_ldu0 : 4273Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldu0">; 4274 4275def int_hexagon_V6_ldu0_128B : 4276Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ldu0_128B">; 4277 4278def int_hexagon_V6_vgtuh_xor : 4279Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_xor">; 4280 4281def int_hexagon_V6_vgtuh_xor_128B : 4282Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">; 4283 4284def int_hexagon_V6_vgth_or : 4285Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_or">; 4286 4287def int_hexagon_V6_vgth_or_128B : 4288Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_or_128B">; 4289 4290def int_hexagon_V6_vavgh : 4291Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">; 4292 4293def int_hexagon_V6_vavgh_128B : 4294Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">; 4295 4296def int_hexagon_V6_vlalignb : 4297Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">; 4298 4299def int_hexagon_V6_vlalignb_128B : 4300Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">; 4301 4302def int_hexagon_V6_vsh : 4303Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">; 4304 4305def int_hexagon_V6_vsh_128B : 4306Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">; 4307 4308def int_hexagon_V6_pred_and_n : 4309Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and_n">; 4310 4311def int_hexagon_V6_pred_and_n_128B : 4312Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_n_128B">; 4313 4314def int_hexagon_V6_vsb : 4315Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">; 4316 4317def int_hexagon_V6_vsb_128B : 4318Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">; 4319 4320def int_hexagon_V6_vroundwuh : 4321Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">; 4322 4323def int_hexagon_V6_vroundwuh_128B : 4324Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">; 4325 4326def int_hexagon_V6_vasrhv : 4327Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">; 4328 4329def int_hexagon_V6_vasrhv_128B : 4330Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">; 4331 4332def int_hexagon_V6_vshuffh : 4333Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">; 4334 4335def int_hexagon_V6_vshuffh_128B : 4336Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">; 4337 4338def int_hexagon_V6_vaddhsat_dv : 4339Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">; 4340 4341def int_hexagon_V6_vaddhsat_dv_128B : 4342Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">; 4343 4344def int_hexagon_V6_vnavgub : 4345Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">; 4346 4347def int_hexagon_V6_vnavgub_128B : 4348Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">; 4349 4350def int_hexagon_V6_vrmpybv : 4351Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">; 4352 4353def int_hexagon_V6_vrmpybv_128B : 4354Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">; 4355 4356def int_hexagon_V6_vnormamth : 4357Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">; 4358 4359def int_hexagon_V6_vnormamth_128B : 4360Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">; 4361 4362def int_hexagon_V6_vdmpyhb : 4363Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb">; 4364 4365def int_hexagon_V6_vdmpyhb_128B : 4366Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">; 4367 4368def int_hexagon_V6_vavguh : 4369Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">; 4370 4371def int_hexagon_V6_vavguh_128B : 4372Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">; 4373 4374def int_hexagon_V6_vlsrwv : 4375Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">; 4376 4377def int_hexagon_V6_vlsrwv_128B : 4378Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">; 4379 4380def int_hexagon_V6_vlsrhv : 4381Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">; 4382 4383def int_hexagon_V6_vlsrhv_128B : 4384Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">; 4385 4386def int_hexagon_V6_vdmpyhisat : 4387Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">; 4388 4389def int_hexagon_V6_vdmpyhisat_128B : 4390Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">; 4391 4392def int_hexagon_V6_vdmpyhvsat : 4393Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">; 4394 4395def int_hexagon_V6_vdmpyhvsat_128B : 4396Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">; 4397 4398def int_hexagon_V6_vaddw : 4399Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">; 4400 4401def int_hexagon_V6_vaddw_128B : 4402Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">; 4403 4404def int_hexagon_V6_vzh : 4405Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">; 4406 4407def int_hexagon_V6_vzh_128B : 4408Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">; 4409 4410def int_hexagon_V6_vaddh : 4411Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">; 4412 4413def int_hexagon_V6_vaddh_128B : 4414Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">; 4415 4416def int_hexagon_V6_vmaxub : 4417Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">; 4418 4419def int_hexagon_V6_vmaxub_128B : 4420Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">; 4421 4422def int_hexagon_V6_vmpyhv_acc : 4423Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">; 4424 4425def int_hexagon_V6_vmpyhv_acc_128B : 4426Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">; 4427 4428def int_hexagon_V6_vadduhsat : 4429Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">; 4430 4431def int_hexagon_V6_vadduhsat_128B : 4432Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">; 4433 4434def int_hexagon_V6_vshufoeh : 4435Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">; 4436 4437def int_hexagon_V6_vshufoeh_128B : 4438Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">; 4439 4440def int_hexagon_V6_vmpyuhv_acc : 4441Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">; 4442 4443def int_hexagon_V6_vmpyuhv_acc_128B : 4444Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">; 4445 4446def int_hexagon_V6_veqh : 4447Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh">; 4448 4449def int_hexagon_V6_veqh_128B : 4450Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_128B">; 4451 4452def int_hexagon_V6_vmpabuuv : 4453Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">; 4454 4455def int_hexagon_V6_vmpabuuv_128B : 4456Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">; 4457 4458def int_hexagon_V6_vasrwhsat : 4459Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">; 4460 4461def int_hexagon_V6_vasrwhsat_128B : 4462Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">; 4463 4464def int_hexagon_V6_vminuh : 4465Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">; 4466 4467def int_hexagon_V6_vminuh_128B : 4468Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">; 4469 4470def int_hexagon_V6_vror : 4471Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">; 4472 4473def int_hexagon_V6_vror_128B : 4474Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">; 4475 4476def int_hexagon_V6_vmpyowh_rnd_sacc : 4477Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">; 4478 4479def int_hexagon_V6_vmpyowh_rnd_sacc_128B : 4480Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">; 4481 4482def int_hexagon_V6_vmaxuh : 4483Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">; 4484 4485def int_hexagon_V6_vmaxuh_128B : 4486Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">; 4487 4488def int_hexagon_V6_vabsh_sat : 4489Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">; 4490 4491def int_hexagon_V6_vabsh_sat_128B : 4492Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">; 4493 4494def int_hexagon_V6_pred_or_n : 4495Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or_n">; 4496 4497def int_hexagon_V6_pred_or_n_128B : 4498Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_n_128B">; 4499 4500def int_hexagon_V6_vdealb : 4501Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">; 4502 4503def int_hexagon_V6_vdealb_128B : 4504Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">; 4505 4506def int_hexagon_V6_vmpybusv : 4507Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">; 4508 4509def int_hexagon_V6_vmpybusv_128B : 4510Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">; 4511 4512def int_hexagon_V6_vzb : 4513Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">; 4514 4515def int_hexagon_V6_vzb_128B : 4516Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">; 4517 4518def int_hexagon_V6_vdmpybus_dv : 4519Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv">; 4520 4521def int_hexagon_V6_vdmpybus_dv_128B : 4522Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">; 4523 4524def int_hexagon_V6_vaddbq : 4525Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbq">; 4526 4527def int_hexagon_V6_vaddbq_128B : 4528Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbq_128B">; 4529 4530def int_hexagon_V6_vaddb : 4531Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">; 4532 4533def int_hexagon_V6_vaddb_128B : 4534Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">; 4535 4536def int_hexagon_V6_vaddwq : 4537Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwq">; 4538 4539def int_hexagon_V6_vaddwq_128B : 4540Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwq_128B">; 4541 4542def int_hexagon_V6_vasrhubrndsat : 4543Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">; 4544 4545def int_hexagon_V6_vasrhubrndsat_128B : 4546Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">; 4547 4548def int_hexagon_V6_vasrhubsat : 4549Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">; 4550 4551def int_hexagon_V6_vasrhubsat_128B : 4552Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">; 4553 4554def int_hexagon_V6_vshufoeb : 4555Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">; 4556 4557def int_hexagon_V6_vshufoeb_128B : 4558Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">; 4559 4560def int_hexagon_V6_vpackhub_sat : 4561Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">; 4562 4563def int_hexagon_V6_vpackhub_sat_128B : 4564Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">; 4565 4566def int_hexagon_V6_vmpyiwh_acc : 4567Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">; 4568 4569def int_hexagon_V6_vmpyiwh_acc_128B : 4570Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">; 4571 4572def int_hexagon_V6_vtmpyb : 4573Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">; 4574 4575def int_hexagon_V6_vtmpyb_128B : 4576Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">; 4577 4578def int_hexagon_V6_vmpabusv : 4579Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">; 4580 4581def int_hexagon_V6_vmpabusv_128B : 4582Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">; 4583 4584def int_hexagon_V6_pred_and : 4585Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and">; 4586 4587def int_hexagon_V6_pred_and_128B : 4588Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_128B">; 4589 4590def int_hexagon_V6_vsubwnq : 4591Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwnq">; 4592 4593def int_hexagon_V6_vsubwnq_128B : 4594Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwnq_128B">; 4595 4596def int_hexagon_V6_vpackwuh_sat : 4597Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">; 4598 4599def int_hexagon_V6_vpackwuh_sat_128B : 4600Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">; 4601 4602def int_hexagon_V6_vswap : 4603Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vswap">; 4604 4605def int_hexagon_V6_vswap_128B : 4606Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vswap_128B">; 4607 4608def int_hexagon_V6_vrmpyubv_acc : 4609Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">; 4610 4611def int_hexagon_V6_vrmpyubv_acc_128B : 4612Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">; 4613 4614def int_hexagon_V6_vgtb_and : 4615Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_and">; 4616 4617def int_hexagon_V6_vgtb_and_128B : 4618Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_and_128B">; 4619 4620def int_hexagon_V6_vaslw : 4621Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">; 4622 4623def int_hexagon_V6_vaslw_128B : 4624Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">; 4625 4626def int_hexagon_V6_vpackhb_sat : 4627Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">; 4628 4629def int_hexagon_V6_vpackhb_sat_128B : 4630Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">; 4631 4632def int_hexagon_V6_vmpyih_acc : 4633Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">; 4634 4635def int_hexagon_V6_vmpyih_acc_128B : 4636Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">; 4637 4638def int_hexagon_V6_vshuffvdd : 4639Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">; 4640 4641def int_hexagon_V6_vshuffvdd_128B : 4642Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">; 4643 4644def int_hexagon_V6_vaddb_dv : 4645Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">; 4646 4647def int_hexagon_V6_vaddb_dv_128B : 4648Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">; 4649 4650def int_hexagon_V6_vunpackub : 4651Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">; 4652 4653def int_hexagon_V6_vunpackub_128B : 4654Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">; 4655 4656def int_hexagon_V6_vgtuw : 4657Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw">; 4658 4659def int_hexagon_V6_vgtuw_128B : 4660Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_128B">; 4661 4662def int_hexagon_V6_vlutvwh : 4663Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">; 4664 4665def int_hexagon_V6_vlutvwh_128B : 4666Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">; 4667 4668def int_hexagon_V6_vgtub : 4669Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub">; 4670 4671def int_hexagon_V6_vgtub_128B : 4672Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_128B">; 4673 4674def int_hexagon_V6_vmpyowh : 4675Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">; 4676 4677def int_hexagon_V6_vmpyowh_128B : 4678Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">; 4679 4680def int_hexagon_V6_vmpyieoh : 4681Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">; 4682 4683def int_hexagon_V6_vmpyieoh_128B : 4684Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">; 4685 4686def int_hexagon_V6_extractw : 4687Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">; 4688 4689def int_hexagon_V6_extractw_128B : 4690Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">; 4691 4692def int_hexagon_V6_vavgwrnd : 4693Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">; 4694 4695def int_hexagon_V6_vavgwrnd_128B : 4696Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">; 4697 4698def int_hexagon_V6_vdmpyhsat_acc : 4699Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">; 4700 4701def int_hexagon_V6_vdmpyhsat_acc_128B : 4702Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">; 4703 4704def int_hexagon_V6_vgtub_xor : 4705Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_xor">; 4706 4707def int_hexagon_V6_vgtub_xor_128B : 4708Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">; 4709 4710def int_hexagon_V6_vmpyub : 4711Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">; 4712 4713def int_hexagon_V6_vmpyub_128B : 4714Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">; 4715 4716def int_hexagon_V6_vmpyuh : 4717Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">; 4718 4719def int_hexagon_V6_vmpyuh_128B : 4720Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">; 4721 4722def int_hexagon_V6_vunpackob : 4723Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">; 4724 4725def int_hexagon_V6_vunpackob_128B : 4726Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">; 4727 4728def int_hexagon_V6_vmpahb : 4729Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">; 4730 4731def int_hexagon_V6_vmpahb_128B : 4732Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">; 4733 4734def int_hexagon_V6_veqw_or : 4735Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_or">; 4736 4737def int_hexagon_V6_veqw_or_128B : 4738Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_or_128B">; 4739 4740def int_hexagon_V6_vandqrt : 4741Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt">; 4742 4743def int_hexagon_V6_vandqrt_128B : 4744Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_128B">; 4745 4746def int_hexagon_V6_vxor : 4747Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">; 4748 4749def int_hexagon_V6_vxor_128B : 4750Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">; 4751 4752def int_hexagon_V6_vasrwhrndsat : 4753Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">; 4754 4755def int_hexagon_V6_vasrwhrndsat_128B : 4756Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">; 4757 4758def int_hexagon_V6_vmpyhsat_acc : 4759Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">; 4760 4761def int_hexagon_V6_vmpyhsat_acc_128B : 4762Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">; 4763 4764def int_hexagon_V6_vrmpybus_acc : 4765Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc">; 4766 4767def int_hexagon_V6_vrmpybus_acc_128B : 4768Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">; 4769 4770def int_hexagon_V6_vsubhw : 4771Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">; 4772 4773def int_hexagon_V6_vsubhw_128B : 4774Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">; 4775 4776def int_hexagon_V6_vdealb4w : 4777Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">; 4778 4779def int_hexagon_V6_vdealb4w_128B : 4780Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">; 4781 4782def int_hexagon_V6_vmpyowh_sacc : 4783Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">; 4784 4785def int_hexagon_V6_vmpyowh_sacc_128B : 4786Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">; 4787 4788def int_hexagon_V6_vmpybv : 4789Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">; 4790 4791def int_hexagon_V6_vmpybv_128B : 4792Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">; 4793 4794def int_hexagon_V6_vabsdiffh : 4795Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">; 4796 4797def int_hexagon_V6_vabsdiffh_128B : 4798Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">; 4799 4800def int_hexagon_V6_vshuffob : 4801Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">; 4802 4803def int_hexagon_V6_vshuffob_128B : 4804Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">; 4805 4806def int_hexagon_V6_vmpyub_acc : 4807Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">; 4808 4809def int_hexagon_V6_vmpyub_acc_128B : 4810Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">; 4811 4812def int_hexagon_V6_vnormamtw : 4813Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">; 4814 4815def int_hexagon_V6_vnormamtw_128B : 4816Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">; 4817 4818def int_hexagon_V6_vunpackuh : 4819Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">; 4820 4821def int_hexagon_V6_vunpackuh_128B : 4822Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">; 4823 4824def int_hexagon_V6_vgtuh_or : 4825Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_or">; 4826 4827def int_hexagon_V6_vgtuh_or_128B : 4828Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">; 4829 4830def int_hexagon_V6_vmpyiewuh_acc : 4831Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">; 4832 4833def int_hexagon_V6_vmpyiewuh_acc_128B : 4834Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">; 4835 4836def int_hexagon_V6_vunpackoh : 4837Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">; 4838 4839def int_hexagon_V6_vunpackoh_128B : 4840Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">; 4841 4842def int_hexagon_V6_vdmpyhsat : 4843Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">; 4844 4845def int_hexagon_V6_vdmpyhsat_128B : 4846Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">; 4847 4848def int_hexagon_V6_vmpyubv : 4849Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">; 4850 4851def int_hexagon_V6_vmpyubv_128B : 4852Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">; 4853 4854def int_hexagon_V6_vmpyhss : 4855Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">; 4856 4857def int_hexagon_V6_vmpyhss_128B : 4858Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">; 4859 4860def int_hexagon_V6_hi : 4861Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">; 4862 4863def int_hexagon_V6_hi_128B : 4864Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">; 4865 4866def int_hexagon_V6_vasrwuhsat : 4867Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">; 4868 4869def int_hexagon_V6_vasrwuhsat_128B : 4870Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">; 4871 4872def int_hexagon_V6_veqw : 4873Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw">; 4874 4875def int_hexagon_V6_veqw_128B : 4876Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_128B">; 4877 4878def int_hexagon_V6_vdsaduh : 4879Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">; 4880 4881def int_hexagon_V6_vdsaduh_128B : 4882Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">; 4883 4884def int_hexagon_V6_vsubw : 4885Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">; 4886 4887def int_hexagon_V6_vsubw_128B : 4888Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">; 4889 4890def int_hexagon_V6_vsubw_dv : 4891Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">; 4892 4893def int_hexagon_V6_vsubw_dv_128B : 4894Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">; 4895 4896def int_hexagon_V6_veqb_and : 4897Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_and">; 4898 4899def int_hexagon_V6_veqb_and_128B : 4900Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_and_128B">; 4901 4902def int_hexagon_V6_vmpyih : 4903Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">; 4904 4905def int_hexagon_V6_vmpyih_128B : 4906Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">; 4907 4908def int_hexagon_V6_vtmpyb_acc : 4909Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">; 4910 4911def int_hexagon_V6_vtmpyb_acc_128B : 4912Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">; 4913 4914def int_hexagon_V6_vrmpybus : 4915Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">; 4916 4917def int_hexagon_V6_vrmpybus_128B : 4918Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_128B">; 4919 4920def int_hexagon_V6_vmpybus_acc : 4921Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">; 4922 4923def int_hexagon_V6_vmpybus_acc_128B : 4924Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">; 4925 4926def int_hexagon_V6_vgth_xor : 4927Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_xor">; 4928 4929def int_hexagon_V6_vgth_xor_128B : 4930Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_xor_128B">; 4931 4932def int_hexagon_V6_vsubhsat : 4933Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">; 4934 4935def int_hexagon_V6_vsubhsat_128B : 4936Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">; 4937 4938def int_hexagon_V6_vrmpyubi_acc : 4939Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [ImmArg<3>]>; 4940 4941def int_hexagon_V6_vrmpyubi_acc_128B : 4942Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [ImmArg<3>]>; 4943 4944def int_hexagon_V6_vabsw : 4945Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">; 4946 4947def int_hexagon_V6_vabsw_128B : 4948Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">; 4949 4950def int_hexagon_V6_vaddwsat_dv : 4951Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">; 4952 4953def int_hexagon_V6_vaddwsat_dv_128B : 4954Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">; 4955 4956def int_hexagon_V6_vlsrw : 4957Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">; 4958 4959def int_hexagon_V6_vlsrw_128B : 4960Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">; 4961 4962def int_hexagon_V6_vabsh : 4963Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">; 4964 4965def int_hexagon_V6_vabsh_128B : 4966Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">; 4967 4968def int_hexagon_V6_vlsrh : 4969Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">; 4970 4971def int_hexagon_V6_vlsrh_128B : 4972Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">; 4973 4974def int_hexagon_V6_valignb : 4975Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">; 4976 4977def int_hexagon_V6_valignb_128B : 4978Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">; 4979 4980def int_hexagon_V6_vsubhq : 4981Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhq">; 4982 4983def int_hexagon_V6_vsubhq_128B : 4984Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhq_128B">; 4985 4986def int_hexagon_V6_vpackoh : 4987Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">; 4988 4989def int_hexagon_V6_vpackoh_128B : 4990Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">; 4991 4992def int_hexagon_V6_vdmpybus_acc : 4993Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc">; 4994 4995def int_hexagon_V6_vdmpybus_acc_128B : 4996Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">; 4997 4998def int_hexagon_V6_vdmpyhvsat_acc : 4999Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">; 5000 5001def int_hexagon_V6_vdmpyhvsat_acc_128B : 5002Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">; 5003 5004def int_hexagon_V6_vrmpybv_acc : 5005Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">; 5006 5007def int_hexagon_V6_vrmpybv_acc_128B : 5008Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">; 5009 5010def int_hexagon_V6_vaddhsat : 5011Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">; 5012 5013def int_hexagon_V6_vaddhsat_128B : 5014Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">; 5015 5016def int_hexagon_V6_vcombine : 5017Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">; 5018 5019def int_hexagon_V6_vcombine_128B : 5020Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">; 5021 5022def int_hexagon_V6_vandqrt_acc : 5023Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc">; 5024 5025def int_hexagon_V6_vandqrt_acc_128B : 5026Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">; 5027 5028def int_hexagon_V6_vaslhv : 5029Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">; 5030 5031def int_hexagon_V6_vaslhv_128B : 5032Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">; 5033 5034def int_hexagon_V6_vinsertwr : 5035Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">; 5036 5037def int_hexagon_V6_vinsertwr_128B : 5038Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">; 5039 5040def int_hexagon_V6_vsubh_dv : 5041Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">; 5042 5043def int_hexagon_V6_vsubh_dv_128B : 5044Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">; 5045 5046def int_hexagon_V6_vshuffb : 5047Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">; 5048 5049def int_hexagon_V6_vshuffb_128B : 5050Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">; 5051 5052def int_hexagon_V6_vand : 5053Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">; 5054 5055def int_hexagon_V6_vand_128B : 5056Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">; 5057 5058def int_hexagon_V6_vmpyhv : 5059Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">; 5060 5061def int_hexagon_V6_vmpyhv_128B : 5062Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">; 5063 5064def int_hexagon_V6_vdmpyhsuisat_acc : 5065Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">; 5066 5067def int_hexagon_V6_vdmpyhsuisat_acc_128B : 5068Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">; 5069 5070def int_hexagon_V6_vsububsat_dv : 5071Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">; 5072 5073def int_hexagon_V6_vsububsat_dv_128B : 5074Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">; 5075 5076def int_hexagon_V6_vgtb_xor : 5077Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_xor">; 5078 5079def int_hexagon_V6_vgtb_xor_128B : 5080Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">; 5081 5082def int_hexagon_V6_vdsaduh_acc : 5083Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">; 5084 5085def int_hexagon_V6_vdsaduh_acc_128B : 5086Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">; 5087 5088def int_hexagon_V6_vrmpyub : 5089Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">; 5090 5091def int_hexagon_V6_vrmpyub_128B : 5092Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">; 5093 5094def int_hexagon_V6_vmpyuh_acc : 5095Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">; 5096 5097def int_hexagon_V6_vmpyuh_acc_128B : 5098Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">; 5099 5100def int_hexagon_V6_vcl0h : 5101Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">; 5102 5103def int_hexagon_V6_vcl0h_128B : 5104Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">; 5105 5106def int_hexagon_V6_vmpyhus_acc : 5107Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">; 5108 5109def int_hexagon_V6_vmpyhus_acc_128B : 5110Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">; 5111 5112def int_hexagon_V6_vmpybv_acc : 5113Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">; 5114 5115def int_hexagon_V6_vmpybv_acc_128B : 5116Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">; 5117 5118def int_hexagon_V6_vrsadubi : 5119Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [ImmArg<2>]>; 5120 5121def int_hexagon_V6_vrsadubi_128B : 5122Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [ImmArg<2>]>; 5123 5124def int_hexagon_V6_vdmpyhb_dv_acc : 5125Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">; 5126 5127def int_hexagon_V6_vdmpyhb_dv_acc_128B : 5128Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">; 5129 5130def int_hexagon_V6_vshufeh : 5131Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">; 5132 5133def int_hexagon_V6_vshufeh_128B : 5134Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">; 5135 5136def int_hexagon_V6_vmpyewuh : 5137Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">; 5138 5139def int_hexagon_V6_vmpyewuh_128B : 5140Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">; 5141 5142def int_hexagon_V6_vmpyhsrs : 5143Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">; 5144 5145def int_hexagon_V6_vmpyhsrs_128B : 5146Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">; 5147 5148def int_hexagon_V6_vdmpybus_dv_acc : 5149Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">; 5150 5151def int_hexagon_V6_vdmpybus_dv_acc_128B : 5152Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">; 5153 5154def int_hexagon_V6_vaddubh : 5155Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">; 5156 5157def int_hexagon_V6_vaddubh_128B : 5158Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">; 5159 5160def int_hexagon_V6_vasrwh : 5161Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">; 5162 5163def int_hexagon_V6_vasrwh_128B : 5164Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">; 5165 5166def int_hexagon_V6_ld0 : 5167Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ld0">; 5168 5169def int_hexagon_V6_ld0_128B : 5170Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ld0_128B">; 5171 5172def int_hexagon_V6_vpopcounth : 5173Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">; 5174 5175def int_hexagon_V6_vpopcounth_128B : 5176Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">; 5177 5178def int_hexagon_V6_ldnt0 : 5179Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldnt0">; 5180 5181def int_hexagon_V6_ldnt0_128B : 5182Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ldnt0_128B">; 5183 5184def int_hexagon_V6_vgth_and : 5185Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_and">; 5186 5187def int_hexagon_V6_vgth_and_128B : 5188Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_and_128B">; 5189 5190def int_hexagon_V6_vaddubsat_dv : 5191Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">; 5192 5193def int_hexagon_V6_vaddubsat_dv_128B : 5194Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">; 5195 5196def int_hexagon_V6_vpackeh : 5197Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">; 5198 5199def int_hexagon_V6_vpackeh_128B : 5200Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">; 5201 5202def int_hexagon_V6_vmpyh : 5203Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">; 5204 5205def int_hexagon_V6_vmpyh_128B : 5206Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">; 5207 5208def int_hexagon_V6_vminh : 5209Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">; 5210 5211def int_hexagon_V6_vminh_128B : 5212Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">; 5213 5214def int_hexagon_V6_pred_scalar2 : 5215Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2">; 5216 5217def int_hexagon_V6_pred_scalar2_128B : 5218Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">; 5219 5220def int_hexagon_V6_vdealh : 5221Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">; 5222 5223def int_hexagon_V6_vdealh_128B : 5224Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">; 5225 5226def int_hexagon_V6_vpackwh_sat : 5227Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">; 5228 5229def int_hexagon_V6_vpackwh_sat_128B : 5230Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">; 5231 5232def int_hexagon_V6_vaslh : 5233Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">; 5234 5235def int_hexagon_V6_vaslh_128B : 5236Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">; 5237 5238def int_hexagon_V6_vgtuw_and : 5239Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_and">; 5240 5241def int_hexagon_V6_vgtuw_and_128B : 5242Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">; 5243 5244def int_hexagon_V6_vor : 5245Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">; 5246 5247def int_hexagon_V6_vor_128B : 5248Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">; 5249 5250def int_hexagon_V6_vlutvvb : 5251Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">; 5252 5253def int_hexagon_V6_vlutvvb_128B : 5254Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">; 5255 5256def int_hexagon_V6_vmpyiowh : 5257Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">; 5258 5259def int_hexagon_V6_vmpyiowh_128B : 5260Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">; 5261 5262def int_hexagon_V6_vlutvvb_oracc : 5263Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">; 5264 5265def int_hexagon_V6_vlutvvb_oracc_128B : 5266Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">; 5267 5268def int_hexagon_V6_vandvrt : 5269Hexagon_v512i1_v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt">; 5270 5271def int_hexagon_V6_vandvrt_128B : 5272Hexagon_v1024i1_v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_128B">; 5273 5274def int_hexagon_V6_veqh_xor : 5275Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_xor">; 5276 5277def int_hexagon_V6_veqh_xor_128B : 5278Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_xor_128B">; 5279 5280def int_hexagon_V6_vadduhw : 5281Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">; 5282 5283def int_hexagon_V6_vadduhw_128B : 5284Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">; 5285 5286def int_hexagon_V6_vcl0w : 5287Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">; 5288 5289def int_hexagon_V6_vcl0w_128B : 5290Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">; 5291 5292def int_hexagon_V6_vmpyihb : 5293Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">; 5294 5295def int_hexagon_V6_vmpyihb_128B : 5296Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">; 5297 5298def int_hexagon_V6_vtmpybus : 5299Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">; 5300 5301def int_hexagon_V6_vtmpybus_128B : 5302Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">; 5303 5304def int_hexagon_V6_vd0 : 5305Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">; 5306 5307def int_hexagon_V6_vd0_128B : 5308Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">; 5309 5310def int_hexagon_V6_veqh_or : 5311Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_or">; 5312 5313def int_hexagon_V6_veqh_or_128B : 5314Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_or_128B">; 5315 5316def int_hexagon_V6_vgtw_or : 5317Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_or">; 5318 5319def int_hexagon_V6_vgtw_or_128B : 5320Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_or_128B">; 5321 5322def int_hexagon_V6_vdmpybus : 5323Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">; 5324 5325def int_hexagon_V6_vdmpybus_128B : 5326Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_128B">; 5327 5328def int_hexagon_V6_vgtub_or : 5329Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_or">; 5330 5331def int_hexagon_V6_vgtub_or_128B : 5332Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_or_128B">; 5333 5334def int_hexagon_V6_vmpybus : 5335Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">; 5336 5337def int_hexagon_V6_vmpybus_128B : 5338Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">; 5339 5340def int_hexagon_V6_vdmpyhb_acc : 5341Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">; 5342 5343def int_hexagon_V6_vdmpyhb_acc_128B : 5344Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">; 5345 5346def int_hexagon_V6_vandvrt_acc : 5347Hexagon_v512i1_v512i1v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc">; 5348 5349def int_hexagon_V6_vandvrt_acc_128B : 5350Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">; 5351 5352def int_hexagon_V6_vassign : 5353Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">; 5354 5355def int_hexagon_V6_vassign_128B : 5356Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">; 5357 5358def int_hexagon_V6_vaddwnq : 5359Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwnq">; 5360 5361def int_hexagon_V6_vaddwnq_128B : 5362Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwnq_128B">; 5363 5364def int_hexagon_V6_vgtub_and : 5365Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_and">; 5366 5367def int_hexagon_V6_vgtub_and_128B : 5368Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_and_128B">; 5369 5370def int_hexagon_V6_vdmpyhb_dv : 5371Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">; 5372 5373def int_hexagon_V6_vdmpyhb_dv_128B : 5374Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">; 5375 5376def int_hexagon_V6_vunpackb : 5377Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">; 5378 5379def int_hexagon_V6_vunpackb_128B : 5380Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">; 5381 5382def int_hexagon_V6_vunpackh : 5383Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">; 5384 5385def int_hexagon_V6_vunpackh_128B : 5386Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">; 5387 5388def int_hexagon_V6_vmpahb_acc : 5389Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">; 5390 5391def int_hexagon_V6_vmpahb_acc_128B : 5392Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">; 5393 5394def int_hexagon_V6_vaddbnq : 5395Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbnq">; 5396 5397def int_hexagon_V6_vaddbnq_128B : 5398Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbnq_128B">; 5399 5400def int_hexagon_V6_vlalignbi : 5401Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [ImmArg<2>]>; 5402 5403def int_hexagon_V6_vlalignbi_128B : 5404Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [ImmArg<2>]>; 5405 5406def int_hexagon_V6_vsatwh : 5407Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">; 5408 5409def int_hexagon_V6_vsatwh_128B : 5410Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">; 5411 5412def int_hexagon_V6_vgtuh : 5413Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh">; 5414 5415def int_hexagon_V6_vgtuh_128B : 5416Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_128B">; 5417 5418def int_hexagon_V6_vmpyihb_acc : 5419Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">; 5420 5421def int_hexagon_V6_vmpyihb_acc_128B : 5422Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">; 5423 5424def int_hexagon_V6_vrmpybusv_acc : 5425Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">; 5426 5427def int_hexagon_V6_vrmpybusv_acc_128B : 5428Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">; 5429 5430def int_hexagon_V6_vrdelta : 5431Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">; 5432 5433def int_hexagon_V6_vrdelta_128B : 5434Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">; 5435 5436def int_hexagon_V6_vroundwh : 5437Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">; 5438 5439def int_hexagon_V6_vroundwh_128B : 5440Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">; 5441 5442def int_hexagon_V6_vaddw_dv : 5443Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">; 5444 5445def int_hexagon_V6_vaddw_dv_128B : 5446Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">; 5447 5448def int_hexagon_V6_vmpyiwb_acc : 5449Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">; 5450 5451def int_hexagon_V6_vmpyiwb_acc_128B : 5452Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">; 5453 5454def int_hexagon_V6_vsubbq : 5455Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbq">; 5456 5457def int_hexagon_V6_vsubbq_128B : 5458Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbq_128B">; 5459 5460def int_hexagon_V6_veqh_and : 5461Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_and">; 5462 5463def int_hexagon_V6_veqh_and_128B : 5464Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_and_128B">; 5465 5466def int_hexagon_V6_valignbi : 5467Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi", [ImmArg<2>]>; 5468 5469def int_hexagon_V6_valignbi_128B : 5470Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B", [ImmArg<2>]>; 5471 5472def int_hexagon_V6_vaddwsat : 5473Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">; 5474 5475def int_hexagon_V6_vaddwsat_128B : 5476Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">; 5477 5478def int_hexagon_V6_veqw_and : 5479Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_and">; 5480 5481def int_hexagon_V6_veqw_and_128B : 5482Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_and_128B">; 5483 5484def int_hexagon_V6_vabsdiffub : 5485Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffub">; 5486 5487def int_hexagon_V6_vabsdiffub_128B : 5488Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">; 5489 5490def int_hexagon_V6_vshuffeb : 5491Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">; 5492 5493def int_hexagon_V6_vshuffeb_128B : 5494Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">; 5495 5496def int_hexagon_V6_vabsdiffuh : 5497Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffuh">; 5498 5499def int_hexagon_V6_vabsdiffuh_128B : 5500Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">; 5501 5502def int_hexagon_V6_veqw_xor : 5503Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_xor">; 5504 5505def int_hexagon_V6_veqw_xor_128B : 5506Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_xor_128B">; 5507 5508def int_hexagon_V6_vgth : 5509Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth">; 5510 5511def int_hexagon_V6_vgth_128B : 5512Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_128B">; 5513 5514def int_hexagon_V6_vgtuw_xor : 5515Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_xor">; 5516 5517def int_hexagon_V6_vgtuw_xor_128B : 5518Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">; 5519 5520def int_hexagon_V6_vgtb : 5521Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb">; 5522 5523def int_hexagon_V6_vgtb_128B : 5524Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_128B">; 5525 5526def int_hexagon_V6_vgtw : 5527Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw">; 5528 5529def int_hexagon_V6_vgtw_128B : 5530Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_128B">; 5531 5532def int_hexagon_V6_vsubwq : 5533Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwq">; 5534 5535def int_hexagon_V6_vsubwq_128B : 5536Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwq_128B">; 5537 5538def int_hexagon_V6_vnot : 5539Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">; 5540 5541def int_hexagon_V6_vnot_128B : 5542Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">; 5543 5544def int_hexagon_V6_vgtb_or : 5545Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_or">; 5546 5547def int_hexagon_V6_vgtb_or_128B : 5548Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_or_128B">; 5549 5550def int_hexagon_V6_vgtuw_or : 5551Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_or">; 5552 5553def int_hexagon_V6_vgtuw_or_128B : 5554Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">; 5555 5556def int_hexagon_V6_vaddubsat : 5557Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">; 5558 5559def int_hexagon_V6_vaddubsat_128B : 5560Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">; 5561 5562def int_hexagon_V6_vmaxw : 5563Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">; 5564 5565def int_hexagon_V6_vmaxw_128B : 5566Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">; 5567 5568def int_hexagon_V6_vaslwv : 5569Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">; 5570 5571def int_hexagon_V6_vaslwv_128B : 5572Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">; 5573 5574def int_hexagon_V6_vabsw_sat : 5575Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">; 5576 5577def int_hexagon_V6_vabsw_sat_128B : 5578Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">; 5579 5580def int_hexagon_V6_vsubwsat_dv : 5581Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">; 5582 5583def int_hexagon_V6_vsubwsat_dv_128B : 5584Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">; 5585 5586def int_hexagon_V6_vroundhub : 5587Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">; 5588 5589def int_hexagon_V6_vroundhub_128B : 5590Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">; 5591 5592def int_hexagon_V6_vdmpyhisat_acc : 5593Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">; 5594 5595def int_hexagon_V6_vdmpyhisat_acc_128B : 5596Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">; 5597 5598def int_hexagon_V6_vmpabus : 5599Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">; 5600 5601def int_hexagon_V6_vmpabus_128B : 5602Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">; 5603 5604def int_hexagon_V6_vassignp : 5605Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">; 5606 5607def int_hexagon_V6_vassignp_128B : 5608Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">; 5609 5610def int_hexagon_V6_veqb : 5611Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb">; 5612 5613def int_hexagon_V6_veqb_128B : 5614Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_128B">; 5615 5616def int_hexagon_V6_vsububh : 5617Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">; 5618 5619def int_hexagon_V6_vsububh_128B : 5620Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">; 5621 5622def int_hexagon_V6_lvsplatw : 5623Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">; 5624 5625def int_hexagon_V6_lvsplatw_128B : 5626Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">; 5627 5628def int_hexagon_V6_vaddhnq : 5629Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhnq">; 5630 5631def int_hexagon_V6_vaddhnq_128B : 5632Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhnq_128B">; 5633 5634def int_hexagon_V6_vdmpyhsusat : 5635Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">; 5636 5637def int_hexagon_V6_vdmpyhsusat_128B : 5638Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">; 5639 5640def int_hexagon_V6_pred_not : 5641Hexagon_v512i1_v512i1_Intrinsic<"HEXAGON_V6_pred_not">; 5642 5643def int_hexagon_V6_pred_not_128B : 5644Hexagon_v1024i1_v1024i1_Intrinsic<"HEXAGON_V6_pred_not_128B">; 5645 5646def int_hexagon_V6_vlutvwh_oracc : 5647Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">; 5648 5649def int_hexagon_V6_vlutvwh_oracc_128B : 5650Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">; 5651 5652def int_hexagon_V6_vmpyiewh_acc : 5653Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">; 5654 5655def int_hexagon_V6_vmpyiewh_acc_128B : 5656Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">; 5657 5658def int_hexagon_V6_vdealvdd : 5659Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">; 5660 5661def int_hexagon_V6_vdealvdd_128B : 5662Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">; 5663 5664def int_hexagon_V6_vavgw : 5665Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">; 5666 5667def int_hexagon_V6_vavgw_128B : 5668Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">; 5669 5670def int_hexagon_V6_vdmpyhsusat_acc : 5671Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">; 5672 5673def int_hexagon_V6_vdmpyhsusat_acc_128B : 5674Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">; 5675 5676def int_hexagon_V6_vgtw_xor : 5677Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_xor">; 5678 5679def int_hexagon_V6_vgtw_xor_128B : 5680Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">; 5681 5682def int_hexagon_V6_vtmpyhb_acc : 5683Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">; 5684 5685def int_hexagon_V6_vtmpyhb_acc_128B : 5686Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">; 5687 5688def int_hexagon_V6_vaddhw : 5689Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">; 5690 5691def int_hexagon_V6_vaddhw_128B : 5692Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">; 5693 5694def int_hexagon_V6_vaddhq : 5695Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhq">; 5696 5697def int_hexagon_V6_vaddhq_128B : 5698Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhq_128B">; 5699 5700def int_hexagon_V6_vrmpyubv : 5701Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">; 5702 5703def int_hexagon_V6_vrmpyubv_128B : 5704Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">; 5705 5706def int_hexagon_V6_vsubh : 5707Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">; 5708 5709def int_hexagon_V6_vsubh_128B : 5710Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">; 5711 5712def int_hexagon_V6_vrmpyubi : 5713Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [ImmArg<2>]>; 5714 5715def int_hexagon_V6_vrmpyubi_128B : 5716Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [ImmArg<2>]>; 5717 5718def int_hexagon_V6_vminw : 5719Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">; 5720 5721def int_hexagon_V6_vminw_128B : 5722Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">; 5723 5724def int_hexagon_V6_vmpyubv_acc : 5725Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">; 5726 5727def int_hexagon_V6_vmpyubv_acc_128B : 5728Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">; 5729 5730def int_hexagon_V6_pred_xor : 5731Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_xor">; 5732 5733def int_hexagon_V6_pred_xor_128B : 5734Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_xor_128B">; 5735 5736def int_hexagon_V6_veqb_xor : 5737Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_xor">; 5738 5739def int_hexagon_V6_veqb_xor_128B : 5740Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_xor_128B">; 5741 5742def int_hexagon_V6_vmpyiewuh : 5743Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">; 5744 5745def int_hexagon_V6_vmpyiewuh_128B : 5746Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">; 5747 5748def int_hexagon_V6_vmpybusv_acc : 5749Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">; 5750 5751def int_hexagon_V6_vmpybusv_acc_128B : 5752Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">; 5753 5754def int_hexagon_V6_vavguhrnd : 5755Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">; 5756 5757def int_hexagon_V6_vavguhrnd_128B : 5758Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">; 5759 5760def int_hexagon_V6_vmpyowh_rnd : 5761Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">; 5762 5763def int_hexagon_V6_vmpyowh_rnd_128B : 5764Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">; 5765 5766def int_hexagon_V6_vsubwsat : 5767Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">; 5768 5769def int_hexagon_V6_vsubwsat_128B : 5770Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">; 5771 5772def int_hexagon_V6_vsubuhw : 5773Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">; 5774 5775def int_hexagon_V6_vsubuhw_128B : 5776Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">; 5777 5778def int_hexagon_V6_vrmpybusi_acc : 5779Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc", [ImmArg<3>]>; 5780 5781def int_hexagon_V6_vrmpybusi_acc_128B : 5782Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B", [ImmArg<3>]>; 5783 5784def int_hexagon_V6_vasrw : 5785Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">; 5786 5787def int_hexagon_V6_vasrw_128B : 5788Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">; 5789 5790def int_hexagon_V6_vasrh : 5791Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">; 5792 5793def int_hexagon_V6_vasrh_128B : 5794Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">; 5795 5796def int_hexagon_V6_vmpyuhv : 5797Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">; 5798 5799def int_hexagon_V6_vmpyuhv_128B : 5800Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">; 5801 5802def int_hexagon_V6_vasrhbrndsat : 5803Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">; 5804 5805def int_hexagon_V6_vasrhbrndsat_128B : 5806Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">; 5807 5808def int_hexagon_V6_vsubuhsat_dv : 5809Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">; 5810 5811def int_hexagon_V6_vsubuhsat_dv_128B : 5812Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">; 5813 5814def int_hexagon_V6_vabsdiffw : 5815Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffw">; 5816 5817def int_hexagon_V6_vabsdiffw_128B : 5818Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">; 5819 5820// V62 HVX Instructions. 5821 5822def int_hexagon_V6_vandnqrt_acc : 5823Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc">; 5824 5825def int_hexagon_V6_vandnqrt_acc_128B : 5826Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">; 5827 5828def int_hexagon_V6_vaddclbh : 5829Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">; 5830 5831def int_hexagon_V6_vaddclbh_128B : 5832Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">; 5833 5834def int_hexagon_V6_vmpyowh_64_acc : 5835Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">; 5836 5837def int_hexagon_V6_vmpyowh_64_acc_128B : 5838Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">; 5839 5840def int_hexagon_V6_vmpyewuh_64 : 5841Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">; 5842 5843def int_hexagon_V6_vmpyewuh_64_128B : 5844Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">; 5845 5846def int_hexagon_V6_vsatuwuh : 5847Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">; 5848 5849def int_hexagon_V6_vsatuwuh_128B : 5850Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">; 5851 5852def int_hexagon_V6_shuffeqh : 5853Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqh">; 5854 5855def int_hexagon_V6_shuffeqh_128B : 5856Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqh_128B">; 5857 5858def int_hexagon_V6_shuffeqw : 5859Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqw">; 5860 5861def int_hexagon_V6_shuffeqw_128B : 5862Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqw_128B">; 5863 5864def int_hexagon_V6_ldcnpnt0 : 5865Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnpnt0">; 5866 5867def int_hexagon_V6_ldcnpnt0_128B : 5868Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnpnt0_128B">; 5869 5870def int_hexagon_V6_vsubcarry : 5871Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic; 5872 5873def int_hexagon_V6_vsubcarry_128B : 5874Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B; 5875 5876def int_hexagon_V6_vasrhbsat : 5877Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">; 5878 5879def int_hexagon_V6_vasrhbsat_128B : 5880Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">; 5881 5882def int_hexagon_V6_vminb : 5883Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">; 5884 5885def int_hexagon_V6_vminb_128B : 5886Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">; 5887 5888def int_hexagon_V6_vmpauhb_acc : 5889Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">; 5890 5891def int_hexagon_V6_vmpauhb_acc_128B : 5892Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">; 5893 5894def int_hexagon_V6_vaddhw_acc : 5895Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">; 5896 5897def int_hexagon_V6_vaddhw_acc_128B : 5898Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">; 5899 5900def int_hexagon_V6_vlsrb : 5901Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">; 5902 5903def int_hexagon_V6_vlsrb_128B : 5904Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">; 5905 5906def int_hexagon_V6_vlutvwhi : 5907Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [ImmArg<2>]>; 5908 5909def int_hexagon_V6_vlutvwhi_128B : 5910Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [ImmArg<2>]>; 5911 5912def int_hexagon_V6_vaddububb_sat : 5913Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">; 5914 5915def int_hexagon_V6_vaddububb_sat_128B : 5916Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">; 5917 5918def int_hexagon_V6_vsubbsat_dv : 5919Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">; 5920 5921def int_hexagon_V6_vsubbsat_dv_128B : 5922Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">; 5923 5924def int_hexagon_V6_ldtp0 : 5925Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0">; 5926 5927def int_hexagon_V6_ldtp0_128B : 5928Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0_128B">; 5929 5930def int_hexagon_V6_vlutvvb_oracci : 5931Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [ImmArg<3>]>; 5932 5933def int_hexagon_V6_vlutvvb_oracci_128B : 5934Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [ImmArg<3>]>; 5935 5936def int_hexagon_V6_vsubuwsat_dv : 5937Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">; 5938 5939def int_hexagon_V6_vsubuwsat_dv_128B : 5940Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">; 5941 5942def int_hexagon_V6_ldpnt0 : 5943Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldpnt0">; 5944 5945def int_hexagon_V6_ldpnt0_128B : 5946Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldpnt0_128B">; 5947 5948def int_hexagon_V6_vandvnqv : 5949Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvnqv">; 5950 5951def int_hexagon_V6_vandvnqv_128B : 5952Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvnqv_128B">; 5953 5954def int_hexagon_V6_lvsplatb : 5955Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">; 5956 5957def int_hexagon_V6_lvsplatb_128B : 5958Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">; 5959 5960def int_hexagon_V6_lvsplath : 5961Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">; 5962 5963def int_hexagon_V6_lvsplath_128B : 5964Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">; 5965 5966def int_hexagon_V6_ldtpnt0 : 5967Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtpnt0">; 5968 5969def int_hexagon_V6_ldtpnt0_128B : 5970Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtpnt0_128B">; 5971 5972def int_hexagon_V6_vlutvwh_nm : 5973Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">; 5974 5975def int_hexagon_V6_vlutvwh_nm_128B : 5976Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">; 5977 5978def int_hexagon_V6_ldnpnt0 : 5979Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldnpnt0">; 5980 5981def int_hexagon_V6_ldnpnt0_128B : 5982Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldnpnt0_128B">; 5983 5984def int_hexagon_V6_vmpauhb : 5985Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">; 5986 5987def int_hexagon_V6_vmpauhb_128B : 5988Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">; 5989 5990def int_hexagon_V6_ldtnp0 : 5991Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnp0">; 5992 5993def int_hexagon_V6_ldtnp0_128B : 5994Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnp0_128B">; 5995 5996def int_hexagon_V6_vrounduhub : 5997Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">; 5998 5999def int_hexagon_V6_vrounduhub_128B : 6000Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">; 6001 6002def int_hexagon_V6_vadduhw_acc : 6003Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">; 6004 6005def int_hexagon_V6_vadduhw_acc_128B : 6006Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">; 6007 6008def int_hexagon_V6_ldcp0 : 6009Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcp0">; 6010 6011def int_hexagon_V6_ldcp0_128B : 6012Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcp0_128B">; 6013 6014def int_hexagon_V6_vadduwsat : 6015Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">; 6016 6017def int_hexagon_V6_vadduwsat_128B : 6018Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">; 6019 6020def int_hexagon_V6_ldtnpnt0 : 6021Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnpnt0">; 6022 6023def int_hexagon_V6_ldtnpnt0_128B : 6024Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnpnt0_128B">; 6025 6026def int_hexagon_V6_vaddbsat : 6027Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">; 6028 6029def int_hexagon_V6_vaddbsat_128B : 6030Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_128B">; 6031 6032def int_hexagon_V6_vandnqrt : 6033Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt">; 6034 6035def int_hexagon_V6_vandnqrt_128B : 6036Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_128B">; 6037 6038def int_hexagon_V6_vmpyiwub_acc : 6039Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">; 6040 6041def int_hexagon_V6_vmpyiwub_acc_128B : 6042Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">; 6043 6044def int_hexagon_V6_vmaxb : 6045Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">; 6046 6047def int_hexagon_V6_vmaxb_128B : 6048Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxb_128B">; 6049 6050def int_hexagon_V6_vandvqv : 6051Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvqv">; 6052 6053def int_hexagon_V6_vandvqv_128B : 6054Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvqv_128B">; 6055 6056def int_hexagon_V6_vaddcarry : 6057Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic; 6058 6059def int_hexagon_V6_vaddcarry_128B : 6060Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B; 6061 6062def int_hexagon_V6_vasrwuhrndsat : 6063Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">; 6064 6065def int_hexagon_V6_vasrwuhrndsat_128B : 6066Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">; 6067 6068def int_hexagon_V6_vlutvvbi : 6069Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [ImmArg<2>]>; 6070 6071def int_hexagon_V6_vlutvvbi_128B : 6072Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [ImmArg<2>]>; 6073 6074def int_hexagon_V6_vsubuwsat : 6075Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">; 6076 6077def int_hexagon_V6_vsubuwsat_128B : 6078Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">; 6079 6080def int_hexagon_V6_vaddbsat_dv : 6081Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">; 6082 6083def int_hexagon_V6_vaddbsat_dv_128B : 6084Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">; 6085 6086def int_hexagon_V6_ldnp0 : 6087Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldnp0">; 6088 6089def int_hexagon_V6_ldnp0_128B : 6090Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldnp0_128B">; 6091 6092def int_hexagon_V6_vasruwuhrndsat : 6093Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">; 6094 6095def int_hexagon_V6_vasruwuhrndsat_128B : 6096Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">; 6097 6098def int_hexagon_V6_vrounduwuh : 6099Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">; 6100 6101def int_hexagon_V6_vrounduwuh_128B : 6102Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">; 6103 6104def int_hexagon_V6_vlutvvb_nm : 6105Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">; 6106 6107def int_hexagon_V6_vlutvvb_nm_128B : 6108Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">; 6109 6110def int_hexagon_V6_pred_scalar2v2 : 6111Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2">; 6112 6113def int_hexagon_V6_pred_scalar2v2_128B : 6114Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">; 6115 6116def int_hexagon_V6_ldp0 : 6117Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldp0">; 6118 6119def int_hexagon_V6_ldp0_128B : 6120Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldp0_128B">; 6121 6122def int_hexagon_V6_vaddubh_acc : 6123Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">; 6124 6125def int_hexagon_V6_vaddubh_acc_128B : 6126Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">; 6127 6128def int_hexagon_V6_vaddclbw : 6129Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">; 6130 6131def int_hexagon_V6_vaddclbw_128B : 6132Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">; 6133 6134def int_hexagon_V6_ldcpnt0 : 6135Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcpnt0">; 6136 6137def int_hexagon_V6_ldcpnt0_128B : 6138Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcpnt0_128B">; 6139 6140def int_hexagon_V6_vadduwsat_dv : 6141Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">; 6142 6143def int_hexagon_V6_vadduwsat_dv_128B : 6144Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">; 6145 6146def int_hexagon_V6_vmpyiwub : 6147Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">; 6148 6149def int_hexagon_V6_vmpyiwub_128B : 6150Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">; 6151 6152def int_hexagon_V6_vsubububb_sat : 6153Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">; 6154 6155def int_hexagon_V6_vsubububb_sat_128B : 6156Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">; 6157 6158def int_hexagon_V6_ldcnp0 : 6159Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0">; 6160 6161def int_hexagon_V6_ldcnp0_128B : 6162Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0_128B">; 6163 6164def int_hexagon_V6_vlutvwh_oracci : 6165Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [ImmArg<3>]>; 6166 6167def int_hexagon_V6_vlutvwh_oracci_128B : 6168Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [ImmArg<3>]>; 6169 6170def int_hexagon_V6_vsubbsat : 6171Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">; 6172 6173def int_hexagon_V6_vsubbsat_128B : 6174Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">; 6175 6176// V65 HVX Instructions. 6177 6178def int_hexagon_V6_vasruhubrndsat : 6179Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">; 6180 6181def int_hexagon_V6_vasruhubrndsat_128B : 6182Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">; 6183 6184def int_hexagon_V6_vrmpybub_rtt : 6185Hexagon_v32i32_v16i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">; 6186 6187def int_hexagon_V6_vrmpybub_rtt_128B : 6188Hexagon_v64i32_v32i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">; 6189 6190def int_hexagon_V6_vmpahhsat : 6191Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">; 6192 6193def int_hexagon_V6_vmpahhsat_128B : 6194Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">; 6195 6196def int_hexagon_V6_vavguwrnd : 6197Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">; 6198 6199def int_hexagon_V6_vavguwrnd_128B : 6200Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">; 6201 6202def int_hexagon_V6_vnavgb : 6203Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">; 6204 6205def int_hexagon_V6_vnavgb_128B : 6206Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">; 6207 6208def int_hexagon_V6_vasrh_acc : 6209Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">; 6210 6211def int_hexagon_V6_vasrh_acc_128B : 6212Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">; 6213 6214def int_hexagon_V6_vmpauhuhsat : 6215Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat">; 6216 6217def int_hexagon_V6_vmpauhuhsat_128B : 6218Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">; 6219 6220def int_hexagon_V6_vmpyh_acc : 6221Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">; 6222 6223def int_hexagon_V6_vmpyh_acc_128B : 6224Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">; 6225 6226def int_hexagon_V6_vrmpybub_rtt_acc : 6227Hexagon_v32i32_v32i32v16i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">; 6228 6229def int_hexagon_V6_vrmpybub_rtt_acc_128B : 6230Hexagon_v64i32_v64i32v32i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">; 6231 6232def int_hexagon_V6_vavgb : 6233Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">; 6234 6235def int_hexagon_V6_vavgb_128B : 6236Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">; 6237 6238def int_hexagon_V6_vaslh_acc : 6239Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">; 6240 6241def int_hexagon_V6_vaslh_acc_128B : 6242Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">; 6243 6244def int_hexagon_V6_vavguw : 6245Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">; 6246 6247def int_hexagon_V6_vavguw_128B : 6248Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">; 6249 6250def int_hexagon_V6_vlut4 : 6251Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">; 6252 6253def int_hexagon_V6_vlut4_128B : 6254Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">; 6255 6256def int_hexagon_V6_vmpyuhe_acc : 6257Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">; 6258 6259def int_hexagon_V6_vmpyuhe_acc_128B : 6260Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">; 6261 6262def int_hexagon_V6_vrmpyub_rtt : 6263Hexagon_v32i32_v16i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">; 6264 6265def int_hexagon_V6_vrmpyub_rtt_128B : 6266Hexagon_v64i32_v32i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">; 6267 6268def int_hexagon_V6_vmpsuhuhsat : 6269Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">; 6270 6271def int_hexagon_V6_vmpsuhuhsat_128B : 6272Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">; 6273 6274def int_hexagon_V6_vasruhubsat : 6275Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">; 6276 6277def int_hexagon_V6_vasruhubsat_128B : 6278Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">; 6279 6280def int_hexagon_V6_vmpyuhe : 6281Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">; 6282 6283def int_hexagon_V6_vmpyuhe_128B : 6284Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">; 6285 6286def int_hexagon_V6_vrmpyub_rtt_acc : 6287Hexagon_v32i32_v32i32v16i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">; 6288 6289def int_hexagon_V6_vrmpyub_rtt_acc_128B : 6290Hexagon_v64i32_v64i32v32i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">; 6291 6292def int_hexagon_V6_vasruwuhsat : 6293Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">; 6294 6295def int_hexagon_V6_vasruwuhsat_128B : 6296Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">; 6297 6298def int_hexagon_V6_vmpabuu_acc : 6299Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">; 6300 6301def int_hexagon_V6_vmpabuu_acc_128B : 6302Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">; 6303 6304def int_hexagon_V6_vprefixqw : 6305Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqw">; 6306 6307def int_hexagon_V6_vprefixqw_128B : 6308Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqw_128B">; 6309 6310def int_hexagon_V6_vprefixqh : 6311Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqh">; 6312 6313def int_hexagon_V6_vprefixqh_128B : 6314Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqh_128B">; 6315 6316def int_hexagon_V6_vprefixqb : 6317Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqb">; 6318 6319def int_hexagon_V6_vprefixqb_128B : 6320Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqb_128B">; 6321 6322def int_hexagon_V6_vabsb : 6323Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">; 6324 6325def int_hexagon_V6_vabsb_128B : 6326Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_128B">; 6327 6328def int_hexagon_V6_vavgbrnd : 6329Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">; 6330 6331def int_hexagon_V6_vavgbrnd_128B : 6332Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">; 6333 6334def int_hexagon_V6_vdd0 : 6335Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">; 6336 6337def int_hexagon_V6_vdd0_128B : 6338Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">; 6339 6340def int_hexagon_V6_vmpabuu : 6341Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">; 6342 6343def int_hexagon_V6_vmpabuu_128B : 6344Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_128B">; 6345 6346def int_hexagon_V6_vabsb_sat : 6347Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">; 6348 6349def int_hexagon_V6_vabsb_sat_128B : 6350Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">; 6351 6352// V66 HVX Instructions. 6353 6354def int_hexagon_V6_vaddcarrysat : 6355Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<"HEXAGON_V6_vaddcarrysat">; 6356 6357def int_hexagon_V6_vaddcarrysat_128B : 6358Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<"HEXAGON_V6_vaddcarrysat_128B">; 6359 6360def int_hexagon_V6_vasr_into : 6361Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">; 6362 6363def int_hexagon_V6_vasr_into_128B : 6364Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">; 6365 6366def int_hexagon_V6_vsatdw : 6367Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">; 6368 6369def int_hexagon_V6_vsatdw_128B : 6370Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">; 6371 6372def int_hexagon_V6_vrotr : 6373Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">; 6374 6375def int_hexagon_V6_vrotr_128B : 6376Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">; 6377 6378