1//===----------------------------------------------------------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// Automatically generated file, do not edit! 9//===----------------------------------------------------------------------===// 10 11// tag : A2_abs 12class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix, 13 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 14 : Hexagon_Intrinsic<GCCIntSuffix, 15 [llvm_i32_ty], [llvm_i32_ty], 16 intr_properties>; 17 18// tag : A2_absp 19class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix, 20 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 21 : Hexagon_Intrinsic<GCCIntSuffix, 22 [llvm_i64_ty], [llvm_i64_ty], 23 intr_properties>; 24 25// tag : A2_add 26class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix, 27 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 28 : Hexagon_Intrinsic<GCCIntSuffix, 29 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty], 30 intr_properties>; 31 32// tag : A2_addp 33class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix, 34 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 35 : Hexagon_Intrinsic<GCCIntSuffix, 36 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty], 37 intr_properties>; 38 39// tag : A2_addsp 40class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix, 41 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 42 : Hexagon_Intrinsic<GCCIntSuffix, 43 [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty], 44 intr_properties>; 45 46// tag : A2_combineii 47class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix, 48 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 49 : Hexagon_Intrinsic<GCCIntSuffix, 50 [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty], 51 intr_properties>; 52 53// tag : A2_roundsat 54class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix, 55 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 56 : Hexagon_Intrinsic<GCCIntSuffix, 57 [llvm_i32_ty], [llvm_i64_ty], 58 intr_properties>; 59 60// tag : A2_sxtw 61class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix, 62 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 63 : Hexagon_Intrinsic<GCCIntSuffix, 64 [llvm_i64_ty], [llvm_i32_ty], 65 intr_properties>; 66 67// tag : A2_vcmpbeq 68class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix, 69 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 70 : Hexagon_Intrinsic<GCCIntSuffix, 71 [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty], 72 intr_properties>; 73 74// tag : A2_vraddub_acc 75class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix, 76 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 77 : Hexagon_Intrinsic<GCCIntSuffix, 78 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty], 79 intr_properties>; 80 81// tag : A4_boundscheck 82class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix, 83 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 84 : Hexagon_Intrinsic<GCCIntSuffix, 85 [llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty], 86 intr_properties>; 87 88// tag : A4_tlbmatch 89class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix, 90 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 91 : Hexagon_Intrinsic<GCCIntSuffix, 92 [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty], 93 intr_properties>; 94 95// tag : A4_vrmaxh 96class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix, 97 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 98 : Hexagon_Intrinsic<GCCIntSuffix, 99 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty], 100 intr_properties>; 101 102// tag : A7_croundd_ri 103class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix, 104 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 105 : Hexagon_Intrinsic<GCCIntSuffix, 106 [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty], 107 intr_properties>; 108 109// tag : C2_mux 110class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix, 111 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 112 : Hexagon_Intrinsic<GCCIntSuffix, 113 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], 114 intr_properties>; 115 116// tag : C2_vmux 117class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix, 118 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 119 : Hexagon_Intrinsic<GCCIntSuffix, 120 [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty], 121 intr_properties>; 122 123// tag : F2_conv_d2df 124class Hexagon_double_i64_Intrinsic<string GCCIntSuffix, 125 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 126 : Hexagon_Intrinsic<GCCIntSuffix, 127 [llvm_double_ty], [llvm_i64_ty], 128 intr_properties>; 129 130// tag : F2_conv_d2sf 131class Hexagon_float_i64_Intrinsic<string GCCIntSuffix, 132 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 133 : Hexagon_Intrinsic<GCCIntSuffix, 134 [llvm_float_ty], [llvm_i64_ty], 135 intr_properties>; 136 137// tag : F2_conv_df2d 138class Hexagon_i64_double_Intrinsic<string GCCIntSuffix, 139 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 140 : Hexagon_Intrinsic<GCCIntSuffix, 141 [llvm_i64_ty], [llvm_double_ty], 142 intr_properties>; 143 144// tag : F2_conv_df2sf 145class Hexagon_float_double_Intrinsic<string GCCIntSuffix, 146 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 147 : Hexagon_Intrinsic<GCCIntSuffix, 148 [llvm_float_ty], [llvm_double_ty], 149 intr_properties>; 150 151// tag : F2_conv_df2uw 152class Hexagon_i32_double_Intrinsic<string GCCIntSuffix, 153 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 154 : Hexagon_Intrinsic<GCCIntSuffix, 155 [llvm_i32_ty], [llvm_double_ty], 156 intr_properties>; 157 158// tag : F2_conv_sf2d 159class Hexagon_i64_float_Intrinsic<string GCCIntSuffix, 160 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 161 : Hexagon_Intrinsic<GCCIntSuffix, 162 [llvm_i64_ty], [llvm_float_ty], 163 intr_properties>; 164 165// tag : F2_conv_sf2df 166class Hexagon_double_float_Intrinsic<string GCCIntSuffix, 167 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 168 : Hexagon_Intrinsic<GCCIntSuffix, 169 [llvm_double_ty], [llvm_float_ty], 170 intr_properties>; 171 172// tag : F2_conv_sf2uw 173class Hexagon_i32_float_Intrinsic<string GCCIntSuffix, 174 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 175 : Hexagon_Intrinsic<GCCIntSuffix, 176 [llvm_i32_ty], [llvm_float_ty], 177 intr_properties>; 178 179// tag : F2_conv_uw2df 180class Hexagon_double_i32_Intrinsic<string GCCIntSuffix, 181 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 182 : Hexagon_Intrinsic<GCCIntSuffix, 183 [llvm_double_ty], [llvm_i32_ty], 184 intr_properties>; 185 186// tag : F2_conv_uw2sf 187class Hexagon_float_i32_Intrinsic<string GCCIntSuffix, 188 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 189 : Hexagon_Intrinsic<GCCIntSuffix, 190 [llvm_float_ty], [llvm_i32_ty], 191 intr_properties>; 192 193// tag : F2_dfadd 194class Hexagon_double_doubledouble_Intrinsic<string GCCIntSuffix, 195 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 196 : Hexagon_Intrinsic<GCCIntSuffix, 197 [llvm_double_ty], [llvm_double_ty,llvm_double_ty], 198 intr_properties>; 199 200// tag : F2_dfclass 201class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix, 202 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 203 : Hexagon_Intrinsic<GCCIntSuffix, 204 [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty], 205 intr_properties>; 206 207// tag : F2_dfcmpeq 208class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix, 209 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 210 : Hexagon_Intrinsic<GCCIntSuffix, 211 [llvm_i32_ty], [llvm_double_ty,llvm_double_ty], 212 intr_properties>; 213 214// tag : F2_dfmpyhh 215class Hexagon_double_doubledoubledouble_Intrinsic<string GCCIntSuffix, 216 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 217 : Hexagon_Intrinsic<GCCIntSuffix, 218 [llvm_double_ty], [llvm_double_ty,llvm_double_ty,llvm_double_ty], 219 intr_properties>; 220 221// tag : F2_sfadd 222class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix, 223 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 224 : Hexagon_Intrinsic<GCCIntSuffix, 225 [llvm_float_ty], [llvm_float_ty,llvm_float_ty], 226 intr_properties>; 227 228// tag : F2_sfclass 229class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix, 230 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 231 : Hexagon_Intrinsic<GCCIntSuffix, 232 [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty], 233 intr_properties>; 234 235// tag : F2_sfcmpeq 236class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix, 237 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 238 : Hexagon_Intrinsic<GCCIntSuffix, 239 [llvm_i32_ty], [llvm_float_ty,llvm_float_ty], 240 intr_properties>; 241 242// tag : F2_sffixupr 243class Hexagon_float_float_Intrinsic<string GCCIntSuffix, 244 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 245 : Hexagon_Intrinsic<GCCIntSuffix, 246 [llvm_float_ty], [llvm_float_ty], 247 intr_properties>; 248 249// tag : F2_sffma 250class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix, 251 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 252 : Hexagon_Intrinsic<GCCIntSuffix, 253 [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty], 254 intr_properties>; 255 256// tag : F2_sffma_sc 257class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix, 258 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 259 : Hexagon_Intrinsic<GCCIntSuffix, 260 [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty], 261 intr_properties>; 262 263// tag : M2_cmaci_s0 264class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix, 265 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 266 : Hexagon_Intrinsic<GCCIntSuffix, 267 [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], 268 intr_properties>; 269 270// tag : S2_insert 271class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix, 272 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 273 : Hexagon_Intrinsic<GCCIntSuffix, 274 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], 275 intr_properties>; 276 277// tag : S2_insert_rp 278class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix, 279 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 280 : Hexagon_Intrinsic<GCCIntSuffix, 281 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty], 282 intr_properties>; 283 284// tag : S2_insertp 285class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix, 286 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 287 : Hexagon_Intrinsic<GCCIntSuffix, 288 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], 289 intr_properties>; 290 291// tag : V6_extractw 292class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix, 293 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 294 : Hexagon_Intrinsic<GCCIntSuffix, 295 [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 296 intr_properties>; 297 298// tag : V6_extractw 299class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix, 300 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 301 : Hexagon_Intrinsic<GCCIntSuffix, 302 [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 303 intr_properties>; 304 305// tag : V6_hi 306class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix, 307 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 308 : Hexagon_Intrinsic<GCCIntSuffix, 309 [llvm_v16i32_ty], [llvm_v32i32_ty], 310 intr_properties>; 311 312// tag : V6_hi 313class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix, 314 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 315 : Hexagon_Intrinsic<GCCIntSuffix, 316 [llvm_v32i32_ty], [llvm_v64i32_ty], 317 intr_properties>; 318 319// tag : V6_lvsplatw 320class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix, 321 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 322 : Hexagon_Intrinsic<GCCIntSuffix, 323 [llvm_v16i32_ty], [llvm_i32_ty], 324 intr_properties>; 325 326// tag : V6_lvsplatb 327class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix, 328 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 329 : Hexagon_Intrinsic<GCCIntSuffix, 330 [llvm_v32i32_ty], [llvm_i32_ty], 331 intr_properties>; 332 333// tag : V6_pred_and 334class Hexagon_v64i1_v64i1v64i1_Intrinsic<string GCCIntSuffix, 335 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 336 : Hexagon_Intrinsic<GCCIntSuffix, 337 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v64i1_ty], 338 intr_properties>; 339 340// tag : V6_pred_and 341class Hexagon_v128i1_v128i1v128i1_Intrinsic<string GCCIntSuffix, 342 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 343 : Hexagon_Intrinsic<GCCIntSuffix, 344 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v128i1_ty], 345 intr_properties>; 346 347// tag : V6_pred_not 348class Hexagon_v64i1_v64i1_Intrinsic<string GCCIntSuffix, 349 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 350 : Hexagon_Intrinsic<GCCIntSuffix, 351 [llvm_v64i1_ty], [llvm_v64i1_ty], 352 intr_properties>; 353 354// tag : V6_pred_not 355class Hexagon_v128i1_v128i1_Intrinsic<string GCCIntSuffix, 356 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 357 : Hexagon_Intrinsic<GCCIntSuffix, 358 [llvm_v128i1_ty], [llvm_v128i1_ty], 359 intr_properties>; 360 361// tag : V6_pred_scalar2 362class Hexagon_v64i1_i32_Intrinsic<string GCCIntSuffix, 363 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 364 : Hexagon_Intrinsic<GCCIntSuffix, 365 [llvm_v64i1_ty], [llvm_i32_ty], 366 intr_properties>; 367 368// tag : V6_pred_scalar2 369class Hexagon_v128i1_i32_Intrinsic<string GCCIntSuffix, 370 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 371 : Hexagon_Intrinsic<GCCIntSuffix, 372 [llvm_v128i1_ty], [llvm_i32_ty], 373 intr_properties>; 374 375// tag : V6_v6mpyhubs10 376class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 377 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 378 : Hexagon_Intrinsic<GCCIntSuffix, 379 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 380 intr_properties>; 381 382// tag : V6_v6mpyhubs10 383class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix, 384 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 385 : Hexagon_Intrinsic<GCCIntSuffix, 386 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], 387 intr_properties>; 388 389// tag : V6_v6mpyhubs10_vxx 390class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 391 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 392 : Hexagon_Intrinsic<GCCIntSuffix, 393 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 394 intr_properties>; 395 396// tag : V6_v6mpyhubs10_vxx 397class Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<string GCCIntSuffix, 398 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 399 : Hexagon_Intrinsic<GCCIntSuffix, 400 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], 401 intr_properties>; 402 403// tag : V6_vS32b_nqpred_ai 404class Hexagon__v64i1ptrv16i32_Intrinsic<string GCCIntSuffix, 405 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 406 : Hexagon_Intrinsic<GCCIntSuffix, 407 [], [llvm_v64i1_ty,llvm_ptr_ty,llvm_v16i32_ty], 408 intr_properties>; 409 410// tag : V6_vS32b_nqpred_ai 411class Hexagon__v128i1ptrv32i32_Intrinsic<string GCCIntSuffix, 412 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 413 : Hexagon_Intrinsic<GCCIntSuffix, 414 [], [llvm_v128i1_ty,llvm_ptr_ty,llvm_v32i32_ty], 415 intr_properties>; 416 417// tag : V6_vabs_hf 418class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix, 419 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 420 : Hexagon_Intrinsic<GCCIntSuffix, 421 [llvm_v16i32_ty], [llvm_v16i32_ty], 422 intr_properties>; 423 424// tag : V6_vabs_hf 425class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix, 426 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 427 : Hexagon_Intrinsic<GCCIntSuffix, 428 [llvm_v32i32_ty], [llvm_v32i32_ty], 429 intr_properties>; 430 431// tag : V6_vabsdiffh 432class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix, 433 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 434 : Hexagon_Intrinsic<GCCIntSuffix, 435 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 436 intr_properties>; 437 438// tag : V6_vabsdiffh 439class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix, 440 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 441 : Hexagon_Intrinsic<GCCIntSuffix, 442 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 443 intr_properties>; 444 445// tag : V6_vadd_sf_hf 446class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix, 447 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 448 : Hexagon_Intrinsic<GCCIntSuffix, 449 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 450 intr_properties>; 451 452// tag : V6_vadd_sf_hf 453class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix, 454 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 455 : Hexagon_Intrinsic<GCCIntSuffix, 456 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 457 intr_properties>; 458 459// tag : V6_vaddb_dv 460class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix, 461 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 462 : Hexagon_Intrinsic<GCCIntSuffix, 463 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty], 464 intr_properties>; 465 466// tag : V6_vaddbnq 467class Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<string GCCIntSuffix, 468 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 469 : Hexagon_Intrinsic<GCCIntSuffix, 470 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 471 intr_properties>; 472 473// tag : V6_vaddbnq 474class Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<string GCCIntSuffix, 475 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 476 : Hexagon_Intrinsic<GCCIntSuffix, 477 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 478 intr_properties>; 479 480// tag : V6_vaddcarry 481class Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic< 482 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 483 : Hexagon_NonGCC_Intrinsic< 484 [llvm_v16i32_ty,llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty], 485 intr_properties>; 486 487// tag : V6_vaddcarry 488class Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B< 489 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 490 : Hexagon_NonGCC_Intrinsic< 491 [llvm_v32i32_ty,llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty], 492 intr_properties>; 493 494// tag : V6_vaddcarrysat 495class Hexagon_v16i32_v16i32v16i32v64i1_Intrinsic<string GCCIntSuffix, 496 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 497 : Hexagon_Intrinsic<GCCIntSuffix, 498 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty], 499 intr_properties>; 500 501// tag : V6_vaddcarrysat 502class Hexagon_v32i32_v32i32v32i32v128i1_Intrinsic<string GCCIntSuffix, 503 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 504 : Hexagon_Intrinsic<GCCIntSuffix, 505 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty], 506 intr_properties>; 507 508// tag : V6_vaddhw_acc 509class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 510 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 511 : Hexagon_Intrinsic<GCCIntSuffix, 512 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 513 intr_properties>; 514 515// tag : V6_vaddhw_acc 516class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 517 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 518 : Hexagon_Intrinsic<GCCIntSuffix, 519 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 520 intr_properties>; 521 522// tag : V6_valignb 523class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 524 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 525 : Hexagon_Intrinsic<GCCIntSuffix, 526 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 527 intr_properties>; 528 529// tag : V6_vandnqrt 530class Hexagon_v16i32_v64i1i32_Intrinsic<string GCCIntSuffix, 531 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 532 : Hexagon_Intrinsic<GCCIntSuffix, 533 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_i32_ty], 534 intr_properties>; 535 536// tag : V6_vandnqrt 537class Hexagon_v32i32_v128i1i32_Intrinsic<string GCCIntSuffix, 538 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 539 : Hexagon_Intrinsic<GCCIntSuffix, 540 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_i32_ty], 541 intr_properties>; 542 543// tag : V6_vandnqrt_acc 544class Hexagon_v16i32_v16i32v64i1i32_Intrinsic<string GCCIntSuffix, 545 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 546 : Hexagon_Intrinsic<GCCIntSuffix, 547 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v64i1_ty,llvm_i32_ty], 548 intr_properties>; 549 550// tag : V6_vandnqrt_acc 551class Hexagon_v32i32_v32i32v128i1i32_Intrinsic<string GCCIntSuffix, 552 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 553 : Hexagon_Intrinsic<GCCIntSuffix, 554 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v128i1_ty,llvm_i32_ty], 555 intr_properties>; 556 557// tag : V6_vandvnqv 558class Hexagon_v16i32_v64i1v16i32_Intrinsic<string GCCIntSuffix, 559 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 560 : Hexagon_Intrinsic<GCCIntSuffix, 561 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty], 562 intr_properties>; 563 564// tag : V6_vandvnqv 565class Hexagon_v32i32_v128i1v32i32_Intrinsic<string GCCIntSuffix, 566 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 567 : Hexagon_Intrinsic<GCCIntSuffix, 568 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty], 569 intr_properties>; 570 571// tag : V6_vandvrt 572class Hexagon_v64i1_v16i32i32_Intrinsic<string GCCIntSuffix, 573 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 574 : Hexagon_Intrinsic<GCCIntSuffix, 575 [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_i32_ty], 576 intr_properties>; 577 578// tag : V6_vandvrt 579class Hexagon_v128i1_v32i32i32_Intrinsic<string GCCIntSuffix, 580 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 581 : Hexagon_Intrinsic<GCCIntSuffix, 582 [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_i32_ty], 583 intr_properties>; 584 585// tag : V6_vandvrt_acc 586class Hexagon_v64i1_v64i1v16i32i32_Intrinsic<string GCCIntSuffix, 587 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 588 : Hexagon_Intrinsic<GCCIntSuffix, 589 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_i32_ty], 590 intr_properties>; 591 592// tag : V6_vandvrt_acc 593class Hexagon_v128i1_v128i1v32i32i32_Intrinsic<string GCCIntSuffix, 594 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 595 : Hexagon_Intrinsic<GCCIntSuffix, 596 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_i32_ty], 597 intr_properties>; 598 599// tag : V6_vaslh 600class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix, 601 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 602 : Hexagon_Intrinsic<GCCIntSuffix, 603 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 604 intr_properties>; 605 606// tag : V6_vaslh 607class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix, 608 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 609 : Hexagon_Intrinsic<GCCIntSuffix, 610 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 611 intr_properties>; 612 613// tag : V6_vasrvuhubrndsat 614class Hexagon_v16i32_v32i32v16i32_Intrinsic<string GCCIntSuffix, 615 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 616 : Hexagon_Intrinsic<GCCIntSuffix, 617 [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty], 618 intr_properties>; 619 620// tag : V6_vasrvuhubrndsat 621class Hexagon_v32i32_v64i32v32i32_Intrinsic<string GCCIntSuffix, 622 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 623 : Hexagon_Intrinsic<GCCIntSuffix, 624 [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty], 625 intr_properties>; 626 627// tag : V6_vassignp 628class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix, 629 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 630 : Hexagon_Intrinsic<GCCIntSuffix, 631 [llvm_v64i32_ty], [llvm_v64i32_ty], 632 intr_properties>; 633 634// tag : V6_vcvt_hf_b 635class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix, 636 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 637 : Hexagon_Intrinsic<GCCIntSuffix, 638 [llvm_v32i32_ty], [llvm_v16i32_ty], 639 intr_properties>; 640 641// tag : V6_vcvt_hf_b 642class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix, 643 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 644 : Hexagon_Intrinsic<GCCIntSuffix, 645 [llvm_v64i32_ty], [llvm_v32i32_ty], 646 intr_properties>; 647 648// tag : V6_vd0 649class Hexagon_v16i32__Intrinsic<string GCCIntSuffix, 650 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 651 : Hexagon_Intrinsic<GCCIntSuffix, 652 [llvm_v16i32_ty], [], 653 intr_properties>; 654 655// tag : V6_vd0 656class Hexagon_v32i32__Intrinsic<string GCCIntSuffix, 657 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 658 : Hexagon_Intrinsic<GCCIntSuffix, 659 [llvm_v32i32_ty], [], 660 intr_properties>; 661 662// tag : V6_vdd0 663class Hexagon_v64i32__Intrinsic<string GCCIntSuffix, 664 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 665 : Hexagon_Intrinsic<GCCIntSuffix, 666 [llvm_v64i32_ty], [], 667 intr_properties>; 668 669// tag : V6_vdealvdd 670class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 671 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 672 : Hexagon_Intrinsic<GCCIntSuffix, 673 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 674 intr_properties>; 675 676// tag : V6_vdealvdd 677class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 678 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 679 : Hexagon_Intrinsic<GCCIntSuffix, 680 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 681 intr_properties>; 682 683// tag : V6_vdmpy_sf_hf_acc 684class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 685 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 686 : Hexagon_Intrinsic<GCCIntSuffix, 687 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 688 intr_properties>; 689 690// tag : V6_vdmpy_sf_hf_acc 691class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 692 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 693 : Hexagon_Intrinsic<GCCIntSuffix, 694 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 695 intr_properties>; 696 697// tag : V6_vdmpybus_dv 698class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix, 699 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 700 : Hexagon_Intrinsic<GCCIntSuffix, 701 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty], 702 intr_properties>; 703 704// tag : V6_vdmpyhisat 705class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix, 706 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 707 : Hexagon_Intrinsic<GCCIntSuffix, 708 [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 709 intr_properties>; 710 711// tag : V6_vdmpyhisat 712class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix, 713 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 714 : Hexagon_Intrinsic<GCCIntSuffix, 715 [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty], 716 intr_properties>; 717 718// tag : V6_vdmpyhisat_acc 719class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix, 720 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 721 : Hexagon_Intrinsic<GCCIntSuffix, 722 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty], 723 intr_properties>; 724 725// tag : V6_vdmpyhisat_acc 726class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix, 727 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 728 : Hexagon_Intrinsic<GCCIntSuffix, 729 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty], 730 intr_properties>; 731 732// tag : V6_veqb 733class Hexagon_v64i1_v16i32v16i32_Intrinsic<string GCCIntSuffix, 734 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 735 : Hexagon_Intrinsic<GCCIntSuffix, 736 [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 737 intr_properties>; 738 739// tag : V6_veqb 740class Hexagon_v128i1_v32i32v32i32_Intrinsic<string GCCIntSuffix, 741 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 742 : Hexagon_Intrinsic<GCCIntSuffix, 743 [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 744 intr_properties>; 745 746// tag : V6_veqb_and 747class Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<string GCCIntSuffix, 748 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 749 : Hexagon_Intrinsic<GCCIntSuffix, 750 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 751 intr_properties>; 752 753// tag : V6_veqb_and 754class Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<string GCCIntSuffix, 755 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 756 : Hexagon_Intrinsic<GCCIntSuffix, 757 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 758 intr_properties>; 759 760// tag : V6_vgathermh 761class Hexagon__ptri32i32v16i32_Intrinsic<string GCCIntSuffix, 762 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 763 : Hexagon_Intrinsic<GCCIntSuffix, 764 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty], 765 intr_properties>; 766 767// tag : V6_vgathermh 768class Hexagon__ptri32i32v32i32_Intrinsic<string GCCIntSuffix, 769 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 770 : Hexagon_Intrinsic<GCCIntSuffix, 771 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 772 intr_properties>; 773 774// tag : V6_vgathermhq 775class Hexagon__ptrv64i1i32i32v16i32_Intrinsic<string GCCIntSuffix, 776 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 777 : Hexagon_Intrinsic<GCCIntSuffix, 778 [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty], 779 intr_properties>; 780 781// tag : V6_vgathermhq 782class Hexagon__ptrv128i1i32i32v32i32_Intrinsic<string GCCIntSuffix, 783 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 784 : Hexagon_Intrinsic<GCCIntSuffix, 785 [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 786 intr_properties>; 787 788// tag : V6_vgathermhw 789class Hexagon__ptri32i32v64i32_Intrinsic<string GCCIntSuffix, 790 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 791 : Hexagon_Intrinsic<GCCIntSuffix, 792 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty], 793 intr_properties>; 794 795// tag : V6_vgathermhwq 796class Hexagon__ptrv64i1i32i32v32i32_Intrinsic<string GCCIntSuffix, 797 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 798 : Hexagon_Intrinsic<GCCIntSuffix, 799 [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 800 intr_properties>; 801 802// tag : V6_vgathermhwq 803class Hexagon__ptrv128i1i32i32v64i32_Intrinsic<string GCCIntSuffix, 804 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 805 : Hexagon_Intrinsic<GCCIntSuffix, 806 [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty], 807 intr_properties>; 808 809// tag : V6_vlut4 810class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix, 811 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 812 : Hexagon_Intrinsic<GCCIntSuffix, 813 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty], 814 intr_properties>; 815 816// tag : V6_vlut4 817class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix, 818 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 819 : Hexagon_Intrinsic<GCCIntSuffix, 820 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty], 821 intr_properties>; 822 823// tag : V6_vlutvvb_oracc 824class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 825 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 826 : Hexagon_Intrinsic<GCCIntSuffix, 827 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 828 intr_properties>; 829 830// tag : V6_vlutvwh_oracc 831class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 832 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 833 : Hexagon_Intrinsic<GCCIntSuffix, 834 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 835 intr_properties>; 836 837// tag : V6_vlutvwh_oracc 838class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 839 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 840 : Hexagon_Intrinsic<GCCIntSuffix, 841 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 842 intr_properties>; 843 844// tag : V6_vmpahhsat 845class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix, 846 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 847 : Hexagon_Intrinsic<GCCIntSuffix, 848 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty], 849 intr_properties>; 850 851// tag : V6_vmpahhsat 852class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix, 853 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 854 : Hexagon_Intrinsic<GCCIntSuffix, 855 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty], 856 intr_properties>; 857 858// tag : V6_vmpybus 859class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix, 860 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 861 : Hexagon_Intrinsic<GCCIntSuffix, 862 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 863 intr_properties>; 864 865// tag : V6_vmpybus 866class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix, 867 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 868 : Hexagon_Intrinsic<GCCIntSuffix, 869 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 870 intr_properties>; 871 872// tag : V6_vmpybus_acc 873class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix, 874 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 875 : Hexagon_Intrinsic<GCCIntSuffix, 876 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty], 877 intr_properties>; 878 879// tag : V6_vmpybus_acc 880class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix, 881 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 882 : Hexagon_Intrinsic<GCCIntSuffix, 883 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty], 884 intr_properties>; 885 886// tag : V6_vprefixqb 887class Hexagon_v16i32_v64i1_Intrinsic<string GCCIntSuffix, 888 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 889 : Hexagon_Intrinsic<GCCIntSuffix, 890 [llvm_v16i32_ty], [llvm_v64i1_ty], 891 intr_properties>; 892 893// tag : V6_vprefixqb 894class Hexagon_v32i32_v128i1_Intrinsic<string GCCIntSuffix, 895 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 896 : Hexagon_Intrinsic<GCCIntSuffix, 897 [llvm_v32i32_ty], [llvm_v128i1_ty], 898 intr_properties>; 899 900// tag : V6_vrmpybusi 901class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix, 902 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 903 : Hexagon_Intrinsic<GCCIntSuffix, 904 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], 905 intr_properties>; 906 907// tag : V6_vrmpybusi 908class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix, 909 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 910 : Hexagon_Intrinsic<GCCIntSuffix, 911 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], 912 intr_properties>; 913 914// tag : V6_vrmpybusi_acc 915class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix, 916 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 917 : Hexagon_Intrinsic<GCCIntSuffix, 918 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], 919 intr_properties>; 920 921// tag : V6_vrmpybusi_acc 922class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix, 923 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 924 : Hexagon_Intrinsic<GCCIntSuffix, 925 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], 926 intr_properties>; 927 928// tag : V6_vscattermh 929class Hexagon__i32i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 930 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 931 : Hexagon_Intrinsic<GCCIntSuffix, 932 [], [llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 933 intr_properties>; 934 935// tag : V6_vscattermh 936class Hexagon__i32i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 937 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 938 : Hexagon_Intrinsic<GCCIntSuffix, 939 [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 940 intr_properties>; 941 942// tag : V6_vscattermhq 943class Hexagon__v64i1i32i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 944 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 945 : Hexagon_Intrinsic<GCCIntSuffix, 946 [], [llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 947 intr_properties>; 948 949// tag : V6_vscattermhq 950class Hexagon__v128i1i32i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 951 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 952 : Hexagon_Intrinsic<GCCIntSuffix, 953 [], [llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 954 intr_properties>; 955 956// tag : V6_vscattermhw 957class Hexagon__i32i32v32i32v16i32_Intrinsic<string GCCIntSuffix, 958 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 959 : Hexagon_Intrinsic<GCCIntSuffix, 960 [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty], 961 intr_properties>; 962 963// tag : V6_vscattermhw 964class Hexagon__i32i32v64i32v32i32_Intrinsic<string GCCIntSuffix, 965 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 966 : Hexagon_Intrinsic<GCCIntSuffix, 967 [], [llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty], 968 intr_properties>; 969 970// tag : V6_vscattermhwq 971class Hexagon__v64i1i32i32v32i32v16i32_Intrinsic<string GCCIntSuffix, 972 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 973 : Hexagon_Intrinsic<GCCIntSuffix, 974 [], [llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty], 975 intr_properties>; 976 977// tag : V6_vscattermhwq 978class Hexagon__v128i1i32i32v64i32v32i32_Intrinsic<string GCCIntSuffix, 979 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 980 : Hexagon_Intrinsic<GCCIntSuffix, 981 [], [llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty], 982 intr_properties>; 983 984// tag : V6_vswap 985class Hexagon_v32i32_v64i1v16i32v16i32_Intrinsic<string GCCIntSuffix, 986 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 987 : Hexagon_Intrinsic<GCCIntSuffix, 988 [llvm_v32i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 989 intr_properties>; 990 991// tag : V6_vswap 992class Hexagon_v64i32_v128i1v32i32v32i32_Intrinsic<string GCCIntSuffix, 993 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 994 : Hexagon_Intrinsic<GCCIntSuffix, 995 [llvm_v64i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 996 intr_properties>; 997 998// tag : V6_vunpackob 999class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix, 1000 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1001 : Hexagon_Intrinsic<GCCIntSuffix, 1002 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty], 1003 intr_properties>; 1004 1005// tag : V6_vunpackob 1006class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix, 1007 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1008 : Hexagon_Intrinsic<GCCIntSuffix, 1009 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty], 1010 intr_properties>; 1011 1012// tag : Y2_dccleana 1013class Hexagon__ptr_Intrinsic<string GCCIntSuffix, 1014 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1015 : Hexagon_Intrinsic<GCCIntSuffix, 1016 [], [llvm_ptr_ty], 1017 intr_properties>; 1018 1019// tag : Y4_l2fetch 1020class Hexagon__ptri32_Intrinsic<string GCCIntSuffix, 1021 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1022 : Hexagon_Intrinsic<GCCIntSuffix, 1023 [], [llvm_ptr_ty,llvm_i32_ty], 1024 intr_properties>; 1025 1026// tag : Y5_l2fetch 1027class Hexagon__ptri64_Intrinsic<string GCCIntSuffix, 1028 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1029 : Hexagon_Intrinsic<GCCIntSuffix, 1030 [], [llvm_ptr_ty,llvm_i64_ty], 1031 intr_properties>; 1032 1033// tag : Y6_dmlink 1034class Hexagon__ptrptr_Intrinsic<string GCCIntSuffix, 1035 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1036 : Hexagon_Intrinsic<GCCIntSuffix, 1037 [], [llvm_ptr_ty,llvm_ptr_ty], 1038 intr_properties>; 1039 1040// tag : Y6_dmpause 1041class Hexagon_i32__Intrinsic<string GCCIntSuffix, 1042 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1043 : Hexagon_Intrinsic<GCCIntSuffix, 1044 [llvm_i32_ty], [], 1045 intr_properties>; 1046 1047// V5 Scalar Instructions. 1048 1049def int_hexagon_A2_abs : 1050Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">; 1051 1052def int_hexagon_A2_absp : 1053Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">; 1054 1055def int_hexagon_A2_abssat : 1056Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">; 1057 1058def int_hexagon_A2_add : 1059Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">; 1060 1061def int_hexagon_A2_addh_h16_hh : 1062Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">; 1063 1064def int_hexagon_A2_addh_h16_hl : 1065Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">; 1066 1067def int_hexagon_A2_addh_h16_lh : 1068Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">; 1069 1070def int_hexagon_A2_addh_h16_ll : 1071Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">; 1072 1073def int_hexagon_A2_addh_h16_sat_hh : 1074Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">; 1075 1076def int_hexagon_A2_addh_h16_sat_hl : 1077Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">; 1078 1079def int_hexagon_A2_addh_h16_sat_lh : 1080Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">; 1081 1082def int_hexagon_A2_addh_h16_sat_ll : 1083Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">; 1084 1085def int_hexagon_A2_addh_l16_hl : 1086Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">; 1087 1088def int_hexagon_A2_addh_l16_ll : 1089Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">; 1090 1091def int_hexagon_A2_addh_l16_sat_hl : 1092Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">; 1093 1094def int_hexagon_A2_addh_l16_sat_ll : 1095Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">; 1096 1097def int_hexagon_A2_addi : 1098Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1099 1100def int_hexagon_A2_addp : 1101Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">; 1102 1103def int_hexagon_A2_addpsat : 1104Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">; 1105 1106def int_hexagon_A2_addsat : 1107Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">; 1108 1109def int_hexagon_A2_addsp : 1110Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">; 1111 1112def int_hexagon_A2_and : 1113Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">; 1114 1115def int_hexagon_A2_andir : 1116Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1117 1118def int_hexagon_A2_andp : 1119Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">; 1120 1121def int_hexagon_A2_aslh : 1122Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">; 1123 1124def int_hexagon_A2_asrh : 1125Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">; 1126 1127def int_hexagon_A2_combine_hh : 1128Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">; 1129 1130def int_hexagon_A2_combine_hl : 1131Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">; 1132 1133def int_hexagon_A2_combine_lh : 1134Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">; 1135 1136def int_hexagon_A2_combine_ll : 1137Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">; 1138 1139def int_hexagon_A2_combineii : 1140Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>; 1141 1142def int_hexagon_A2_combinew : 1143Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">; 1144 1145def int_hexagon_A2_max : 1146Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">; 1147 1148def int_hexagon_A2_maxp : 1149Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">; 1150 1151def int_hexagon_A2_maxu : 1152Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">; 1153 1154def int_hexagon_A2_maxup : 1155Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">; 1156 1157def int_hexagon_A2_min : 1158Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">; 1159 1160def int_hexagon_A2_minp : 1161Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">; 1162 1163def int_hexagon_A2_minu : 1164Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">; 1165 1166def int_hexagon_A2_minup : 1167Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">; 1168 1169def int_hexagon_A2_neg : 1170Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">; 1171 1172def int_hexagon_A2_negp : 1173Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">; 1174 1175def int_hexagon_A2_negsat : 1176Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">; 1177 1178def int_hexagon_A2_not : 1179Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">; 1180 1181def int_hexagon_A2_notp : 1182Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">; 1183 1184def int_hexagon_A2_or : 1185Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">; 1186 1187def int_hexagon_A2_orir : 1188Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1189 1190def int_hexagon_A2_orp : 1191Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">; 1192 1193def int_hexagon_A2_roundsat : 1194Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">; 1195 1196def int_hexagon_A2_sat : 1197Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">; 1198 1199def int_hexagon_A2_satb : 1200Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">; 1201 1202def int_hexagon_A2_sath : 1203Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">; 1204 1205def int_hexagon_A2_satub : 1206Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">; 1207 1208def int_hexagon_A2_satuh : 1209Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">; 1210 1211def int_hexagon_A2_sub : 1212Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">; 1213 1214def int_hexagon_A2_subh_h16_hh : 1215Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">; 1216 1217def int_hexagon_A2_subh_h16_hl : 1218Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">; 1219 1220def int_hexagon_A2_subh_h16_lh : 1221Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">; 1222 1223def int_hexagon_A2_subh_h16_ll : 1224Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">; 1225 1226def int_hexagon_A2_subh_h16_sat_hh : 1227Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">; 1228 1229def int_hexagon_A2_subh_h16_sat_hl : 1230Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">; 1231 1232def int_hexagon_A2_subh_h16_sat_lh : 1233Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">; 1234 1235def int_hexagon_A2_subh_h16_sat_ll : 1236Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">; 1237 1238def int_hexagon_A2_subh_l16_hl : 1239Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">; 1240 1241def int_hexagon_A2_subh_l16_ll : 1242Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">; 1243 1244def int_hexagon_A2_subh_l16_sat_hl : 1245Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">; 1246 1247def int_hexagon_A2_subh_l16_sat_ll : 1248Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">; 1249 1250def int_hexagon_A2_subp : 1251Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">; 1252 1253def int_hexagon_A2_subri : 1254Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1255 1256def int_hexagon_A2_subsat : 1257Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">; 1258 1259def int_hexagon_A2_svaddh : 1260Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">; 1261 1262def int_hexagon_A2_svaddhs : 1263Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">; 1264 1265def int_hexagon_A2_svadduhs : 1266Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">; 1267 1268def int_hexagon_A2_svavgh : 1269Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">; 1270 1271def int_hexagon_A2_svavghs : 1272Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">; 1273 1274def int_hexagon_A2_svnavgh : 1275Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">; 1276 1277def int_hexagon_A2_svsubh : 1278Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">; 1279 1280def int_hexagon_A2_svsubhs : 1281Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">; 1282 1283def int_hexagon_A2_svsubuhs : 1284Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">; 1285 1286def int_hexagon_A2_swiz : 1287Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">; 1288 1289def int_hexagon_A2_sxtb : 1290Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">; 1291 1292def int_hexagon_A2_sxth : 1293Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">; 1294 1295def int_hexagon_A2_sxtw : 1296Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">; 1297 1298def int_hexagon_A2_tfr : 1299Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">; 1300 1301def int_hexagon_A2_tfrih : 1302Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1303 1304def int_hexagon_A2_tfril : 1305Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1306 1307def int_hexagon_A2_tfrp : 1308Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">; 1309 1310def int_hexagon_A2_tfrpi : 1311Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1312 1313def int_hexagon_A2_tfrsi : 1314Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1315 1316def int_hexagon_A2_vabsh : 1317Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">; 1318 1319def int_hexagon_A2_vabshsat : 1320Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">; 1321 1322def int_hexagon_A2_vabsw : 1323Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">; 1324 1325def int_hexagon_A2_vabswsat : 1326Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">; 1327 1328def int_hexagon_A2_vaddb_map : 1329Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">; 1330 1331def int_hexagon_A2_vaddh : 1332Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">; 1333 1334def int_hexagon_A2_vaddhs : 1335Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">; 1336 1337def int_hexagon_A2_vaddub : 1338Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">; 1339 1340def int_hexagon_A2_vaddubs : 1341Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">; 1342 1343def int_hexagon_A2_vadduhs : 1344Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">; 1345 1346def int_hexagon_A2_vaddw : 1347Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">; 1348 1349def int_hexagon_A2_vaddws : 1350Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">; 1351 1352def int_hexagon_A2_vavgh : 1353Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">; 1354 1355def int_hexagon_A2_vavghcr : 1356Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">; 1357 1358def int_hexagon_A2_vavghr : 1359Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">; 1360 1361def int_hexagon_A2_vavgub : 1362Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">; 1363 1364def int_hexagon_A2_vavgubr : 1365Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">; 1366 1367def int_hexagon_A2_vavguh : 1368Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">; 1369 1370def int_hexagon_A2_vavguhr : 1371Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">; 1372 1373def int_hexagon_A2_vavguw : 1374Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">; 1375 1376def int_hexagon_A2_vavguwr : 1377Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">; 1378 1379def int_hexagon_A2_vavgw : 1380Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">; 1381 1382def int_hexagon_A2_vavgwcr : 1383Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">; 1384 1385def int_hexagon_A2_vavgwr : 1386Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">; 1387 1388def int_hexagon_A2_vcmpbeq : 1389Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">; 1390 1391def int_hexagon_A2_vcmpbgtu : 1392Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">; 1393 1394def int_hexagon_A2_vcmpheq : 1395Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">; 1396 1397def int_hexagon_A2_vcmphgt : 1398Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">; 1399 1400def int_hexagon_A2_vcmphgtu : 1401Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">; 1402 1403def int_hexagon_A2_vcmpweq : 1404Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">; 1405 1406def int_hexagon_A2_vcmpwgt : 1407Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">; 1408 1409def int_hexagon_A2_vcmpwgtu : 1410Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">; 1411 1412def int_hexagon_A2_vconj : 1413Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">; 1414 1415def int_hexagon_A2_vmaxb : 1416Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">; 1417 1418def int_hexagon_A2_vmaxh : 1419Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">; 1420 1421def int_hexagon_A2_vmaxub : 1422Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">; 1423 1424def int_hexagon_A2_vmaxuh : 1425Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">; 1426 1427def int_hexagon_A2_vmaxuw : 1428Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">; 1429 1430def int_hexagon_A2_vmaxw : 1431Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">; 1432 1433def int_hexagon_A2_vminb : 1434Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">; 1435 1436def int_hexagon_A2_vminh : 1437Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">; 1438 1439def int_hexagon_A2_vminub : 1440Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">; 1441 1442def int_hexagon_A2_vminuh : 1443Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">; 1444 1445def int_hexagon_A2_vminuw : 1446Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">; 1447 1448def int_hexagon_A2_vminw : 1449Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">; 1450 1451def int_hexagon_A2_vnavgh : 1452Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">; 1453 1454def int_hexagon_A2_vnavghcr : 1455Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">; 1456 1457def int_hexagon_A2_vnavghr : 1458Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">; 1459 1460def int_hexagon_A2_vnavgw : 1461Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">; 1462 1463def int_hexagon_A2_vnavgwcr : 1464Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">; 1465 1466def int_hexagon_A2_vnavgwr : 1467Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">; 1468 1469def int_hexagon_A2_vraddub : 1470Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">; 1471 1472def int_hexagon_A2_vraddub_acc : 1473Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">; 1474 1475def int_hexagon_A2_vrsadub : 1476Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">; 1477 1478def int_hexagon_A2_vrsadub_acc : 1479Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">; 1480 1481def int_hexagon_A2_vsubb_map : 1482Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">; 1483 1484def int_hexagon_A2_vsubh : 1485Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">; 1486 1487def int_hexagon_A2_vsubhs : 1488Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">; 1489 1490def int_hexagon_A2_vsubub : 1491Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">; 1492 1493def int_hexagon_A2_vsububs : 1494Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">; 1495 1496def int_hexagon_A2_vsubuhs : 1497Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">; 1498 1499def int_hexagon_A2_vsubw : 1500Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">; 1501 1502def int_hexagon_A2_vsubws : 1503Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">; 1504 1505def int_hexagon_A2_xor : 1506Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">; 1507 1508def int_hexagon_A2_xorp : 1509Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">; 1510 1511def int_hexagon_A2_zxtb : 1512Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">; 1513 1514def int_hexagon_A2_zxth : 1515Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">; 1516 1517def int_hexagon_A4_andn : 1518Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">; 1519 1520def int_hexagon_A4_andnp : 1521Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">; 1522 1523def int_hexagon_A4_bitsplit : 1524Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">; 1525 1526def int_hexagon_A4_bitspliti : 1527Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1528 1529def int_hexagon_A4_boundscheck : 1530Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">; 1531 1532def int_hexagon_A4_cmpbeq : 1533Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">; 1534 1535def int_hexagon_A4_cmpbeqi : 1536Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1537 1538def int_hexagon_A4_cmpbgt : 1539Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">; 1540 1541def int_hexagon_A4_cmpbgti : 1542Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1543 1544def int_hexagon_A4_cmpbgtu : 1545Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">; 1546 1547def int_hexagon_A4_cmpbgtui : 1548Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1549 1550def int_hexagon_A4_cmpheq : 1551Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">; 1552 1553def int_hexagon_A4_cmpheqi : 1554Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1555 1556def int_hexagon_A4_cmphgt : 1557Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">; 1558 1559def int_hexagon_A4_cmphgti : 1560Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1561 1562def int_hexagon_A4_cmphgtu : 1563Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">; 1564 1565def int_hexagon_A4_cmphgtui : 1566Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1567 1568def int_hexagon_A4_combineir : 1569Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1570 1571def int_hexagon_A4_combineri : 1572Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1573 1574def int_hexagon_A4_cround_ri : 1575Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1576 1577def int_hexagon_A4_cround_rr : 1578Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">; 1579 1580def int_hexagon_A4_modwrapu : 1581Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">; 1582 1583def int_hexagon_A4_orn : 1584Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">; 1585 1586def int_hexagon_A4_ornp : 1587Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">; 1588 1589def int_hexagon_A4_rcmpeq : 1590Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">; 1591 1592def int_hexagon_A4_rcmpeqi : 1593Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1594 1595def int_hexagon_A4_rcmpneq : 1596Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">; 1597 1598def int_hexagon_A4_rcmpneqi : 1599Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1600 1601def int_hexagon_A4_round_ri : 1602Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1603 1604def int_hexagon_A4_round_ri_sat : 1605Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1606 1607def int_hexagon_A4_round_rr : 1608Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">; 1609 1610def int_hexagon_A4_round_rr_sat : 1611Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">; 1612 1613def int_hexagon_A4_tlbmatch : 1614Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">; 1615 1616def int_hexagon_A4_vcmpbeq_any : 1617Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">; 1618 1619def int_hexagon_A4_vcmpbeqi : 1620Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1621 1622def int_hexagon_A4_vcmpbgt : 1623Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">; 1624 1625def int_hexagon_A4_vcmpbgti : 1626Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1627 1628def int_hexagon_A4_vcmpbgtui : 1629Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1630 1631def int_hexagon_A4_vcmpheqi : 1632Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1633 1634def int_hexagon_A4_vcmphgti : 1635Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1636 1637def int_hexagon_A4_vcmphgtui : 1638Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1639 1640def int_hexagon_A4_vcmpweqi : 1641Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1642 1643def int_hexagon_A4_vcmpwgti : 1644Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1645 1646def int_hexagon_A4_vcmpwgtui : 1647Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1648 1649def int_hexagon_A4_vrmaxh : 1650Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">; 1651 1652def int_hexagon_A4_vrmaxuh : 1653Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">; 1654 1655def int_hexagon_A4_vrmaxuw : 1656Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">; 1657 1658def int_hexagon_A4_vrmaxw : 1659Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">; 1660 1661def int_hexagon_A4_vrminh : 1662Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">; 1663 1664def int_hexagon_A4_vrminuh : 1665Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">; 1666 1667def int_hexagon_A4_vrminuw : 1668Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">; 1669 1670def int_hexagon_A4_vrminw : 1671Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">; 1672 1673def int_hexagon_A5_vaddhubs : 1674Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">; 1675 1676def int_hexagon_C2_all8 : 1677Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">; 1678 1679def int_hexagon_C2_and : 1680Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">; 1681 1682def int_hexagon_C2_andn : 1683Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">; 1684 1685def int_hexagon_C2_any8 : 1686Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">; 1687 1688def int_hexagon_C2_bitsclr : 1689Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">; 1690 1691def int_hexagon_C2_bitsclri : 1692Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1693 1694def int_hexagon_C2_bitsset : 1695Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">; 1696 1697def int_hexagon_C2_cmpeq : 1698Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">; 1699 1700def int_hexagon_C2_cmpeqi : 1701Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1702 1703def int_hexagon_C2_cmpeqp : 1704Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">; 1705 1706def int_hexagon_C2_cmpgei : 1707Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1708 1709def int_hexagon_C2_cmpgeui : 1710Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1711 1712def int_hexagon_C2_cmpgt : 1713Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">; 1714 1715def int_hexagon_C2_cmpgti : 1716Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1717 1718def int_hexagon_C2_cmpgtp : 1719Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">; 1720 1721def int_hexagon_C2_cmpgtu : 1722Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">; 1723 1724def int_hexagon_C2_cmpgtui : 1725Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1726 1727def int_hexagon_C2_cmpgtup : 1728Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">; 1729 1730def int_hexagon_C2_cmplt : 1731Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">; 1732 1733def int_hexagon_C2_cmpltu : 1734Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">; 1735 1736def int_hexagon_C2_mask : 1737Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">; 1738 1739def int_hexagon_C2_mux : 1740Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">; 1741 1742def int_hexagon_C2_muxii : 1743Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 1744 1745def int_hexagon_C2_muxir : 1746Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1747 1748def int_hexagon_C2_muxri : 1749Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1750 1751def int_hexagon_C2_not : 1752Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">; 1753 1754def int_hexagon_C2_or : 1755Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">; 1756 1757def int_hexagon_C2_orn : 1758Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">; 1759 1760def int_hexagon_C2_pxfer_map : 1761Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">; 1762 1763def int_hexagon_C2_tfrpr : 1764Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">; 1765 1766def int_hexagon_C2_tfrrp : 1767Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">; 1768 1769def int_hexagon_C2_vitpack : 1770Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">; 1771 1772def int_hexagon_C2_vmux : 1773Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">; 1774 1775def int_hexagon_C2_xor : 1776Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">; 1777 1778def int_hexagon_C4_and_and : 1779Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">; 1780 1781def int_hexagon_C4_and_andn : 1782Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">; 1783 1784def int_hexagon_C4_and_or : 1785Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">; 1786 1787def int_hexagon_C4_and_orn : 1788Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">; 1789 1790def int_hexagon_C4_cmplte : 1791Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">; 1792 1793def int_hexagon_C4_cmpltei : 1794Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1795 1796def int_hexagon_C4_cmplteu : 1797Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">; 1798 1799def int_hexagon_C4_cmplteui : 1800Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1801 1802def int_hexagon_C4_cmpneq : 1803Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">; 1804 1805def int_hexagon_C4_cmpneqi : 1806Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1807 1808def int_hexagon_C4_fastcorner9 : 1809Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">; 1810 1811def int_hexagon_C4_fastcorner9_not : 1812Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">; 1813 1814def int_hexagon_C4_nbitsclr : 1815Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">; 1816 1817def int_hexagon_C4_nbitsclri : 1818Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1819 1820def int_hexagon_C4_nbitsset : 1821Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">; 1822 1823def int_hexagon_C4_or_and : 1824Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">; 1825 1826def int_hexagon_C4_or_andn : 1827Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">; 1828 1829def int_hexagon_C4_or_or : 1830Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">; 1831 1832def int_hexagon_C4_or_orn : 1833Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">; 1834 1835def int_hexagon_F2_conv_d2df : 1836Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">; 1837 1838def int_hexagon_F2_conv_d2sf : 1839Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">; 1840 1841def int_hexagon_F2_conv_df2d : 1842Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">; 1843 1844def int_hexagon_F2_conv_df2d_chop : 1845Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">; 1846 1847def int_hexagon_F2_conv_df2sf : 1848Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">; 1849 1850def int_hexagon_F2_conv_df2ud : 1851Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">; 1852 1853def int_hexagon_F2_conv_df2ud_chop : 1854Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">; 1855 1856def int_hexagon_F2_conv_df2uw : 1857Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">; 1858 1859def int_hexagon_F2_conv_df2uw_chop : 1860Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">; 1861 1862def int_hexagon_F2_conv_df2w : 1863Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">; 1864 1865def int_hexagon_F2_conv_df2w_chop : 1866Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">; 1867 1868def int_hexagon_F2_conv_sf2d : 1869Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">; 1870 1871def int_hexagon_F2_conv_sf2d_chop : 1872Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">; 1873 1874def int_hexagon_F2_conv_sf2df : 1875Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">; 1876 1877def int_hexagon_F2_conv_sf2ud : 1878Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">; 1879 1880def int_hexagon_F2_conv_sf2ud_chop : 1881Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">; 1882 1883def int_hexagon_F2_conv_sf2uw : 1884Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">; 1885 1886def int_hexagon_F2_conv_sf2uw_chop : 1887Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">; 1888 1889def int_hexagon_F2_conv_sf2w : 1890Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">; 1891 1892def int_hexagon_F2_conv_sf2w_chop : 1893Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">; 1894 1895def int_hexagon_F2_conv_ud2df : 1896Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">; 1897 1898def int_hexagon_F2_conv_ud2sf : 1899Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">; 1900 1901def int_hexagon_F2_conv_uw2df : 1902Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">; 1903 1904def int_hexagon_F2_conv_uw2sf : 1905Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">; 1906 1907def int_hexagon_F2_conv_w2df : 1908Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">; 1909 1910def int_hexagon_F2_conv_w2sf : 1911Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">; 1912 1913def int_hexagon_F2_dfclass : 1914Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [IntrNoMem, Throws, ImmArg<ArgIndex<1>>]>; 1915 1916def int_hexagon_F2_dfcmpeq : 1917Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq", [IntrNoMem, Throws]>; 1918 1919def int_hexagon_F2_dfcmpge : 1920Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge", [IntrNoMem, Throws]>; 1921 1922def int_hexagon_F2_dfcmpgt : 1923Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt", [IntrNoMem, Throws]>; 1924 1925def int_hexagon_F2_dfcmpuo : 1926Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo", [IntrNoMem, Throws]>; 1927 1928def int_hexagon_F2_dfimm_n : 1929Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 1930 1931def int_hexagon_F2_dfimm_p : 1932Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 1933 1934def int_hexagon_F2_sfadd : 1935Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd", [IntrNoMem, Throws]>; 1936 1937def int_hexagon_F2_sfclass : 1938Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass", [IntrNoMem, Throws, ImmArg<ArgIndex<1>>]>; 1939 1940def int_hexagon_F2_sfcmpeq : 1941Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq", [IntrNoMem, Throws]>; 1942 1943def int_hexagon_F2_sfcmpge : 1944Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge", [IntrNoMem, Throws]>; 1945 1946def int_hexagon_F2_sfcmpgt : 1947Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt", [IntrNoMem, Throws]>; 1948 1949def int_hexagon_F2_sfcmpuo : 1950Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo", [IntrNoMem, Throws]>; 1951 1952def int_hexagon_F2_sffixupd : 1953Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd", [IntrNoMem, Throws]>; 1954 1955def int_hexagon_F2_sffixupn : 1956Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn", [IntrNoMem, Throws]>; 1957 1958def int_hexagon_F2_sffixupr : 1959Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr", [IntrNoMem, Throws]>; 1960 1961def int_hexagon_F2_sffma : 1962Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma", [IntrNoMem, Throws]>; 1963 1964def int_hexagon_F2_sffma_lib : 1965Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib", [IntrNoMem, Throws]>; 1966 1967def int_hexagon_F2_sffma_sc : 1968Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc", [IntrNoMem, Throws]>; 1969 1970def int_hexagon_F2_sffms : 1971Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms", [IntrNoMem, Throws]>; 1972 1973def int_hexagon_F2_sffms_lib : 1974Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib", [IntrNoMem, Throws]>; 1975 1976def int_hexagon_F2_sfimm_n : 1977Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 1978 1979def int_hexagon_F2_sfimm_p : 1980Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 1981 1982def int_hexagon_F2_sfmax : 1983Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax", [IntrNoMem, Throws]>; 1984 1985def int_hexagon_F2_sfmin : 1986Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin", [IntrNoMem, Throws]>; 1987 1988def int_hexagon_F2_sfmpy : 1989Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy", [IntrNoMem, Throws]>; 1990 1991def int_hexagon_F2_sfsub : 1992Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub", [IntrNoMem, Throws]>; 1993 1994def int_hexagon_M2_acci : 1995Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">; 1996 1997def int_hexagon_M2_accii : 1998Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1999 2000def int_hexagon_M2_cmaci_s0 : 2001Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">; 2002 2003def int_hexagon_M2_cmacr_s0 : 2004Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">; 2005 2006def int_hexagon_M2_cmacs_s0 : 2007Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">; 2008 2009def int_hexagon_M2_cmacs_s1 : 2010Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">; 2011 2012def int_hexagon_M2_cmacsc_s0 : 2013Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">; 2014 2015def int_hexagon_M2_cmacsc_s1 : 2016Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">; 2017 2018def int_hexagon_M2_cmpyi_s0 : 2019Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">; 2020 2021def int_hexagon_M2_cmpyr_s0 : 2022Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">; 2023 2024def int_hexagon_M2_cmpyrs_s0 : 2025Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">; 2026 2027def int_hexagon_M2_cmpyrs_s1 : 2028Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">; 2029 2030def int_hexagon_M2_cmpyrsc_s0 : 2031Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">; 2032 2033def int_hexagon_M2_cmpyrsc_s1 : 2034Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">; 2035 2036def int_hexagon_M2_cmpys_s0 : 2037Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">; 2038 2039def int_hexagon_M2_cmpys_s1 : 2040Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s1">; 2041 2042def int_hexagon_M2_cmpysc_s0 : 2043Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">; 2044 2045def int_hexagon_M2_cmpysc_s1 : 2046Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">; 2047 2048def int_hexagon_M2_cnacs_s0 : 2049Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">; 2050 2051def int_hexagon_M2_cnacs_s1 : 2052Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">; 2053 2054def int_hexagon_M2_cnacsc_s0 : 2055Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">; 2056 2057def int_hexagon_M2_cnacsc_s1 : 2058Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">; 2059 2060def int_hexagon_M2_dpmpyss_acc_s0 : 2061Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">; 2062 2063def int_hexagon_M2_dpmpyss_nac_s0 : 2064Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">; 2065 2066def int_hexagon_M2_dpmpyss_rnd_s0 : 2067Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">; 2068 2069def int_hexagon_M2_dpmpyss_s0 : 2070Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">; 2071 2072def int_hexagon_M2_dpmpyuu_acc_s0 : 2073Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">; 2074 2075def int_hexagon_M2_dpmpyuu_nac_s0 : 2076Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">; 2077 2078def int_hexagon_M2_dpmpyuu_s0 : 2079Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">; 2080 2081def int_hexagon_M2_hmmpyh_rs1 : 2082Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">; 2083 2084def int_hexagon_M2_hmmpyh_s1 : 2085Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">; 2086 2087def int_hexagon_M2_hmmpyl_rs1 : 2088Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">; 2089 2090def int_hexagon_M2_hmmpyl_s1 : 2091Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">; 2092 2093def int_hexagon_M2_maci : 2094Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">; 2095 2096def int_hexagon_M2_macsin : 2097Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2098 2099def int_hexagon_M2_macsip : 2100Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2101 2102def int_hexagon_M2_mmachs_rs0 : 2103Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">; 2104 2105def int_hexagon_M2_mmachs_rs1 : 2106Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">; 2107 2108def int_hexagon_M2_mmachs_s0 : 2109Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">; 2110 2111def int_hexagon_M2_mmachs_s1 : 2112Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">; 2113 2114def int_hexagon_M2_mmacls_rs0 : 2115Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">; 2116 2117def int_hexagon_M2_mmacls_rs1 : 2118Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">; 2119 2120def int_hexagon_M2_mmacls_s0 : 2121Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">; 2122 2123def int_hexagon_M2_mmacls_s1 : 2124Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">; 2125 2126def int_hexagon_M2_mmacuhs_rs0 : 2127Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">; 2128 2129def int_hexagon_M2_mmacuhs_rs1 : 2130Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">; 2131 2132def int_hexagon_M2_mmacuhs_s0 : 2133Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">; 2134 2135def int_hexagon_M2_mmacuhs_s1 : 2136Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">; 2137 2138def int_hexagon_M2_mmaculs_rs0 : 2139Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">; 2140 2141def int_hexagon_M2_mmaculs_rs1 : 2142Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">; 2143 2144def int_hexagon_M2_mmaculs_s0 : 2145Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">; 2146 2147def int_hexagon_M2_mmaculs_s1 : 2148Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">; 2149 2150def int_hexagon_M2_mmpyh_rs0 : 2151Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">; 2152 2153def int_hexagon_M2_mmpyh_rs1 : 2154Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">; 2155 2156def int_hexagon_M2_mmpyh_s0 : 2157Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">; 2158 2159def int_hexagon_M2_mmpyh_s1 : 2160Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">; 2161 2162def int_hexagon_M2_mmpyl_rs0 : 2163Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">; 2164 2165def int_hexagon_M2_mmpyl_rs1 : 2166Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">; 2167 2168def int_hexagon_M2_mmpyl_s0 : 2169Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">; 2170 2171def int_hexagon_M2_mmpyl_s1 : 2172Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">; 2173 2174def int_hexagon_M2_mmpyuh_rs0 : 2175Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">; 2176 2177def int_hexagon_M2_mmpyuh_rs1 : 2178Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">; 2179 2180def int_hexagon_M2_mmpyuh_s0 : 2181Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">; 2182 2183def int_hexagon_M2_mmpyuh_s1 : 2184Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">; 2185 2186def int_hexagon_M2_mmpyul_rs0 : 2187Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">; 2188 2189def int_hexagon_M2_mmpyul_rs1 : 2190Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">; 2191 2192def int_hexagon_M2_mmpyul_s0 : 2193Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">; 2194 2195def int_hexagon_M2_mmpyul_s1 : 2196Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">; 2197 2198def int_hexagon_M2_mpy_acc_hh_s0 : 2199Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">; 2200 2201def int_hexagon_M2_mpy_acc_hh_s1 : 2202Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">; 2203 2204def int_hexagon_M2_mpy_acc_hl_s0 : 2205Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">; 2206 2207def int_hexagon_M2_mpy_acc_hl_s1 : 2208Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">; 2209 2210def int_hexagon_M2_mpy_acc_lh_s0 : 2211Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">; 2212 2213def int_hexagon_M2_mpy_acc_lh_s1 : 2214Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">; 2215 2216def int_hexagon_M2_mpy_acc_ll_s0 : 2217Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">; 2218 2219def int_hexagon_M2_mpy_acc_ll_s1 : 2220Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">; 2221 2222def int_hexagon_M2_mpy_acc_sat_hh_s0 : 2223Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">; 2224 2225def int_hexagon_M2_mpy_acc_sat_hh_s1 : 2226Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">; 2227 2228def int_hexagon_M2_mpy_acc_sat_hl_s0 : 2229Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">; 2230 2231def int_hexagon_M2_mpy_acc_sat_hl_s1 : 2232Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">; 2233 2234def int_hexagon_M2_mpy_acc_sat_lh_s0 : 2235Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">; 2236 2237def int_hexagon_M2_mpy_acc_sat_lh_s1 : 2238Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">; 2239 2240def int_hexagon_M2_mpy_acc_sat_ll_s0 : 2241Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">; 2242 2243def int_hexagon_M2_mpy_acc_sat_ll_s1 : 2244Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">; 2245 2246def int_hexagon_M2_mpy_hh_s0 : 2247Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">; 2248 2249def int_hexagon_M2_mpy_hh_s1 : 2250Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">; 2251 2252def int_hexagon_M2_mpy_hl_s0 : 2253Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">; 2254 2255def int_hexagon_M2_mpy_hl_s1 : 2256Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">; 2257 2258def int_hexagon_M2_mpy_lh_s0 : 2259Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">; 2260 2261def int_hexagon_M2_mpy_lh_s1 : 2262Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">; 2263 2264def int_hexagon_M2_mpy_ll_s0 : 2265Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">; 2266 2267def int_hexagon_M2_mpy_ll_s1 : 2268Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">; 2269 2270def int_hexagon_M2_mpy_nac_hh_s0 : 2271Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">; 2272 2273def int_hexagon_M2_mpy_nac_hh_s1 : 2274Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">; 2275 2276def int_hexagon_M2_mpy_nac_hl_s0 : 2277Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">; 2278 2279def int_hexagon_M2_mpy_nac_hl_s1 : 2280Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">; 2281 2282def int_hexagon_M2_mpy_nac_lh_s0 : 2283Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">; 2284 2285def int_hexagon_M2_mpy_nac_lh_s1 : 2286Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">; 2287 2288def int_hexagon_M2_mpy_nac_ll_s0 : 2289Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">; 2290 2291def int_hexagon_M2_mpy_nac_ll_s1 : 2292Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">; 2293 2294def int_hexagon_M2_mpy_nac_sat_hh_s0 : 2295Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">; 2296 2297def int_hexagon_M2_mpy_nac_sat_hh_s1 : 2298Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">; 2299 2300def int_hexagon_M2_mpy_nac_sat_hl_s0 : 2301Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">; 2302 2303def int_hexagon_M2_mpy_nac_sat_hl_s1 : 2304Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">; 2305 2306def int_hexagon_M2_mpy_nac_sat_lh_s0 : 2307Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">; 2308 2309def int_hexagon_M2_mpy_nac_sat_lh_s1 : 2310Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">; 2311 2312def int_hexagon_M2_mpy_nac_sat_ll_s0 : 2313Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">; 2314 2315def int_hexagon_M2_mpy_nac_sat_ll_s1 : 2316Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">; 2317 2318def int_hexagon_M2_mpy_rnd_hh_s0 : 2319Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">; 2320 2321def int_hexagon_M2_mpy_rnd_hh_s1 : 2322Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">; 2323 2324def int_hexagon_M2_mpy_rnd_hl_s0 : 2325Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">; 2326 2327def int_hexagon_M2_mpy_rnd_hl_s1 : 2328Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">; 2329 2330def int_hexagon_M2_mpy_rnd_lh_s0 : 2331Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">; 2332 2333def int_hexagon_M2_mpy_rnd_lh_s1 : 2334Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">; 2335 2336def int_hexagon_M2_mpy_rnd_ll_s0 : 2337Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">; 2338 2339def int_hexagon_M2_mpy_rnd_ll_s1 : 2340Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">; 2341 2342def int_hexagon_M2_mpy_sat_hh_s0 : 2343Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">; 2344 2345def int_hexagon_M2_mpy_sat_hh_s1 : 2346Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">; 2347 2348def int_hexagon_M2_mpy_sat_hl_s0 : 2349Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">; 2350 2351def int_hexagon_M2_mpy_sat_hl_s1 : 2352Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">; 2353 2354def int_hexagon_M2_mpy_sat_lh_s0 : 2355Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">; 2356 2357def int_hexagon_M2_mpy_sat_lh_s1 : 2358Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">; 2359 2360def int_hexagon_M2_mpy_sat_ll_s0 : 2361Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">; 2362 2363def int_hexagon_M2_mpy_sat_ll_s1 : 2364Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">; 2365 2366def int_hexagon_M2_mpy_sat_rnd_hh_s0 : 2367Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">; 2368 2369def int_hexagon_M2_mpy_sat_rnd_hh_s1 : 2370Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">; 2371 2372def int_hexagon_M2_mpy_sat_rnd_hl_s0 : 2373Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">; 2374 2375def int_hexagon_M2_mpy_sat_rnd_hl_s1 : 2376Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">; 2377 2378def int_hexagon_M2_mpy_sat_rnd_lh_s0 : 2379Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">; 2380 2381def int_hexagon_M2_mpy_sat_rnd_lh_s1 : 2382Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">; 2383 2384def int_hexagon_M2_mpy_sat_rnd_ll_s0 : 2385Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">; 2386 2387def int_hexagon_M2_mpy_sat_rnd_ll_s1 : 2388Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">; 2389 2390def int_hexagon_M2_mpy_up : 2391Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">; 2392 2393def int_hexagon_M2_mpy_up_s1 : 2394Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">; 2395 2396def int_hexagon_M2_mpy_up_s1_sat : 2397Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">; 2398 2399def int_hexagon_M2_mpyd_acc_hh_s0 : 2400Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">; 2401 2402def int_hexagon_M2_mpyd_acc_hh_s1 : 2403Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">; 2404 2405def int_hexagon_M2_mpyd_acc_hl_s0 : 2406Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">; 2407 2408def int_hexagon_M2_mpyd_acc_hl_s1 : 2409Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">; 2410 2411def int_hexagon_M2_mpyd_acc_lh_s0 : 2412Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">; 2413 2414def int_hexagon_M2_mpyd_acc_lh_s1 : 2415Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">; 2416 2417def int_hexagon_M2_mpyd_acc_ll_s0 : 2418Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">; 2419 2420def int_hexagon_M2_mpyd_acc_ll_s1 : 2421Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">; 2422 2423def int_hexagon_M2_mpyd_hh_s0 : 2424Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">; 2425 2426def int_hexagon_M2_mpyd_hh_s1 : 2427Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">; 2428 2429def int_hexagon_M2_mpyd_hl_s0 : 2430Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">; 2431 2432def int_hexagon_M2_mpyd_hl_s1 : 2433Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">; 2434 2435def int_hexagon_M2_mpyd_lh_s0 : 2436Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">; 2437 2438def int_hexagon_M2_mpyd_lh_s1 : 2439Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">; 2440 2441def int_hexagon_M2_mpyd_ll_s0 : 2442Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">; 2443 2444def int_hexagon_M2_mpyd_ll_s1 : 2445Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">; 2446 2447def int_hexagon_M2_mpyd_nac_hh_s0 : 2448Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">; 2449 2450def int_hexagon_M2_mpyd_nac_hh_s1 : 2451Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">; 2452 2453def int_hexagon_M2_mpyd_nac_hl_s0 : 2454Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">; 2455 2456def int_hexagon_M2_mpyd_nac_hl_s1 : 2457Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">; 2458 2459def int_hexagon_M2_mpyd_nac_lh_s0 : 2460Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">; 2461 2462def int_hexagon_M2_mpyd_nac_lh_s1 : 2463Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">; 2464 2465def int_hexagon_M2_mpyd_nac_ll_s0 : 2466Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">; 2467 2468def int_hexagon_M2_mpyd_nac_ll_s1 : 2469Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">; 2470 2471def int_hexagon_M2_mpyd_rnd_hh_s0 : 2472Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">; 2473 2474def int_hexagon_M2_mpyd_rnd_hh_s1 : 2475Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">; 2476 2477def int_hexagon_M2_mpyd_rnd_hl_s0 : 2478Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">; 2479 2480def int_hexagon_M2_mpyd_rnd_hl_s1 : 2481Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">; 2482 2483def int_hexagon_M2_mpyd_rnd_lh_s0 : 2484Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">; 2485 2486def int_hexagon_M2_mpyd_rnd_lh_s1 : 2487Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">; 2488 2489def int_hexagon_M2_mpyd_rnd_ll_s0 : 2490Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">; 2491 2492def int_hexagon_M2_mpyd_rnd_ll_s1 : 2493Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">; 2494 2495def int_hexagon_M2_mpyi : 2496Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">; 2497 2498def int_hexagon_M2_mpysmi : 2499Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2500 2501def int_hexagon_M2_mpysu_up : 2502Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">; 2503 2504def int_hexagon_M2_mpyu_acc_hh_s0 : 2505Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">; 2506 2507def int_hexagon_M2_mpyu_acc_hh_s1 : 2508Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">; 2509 2510def int_hexagon_M2_mpyu_acc_hl_s0 : 2511Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">; 2512 2513def int_hexagon_M2_mpyu_acc_hl_s1 : 2514Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">; 2515 2516def int_hexagon_M2_mpyu_acc_lh_s0 : 2517Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">; 2518 2519def int_hexagon_M2_mpyu_acc_lh_s1 : 2520Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">; 2521 2522def int_hexagon_M2_mpyu_acc_ll_s0 : 2523Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">; 2524 2525def int_hexagon_M2_mpyu_acc_ll_s1 : 2526Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">; 2527 2528def int_hexagon_M2_mpyu_hh_s0 : 2529Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">; 2530 2531def int_hexagon_M2_mpyu_hh_s1 : 2532Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">; 2533 2534def int_hexagon_M2_mpyu_hl_s0 : 2535Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">; 2536 2537def int_hexagon_M2_mpyu_hl_s1 : 2538Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">; 2539 2540def int_hexagon_M2_mpyu_lh_s0 : 2541Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">; 2542 2543def int_hexagon_M2_mpyu_lh_s1 : 2544Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">; 2545 2546def int_hexagon_M2_mpyu_ll_s0 : 2547Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">; 2548 2549def int_hexagon_M2_mpyu_ll_s1 : 2550Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">; 2551 2552def int_hexagon_M2_mpyu_nac_hh_s0 : 2553Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">; 2554 2555def int_hexagon_M2_mpyu_nac_hh_s1 : 2556Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">; 2557 2558def int_hexagon_M2_mpyu_nac_hl_s0 : 2559Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">; 2560 2561def int_hexagon_M2_mpyu_nac_hl_s1 : 2562Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">; 2563 2564def int_hexagon_M2_mpyu_nac_lh_s0 : 2565Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">; 2566 2567def int_hexagon_M2_mpyu_nac_lh_s1 : 2568Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">; 2569 2570def int_hexagon_M2_mpyu_nac_ll_s0 : 2571Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">; 2572 2573def int_hexagon_M2_mpyu_nac_ll_s1 : 2574Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">; 2575 2576def int_hexagon_M2_mpyu_up : 2577Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">; 2578 2579def int_hexagon_M2_mpyud_acc_hh_s0 : 2580Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">; 2581 2582def int_hexagon_M2_mpyud_acc_hh_s1 : 2583Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">; 2584 2585def int_hexagon_M2_mpyud_acc_hl_s0 : 2586Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">; 2587 2588def int_hexagon_M2_mpyud_acc_hl_s1 : 2589Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">; 2590 2591def int_hexagon_M2_mpyud_acc_lh_s0 : 2592Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">; 2593 2594def int_hexagon_M2_mpyud_acc_lh_s1 : 2595Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">; 2596 2597def int_hexagon_M2_mpyud_acc_ll_s0 : 2598Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">; 2599 2600def int_hexagon_M2_mpyud_acc_ll_s1 : 2601Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">; 2602 2603def int_hexagon_M2_mpyud_hh_s0 : 2604Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">; 2605 2606def int_hexagon_M2_mpyud_hh_s1 : 2607Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">; 2608 2609def int_hexagon_M2_mpyud_hl_s0 : 2610Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">; 2611 2612def int_hexagon_M2_mpyud_hl_s1 : 2613Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">; 2614 2615def int_hexagon_M2_mpyud_lh_s0 : 2616Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">; 2617 2618def int_hexagon_M2_mpyud_lh_s1 : 2619Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">; 2620 2621def int_hexagon_M2_mpyud_ll_s0 : 2622Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">; 2623 2624def int_hexagon_M2_mpyud_ll_s1 : 2625Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">; 2626 2627def int_hexagon_M2_mpyud_nac_hh_s0 : 2628Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">; 2629 2630def int_hexagon_M2_mpyud_nac_hh_s1 : 2631Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">; 2632 2633def int_hexagon_M2_mpyud_nac_hl_s0 : 2634Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">; 2635 2636def int_hexagon_M2_mpyud_nac_hl_s1 : 2637Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">; 2638 2639def int_hexagon_M2_mpyud_nac_lh_s0 : 2640Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">; 2641 2642def int_hexagon_M2_mpyud_nac_lh_s1 : 2643Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">; 2644 2645def int_hexagon_M2_mpyud_nac_ll_s0 : 2646Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">; 2647 2648def int_hexagon_M2_mpyud_nac_ll_s1 : 2649Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">; 2650 2651def int_hexagon_M2_mpyui : 2652Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">; 2653 2654def int_hexagon_M2_nacci : 2655Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">; 2656 2657def int_hexagon_M2_naccii : 2658Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2659 2660def int_hexagon_M2_subacc : 2661Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">; 2662 2663def int_hexagon_M2_vabsdiffh : 2664Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">; 2665 2666def int_hexagon_M2_vabsdiffw : 2667Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">; 2668 2669def int_hexagon_M2_vcmac_s0_sat_i : 2670Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">; 2671 2672def int_hexagon_M2_vcmac_s0_sat_r : 2673Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">; 2674 2675def int_hexagon_M2_vcmpy_s0_sat_i : 2676Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">; 2677 2678def int_hexagon_M2_vcmpy_s0_sat_r : 2679Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">; 2680 2681def int_hexagon_M2_vcmpy_s1_sat_i : 2682Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">; 2683 2684def int_hexagon_M2_vcmpy_s1_sat_r : 2685Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">; 2686 2687def int_hexagon_M2_vdmacs_s0 : 2688Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">; 2689 2690def int_hexagon_M2_vdmacs_s1 : 2691Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">; 2692 2693def int_hexagon_M2_vdmpyrs_s0 : 2694Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">; 2695 2696def int_hexagon_M2_vdmpyrs_s1 : 2697Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">; 2698 2699def int_hexagon_M2_vdmpys_s0 : 2700Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">; 2701 2702def int_hexagon_M2_vdmpys_s1 : 2703Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">; 2704 2705def int_hexagon_M2_vmac2 : 2706Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">; 2707 2708def int_hexagon_M2_vmac2es : 2709Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">; 2710 2711def int_hexagon_M2_vmac2es_s0 : 2712Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">; 2713 2714def int_hexagon_M2_vmac2es_s1 : 2715Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">; 2716 2717def int_hexagon_M2_vmac2s_s0 : 2718Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">; 2719 2720def int_hexagon_M2_vmac2s_s1 : 2721Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">; 2722 2723def int_hexagon_M2_vmac2su_s0 : 2724Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">; 2725 2726def int_hexagon_M2_vmac2su_s1 : 2727Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">; 2728 2729def int_hexagon_M2_vmpy2es_s0 : 2730Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">; 2731 2732def int_hexagon_M2_vmpy2es_s1 : 2733Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">; 2734 2735def int_hexagon_M2_vmpy2s_s0 : 2736Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">; 2737 2738def int_hexagon_M2_vmpy2s_s0pack : 2739Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">; 2740 2741def int_hexagon_M2_vmpy2s_s1 : 2742Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">; 2743 2744def int_hexagon_M2_vmpy2s_s1pack : 2745Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">; 2746 2747def int_hexagon_M2_vmpy2su_s0 : 2748Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">; 2749 2750def int_hexagon_M2_vmpy2su_s1 : 2751Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">; 2752 2753def int_hexagon_M2_vraddh : 2754Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">; 2755 2756def int_hexagon_M2_vradduh : 2757Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">; 2758 2759def int_hexagon_M2_vrcmaci_s0 : 2760Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">; 2761 2762def int_hexagon_M2_vrcmaci_s0c : 2763Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">; 2764 2765def int_hexagon_M2_vrcmacr_s0 : 2766Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">; 2767 2768def int_hexagon_M2_vrcmacr_s0c : 2769Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">; 2770 2771def int_hexagon_M2_vrcmpyi_s0 : 2772Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">; 2773 2774def int_hexagon_M2_vrcmpyi_s0c : 2775Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">; 2776 2777def int_hexagon_M2_vrcmpyr_s0 : 2778Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">; 2779 2780def int_hexagon_M2_vrcmpyr_s0c : 2781Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">; 2782 2783def int_hexagon_M2_vrcmpys_acc_s1 : 2784Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">; 2785 2786def int_hexagon_M2_vrcmpys_s1 : 2787Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">; 2788 2789def int_hexagon_M2_vrcmpys_s1rp : 2790Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">; 2791 2792def int_hexagon_M2_vrmac_s0 : 2793Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">; 2794 2795def int_hexagon_M2_vrmpy_s0 : 2796Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">; 2797 2798def int_hexagon_M2_xor_xacc : 2799Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">; 2800 2801def int_hexagon_M4_and_and : 2802Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">; 2803 2804def int_hexagon_M4_and_andn : 2805Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">; 2806 2807def int_hexagon_M4_and_or : 2808Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">; 2809 2810def int_hexagon_M4_and_xor : 2811Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">; 2812 2813def int_hexagon_M4_cmpyi_wh : 2814Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">; 2815 2816def int_hexagon_M4_cmpyi_whc : 2817Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">; 2818 2819def int_hexagon_M4_cmpyr_wh : 2820Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">; 2821 2822def int_hexagon_M4_cmpyr_whc : 2823Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">; 2824 2825def int_hexagon_M4_mac_up_s1_sat : 2826Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">; 2827 2828def int_hexagon_M4_mpyri_addi : 2829Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 2830 2831def int_hexagon_M4_mpyri_addr : 2832Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2833 2834def int_hexagon_M4_mpyri_addr_u2 : 2835Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2836 2837def int_hexagon_M4_mpyrr_addi : 2838Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 2839 2840def int_hexagon_M4_mpyrr_addr : 2841Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">; 2842 2843def int_hexagon_M4_nac_up_s1_sat : 2844Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">; 2845 2846def int_hexagon_M4_or_and : 2847Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">; 2848 2849def int_hexagon_M4_or_andn : 2850Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">; 2851 2852def int_hexagon_M4_or_or : 2853Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">; 2854 2855def int_hexagon_M4_or_xor : 2856Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">; 2857 2858def int_hexagon_M4_pmpyw : 2859Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">; 2860 2861def int_hexagon_M4_pmpyw_acc : 2862Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">; 2863 2864def int_hexagon_M4_vpmpyh : 2865Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">; 2866 2867def int_hexagon_M4_vpmpyh_acc : 2868Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">; 2869 2870def int_hexagon_M4_vrmpyeh_acc_s0 : 2871Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">; 2872 2873def int_hexagon_M4_vrmpyeh_acc_s1 : 2874Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">; 2875 2876def int_hexagon_M4_vrmpyeh_s0 : 2877Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">; 2878 2879def int_hexagon_M4_vrmpyeh_s1 : 2880Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">; 2881 2882def int_hexagon_M4_vrmpyoh_acc_s0 : 2883Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">; 2884 2885def int_hexagon_M4_vrmpyoh_acc_s1 : 2886Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">; 2887 2888def int_hexagon_M4_vrmpyoh_s0 : 2889Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">; 2890 2891def int_hexagon_M4_vrmpyoh_s1 : 2892Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">; 2893 2894def int_hexagon_M4_xor_and : 2895Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">; 2896 2897def int_hexagon_M4_xor_andn : 2898Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">; 2899 2900def int_hexagon_M4_xor_or : 2901Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">; 2902 2903def int_hexagon_M4_xor_xacc : 2904Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">; 2905 2906def int_hexagon_M5_vdmacbsu : 2907Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">; 2908 2909def int_hexagon_M5_vdmpybsu : 2910Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">; 2911 2912def int_hexagon_M5_vmacbsu : 2913Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">; 2914 2915def int_hexagon_M5_vmacbuu : 2916Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">; 2917 2918def int_hexagon_M5_vmpybsu : 2919Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">; 2920 2921def int_hexagon_M5_vmpybuu : 2922Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">; 2923 2924def int_hexagon_M5_vrmacbsu : 2925Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">; 2926 2927def int_hexagon_M5_vrmacbuu : 2928Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">; 2929 2930def int_hexagon_M5_vrmpybsu : 2931Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">; 2932 2933def int_hexagon_M5_vrmpybuu : 2934Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">; 2935 2936def int_hexagon_S2_addasl_rrri : 2937Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2938 2939def int_hexagon_S2_asl_i_p : 2940Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2941 2942def int_hexagon_S2_asl_i_p_acc : 2943Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2944 2945def int_hexagon_S2_asl_i_p_and : 2946Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2947 2948def int_hexagon_S2_asl_i_p_nac : 2949Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2950 2951def int_hexagon_S2_asl_i_p_or : 2952Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2953 2954def int_hexagon_S2_asl_i_p_xacc : 2955Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2956 2957def int_hexagon_S2_asl_i_r : 2958Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2959 2960def int_hexagon_S2_asl_i_r_acc : 2961Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2962 2963def int_hexagon_S2_asl_i_r_and : 2964Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2965 2966def int_hexagon_S2_asl_i_r_nac : 2967Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2968 2969def int_hexagon_S2_asl_i_r_or : 2970Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2971 2972def int_hexagon_S2_asl_i_r_sat : 2973Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2974 2975def int_hexagon_S2_asl_i_r_xacc : 2976Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2977 2978def int_hexagon_S2_asl_i_vh : 2979Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2980 2981def int_hexagon_S2_asl_i_vw : 2982Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2983 2984def int_hexagon_S2_asl_r_p : 2985Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">; 2986 2987def int_hexagon_S2_asl_r_p_acc : 2988Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">; 2989 2990def int_hexagon_S2_asl_r_p_and : 2991Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">; 2992 2993def int_hexagon_S2_asl_r_p_nac : 2994Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">; 2995 2996def int_hexagon_S2_asl_r_p_or : 2997Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">; 2998 2999def int_hexagon_S2_asl_r_p_xor : 3000Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">; 3001 3002def int_hexagon_S2_asl_r_r : 3003Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">; 3004 3005def int_hexagon_S2_asl_r_r_acc : 3006Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">; 3007 3008def int_hexagon_S2_asl_r_r_and : 3009Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">; 3010 3011def int_hexagon_S2_asl_r_r_nac : 3012Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">; 3013 3014def int_hexagon_S2_asl_r_r_or : 3015Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">; 3016 3017def int_hexagon_S2_asl_r_r_sat : 3018Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">; 3019 3020def int_hexagon_S2_asl_r_vh : 3021Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">; 3022 3023def int_hexagon_S2_asl_r_vw : 3024Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">; 3025 3026def int_hexagon_S2_asr_i_p : 3027Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3028 3029def int_hexagon_S2_asr_i_p_acc : 3030Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3031 3032def int_hexagon_S2_asr_i_p_and : 3033Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3034 3035def int_hexagon_S2_asr_i_p_nac : 3036Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3037 3038def int_hexagon_S2_asr_i_p_or : 3039Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3040 3041def int_hexagon_S2_asr_i_p_rnd : 3042Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3043 3044def int_hexagon_S2_asr_i_p_rnd_goodsyntax : 3045Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3046 3047def int_hexagon_S2_asr_i_r : 3048Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3049 3050def int_hexagon_S2_asr_i_r_acc : 3051Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3052 3053def int_hexagon_S2_asr_i_r_and : 3054Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3055 3056def int_hexagon_S2_asr_i_r_nac : 3057Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3058 3059def int_hexagon_S2_asr_i_r_or : 3060Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3061 3062def int_hexagon_S2_asr_i_r_rnd : 3063Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3064 3065def int_hexagon_S2_asr_i_r_rnd_goodsyntax : 3066Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3067 3068def int_hexagon_S2_asr_i_svw_trun : 3069Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3070 3071def int_hexagon_S2_asr_i_vh : 3072Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3073 3074def int_hexagon_S2_asr_i_vw : 3075Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3076 3077def int_hexagon_S2_asr_r_p : 3078Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">; 3079 3080def int_hexagon_S2_asr_r_p_acc : 3081Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">; 3082 3083def int_hexagon_S2_asr_r_p_and : 3084Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">; 3085 3086def int_hexagon_S2_asr_r_p_nac : 3087Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">; 3088 3089def int_hexagon_S2_asr_r_p_or : 3090Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">; 3091 3092def int_hexagon_S2_asr_r_p_xor : 3093Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">; 3094 3095def int_hexagon_S2_asr_r_r : 3096Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">; 3097 3098def int_hexagon_S2_asr_r_r_acc : 3099Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">; 3100 3101def int_hexagon_S2_asr_r_r_and : 3102Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">; 3103 3104def int_hexagon_S2_asr_r_r_nac : 3105Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">; 3106 3107def int_hexagon_S2_asr_r_r_or : 3108Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">; 3109 3110def int_hexagon_S2_asr_r_r_sat : 3111Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">; 3112 3113def int_hexagon_S2_asr_r_svw_trun : 3114Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">; 3115 3116def int_hexagon_S2_asr_r_vh : 3117Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">; 3118 3119def int_hexagon_S2_asr_r_vw : 3120Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">; 3121 3122def int_hexagon_S2_brev : 3123Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">; 3124 3125def int_hexagon_S2_brevp : 3126Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">; 3127 3128def int_hexagon_S2_cl0 : 3129Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">; 3130 3131def int_hexagon_S2_cl0p : 3132Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">; 3133 3134def int_hexagon_S2_cl1 : 3135Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">; 3136 3137def int_hexagon_S2_cl1p : 3138Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">; 3139 3140def int_hexagon_S2_clb : 3141Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">; 3142 3143def int_hexagon_S2_clbnorm : 3144Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">; 3145 3146def int_hexagon_S2_clbp : 3147Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">; 3148 3149def int_hexagon_S2_clrbit_i : 3150Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3151 3152def int_hexagon_S2_clrbit_r : 3153Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">; 3154 3155def int_hexagon_S2_ct0 : 3156Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">; 3157 3158def int_hexagon_S2_ct0p : 3159Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">; 3160 3161def int_hexagon_S2_ct1 : 3162Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">; 3163 3164def int_hexagon_S2_ct1p : 3165Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">; 3166 3167def int_hexagon_S2_deinterleave : 3168Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">; 3169 3170def int_hexagon_S2_extractu : 3171Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3172 3173def int_hexagon_S2_extractu_rp : 3174Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">; 3175 3176def int_hexagon_S2_extractup : 3177Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3178 3179def int_hexagon_S2_extractup_rp : 3180Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">; 3181 3182def int_hexagon_S2_insert : 3183Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3184 3185def int_hexagon_S2_insert_rp : 3186Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">; 3187 3188def int_hexagon_S2_insertp : 3189Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3190 3191def int_hexagon_S2_insertp_rp : 3192Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">; 3193 3194def int_hexagon_S2_interleave : 3195Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">; 3196 3197def int_hexagon_S2_lfsp : 3198Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">; 3199 3200def int_hexagon_S2_lsl_r_p : 3201Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">; 3202 3203def int_hexagon_S2_lsl_r_p_acc : 3204Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">; 3205 3206def int_hexagon_S2_lsl_r_p_and : 3207Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">; 3208 3209def int_hexagon_S2_lsl_r_p_nac : 3210Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">; 3211 3212def int_hexagon_S2_lsl_r_p_or : 3213Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">; 3214 3215def int_hexagon_S2_lsl_r_p_xor : 3216Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">; 3217 3218def int_hexagon_S2_lsl_r_r : 3219Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">; 3220 3221def int_hexagon_S2_lsl_r_r_acc : 3222Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">; 3223 3224def int_hexagon_S2_lsl_r_r_and : 3225Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">; 3226 3227def int_hexagon_S2_lsl_r_r_nac : 3228Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">; 3229 3230def int_hexagon_S2_lsl_r_r_or : 3231Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">; 3232 3233def int_hexagon_S2_lsl_r_vh : 3234Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">; 3235 3236def int_hexagon_S2_lsl_r_vw : 3237Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">; 3238 3239def int_hexagon_S2_lsr_i_p : 3240Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3241 3242def int_hexagon_S2_lsr_i_p_acc : 3243Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3244 3245def int_hexagon_S2_lsr_i_p_and : 3246Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3247 3248def int_hexagon_S2_lsr_i_p_nac : 3249Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3250 3251def int_hexagon_S2_lsr_i_p_or : 3252Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3253 3254def int_hexagon_S2_lsr_i_p_xacc : 3255Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3256 3257def int_hexagon_S2_lsr_i_r : 3258Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3259 3260def int_hexagon_S2_lsr_i_r_acc : 3261Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3262 3263def int_hexagon_S2_lsr_i_r_and : 3264Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3265 3266def int_hexagon_S2_lsr_i_r_nac : 3267Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3268 3269def int_hexagon_S2_lsr_i_r_or : 3270Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3271 3272def int_hexagon_S2_lsr_i_r_xacc : 3273Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3274 3275def int_hexagon_S2_lsr_i_vh : 3276Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3277 3278def int_hexagon_S2_lsr_i_vw : 3279Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3280 3281def int_hexagon_S2_lsr_r_p : 3282Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">; 3283 3284def int_hexagon_S2_lsr_r_p_acc : 3285Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">; 3286 3287def int_hexagon_S2_lsr_r_p_and : 3288Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">; 3289 3290def int_hexagon_S2_lsr_r_p_nac : 3291Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">; 3292 3293def int_hexagon_S2_lsr_r_p_or : 3294Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">; 3295 3296def int_hexagon_S2_lsr_r_p_xor : 3297Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">; 3298 3299def int_hexagon_S2_lsr_r_r : 3300Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">; 3301 3302def int_hexagon_S2_lsr_r_r_acc : 3303Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">; 3304 3305def int_hexagon_S2_lsr_r_r_and : 3306Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">; 3307 3308def int_hexagon_S2_lsr_r_r_nac : 3309Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">; 3310 3311def int_hexagon_S2_lsr_r_r_or : 3312Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">; 3313 3314def int_hexagon_S2_lsr_r_vh : 3315Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">; 3316 3317def int_hexagon_S2_lsr_r_vw : 3318Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">; 3319 3320def int_hexagon_S2_packhl : 3321Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">; 3322 3323def int_hexagon_S2_parityp : 3324Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">; 3325 3326def int_hexagon_S2_setbit_i : 3327Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3328 3329def int_hexagon_S2_setbit_r : 3330Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">; 3331 3332def int_hexagon_S2_shuffeb : 3333Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">; 3334 3335def int_hexagon_S2_shuffeh : 3336Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">; 3337 3338def int_hexagon_S2_shuffob : 3339Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">; 3340 3341def int_hexagon_S2_shuffoh : 3342Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">; 3343 3344def int_hexagon_S2_svsathb : 3345Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">; 3346 3347def int_hexagon_S2_svsathub : 3348Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">; 3349 3350def int_hexagon_S2_tableidxb_goodsyntax : 3351Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3352 3353def int_hexagon_S2_tableidxd_goodsyntax : 3354Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3355 3356def int_hexagon_S2_tableidxh_goodsyntax : 3357Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3358 3359def int_hexagon_S2_tableidxw_goodsyntax : 3360Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3361 3362def int_hexagon_S2_togglebit_i : 3363Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3364 3365def int_hexagon_S2_togglebit_r : 3366Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">; 3367 3368def int_hexagon_S2_tstbit_i : 3369Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3370 3371def int_hexagon_S2_tstbit_r : 3372Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">; 3373 3374def int_hexagon_S2_valignib : 3375Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3376 3377def int_hexagon_S2_valignrb : 3378Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">; 3379 3380def int_hexagon_S2_vcnegh : 3381Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">; 3382 3383def int_hexagon_S2_vcrotate : 3384Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">; 3385 3386def int_hexagon_S2_vrcnegh : 3387Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">; 3388 3389def int_hexagon_S2_vrndpackwh : 3390Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">; 3391 3392def int_hexagon_S2_vrndpackwhs : 3393Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">; 3394 3395def int_hexagon_S2_vsathb : 3396Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">; 3397 3398def int_hexagon_S2_vsathb_nopack : 3399Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">; 3400 3401def int_hexagon_S2_vsathub : 3402Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">; 3403 3404def int_hexagon_S2_vsathub_nopack : 3405Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">; 3406 3407def int_hexagon_S2_vsatwh : 3408Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">; 3409 3410def int_hexagon_S2_vsatwh_nopack : 3411Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">; 3412 3413def int_hexagon_S2_vsatwuh : 3414Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">; 3415 3416def int_hexagon_S2_vsatwuh_nopack : 3417Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">; 3418 3419def int_hexagon_S2_vsplatrb : 3420Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">; 3421 3422def int_hexagon_S2_vsplatrh : 3423Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">; 3424 3425def int_hexagon_S2_vspliceib : 3426Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3427 3428def int_hexagon_S2_vsplicerb : 3429Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">; 3430 3431def int_hexagon_S2_vsxtbh : 3432Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">; 3433 3434def int_hexagon_S2_vsxthw : 3435Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">; 3436 3437def int_hexagon_S2_vtrunehb : 3438Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">; 3439 3440def int_hexagon_S2_vtrunewh : 3441Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">; 3442 3443def int_hexagon_S2_vtrunohb : 3444Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">; 3445 3446def int_hexagon_S2_vtrunowh : 3447Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">; 3448 3449def int_hexagon_S2_vzxtbh : 3450Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">; 3451 3452def int_hexagon_S2_vzxthw : 3453Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">; 3454 3455def int_hexagon_S4_addaddi : 3456Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3457 3458def int_hexagon_S4_addi_asl_ri : 3459Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3460 3461def int_hexagon_S4_addi_lsr_ri : 3462Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3463 3464def int_hexagon_S4_andi_asl_ri : 3465Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3466 3467def int_hexagon_S4_andi_lsr_ri : 3468Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3469 3470def int_hexagon_S4_clbaddi : 3471Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3472 3473def int_hexagon_S4_clbpaddi : 3474Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3475 3476def int_hexagon_S4_clbpnorm : 3477Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">; 3478 3479def int_hexagon_S4_extract : 3480Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3481 3482def int_hexagon_S4_extract_rp : 3483Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">; 3484 3485def int_hexagon_S4_extractp : 3486Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3487 3488def int_hexagon_S4_extractp_rp : 3489Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">; 3490 3491def int_hexagon_S4_lsli : 3492Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 3493 3494def int_hexagon_S4_ntstbit_i : 3495Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3496 3497def int_hexagon_S4_ntstbit_r : 3498Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">; 3499 3500def int_hexagon_S4_or_andi : 3501Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3502 3503def int_hexagon_S4_or_andix : 3504Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3505 3506def int_hexagon_S4_or_ori : 3507Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3508 3509def int_hexagon_S4_ori_asl_ri : 3510Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3511 3512def int_hexagon_S4_ori_lsr_ri : 3513Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3514 3515def int_hexagon_S4_parity : 3516Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">; 3517 3518def int_hexagon_S4_subaddi : 3519Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3520 3521def int_hexagon_S4_subi_asl_ri : 3522Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3523 3524def int_hexagon_S4_subi_lsr_ri : 3525Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3526 3527def int_hexagon_S4_vrcrotate : 3528Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3529 3530def int_hexagon_S4_vrcrotate_acc : 3531Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 3532 3533def int_hexagon_S4_vxaddsubh : 3534Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">; 3535 3536def int_hexagon_S4_vxaddsubhr : 3537Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">; 3538 3539def int_hexagon_S4_vxaddsubw : 3540Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">; 3541 3542def int_hexagon_S4_vxsubaddh : 3543Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">; 3544 3545def int_hexagon_S4_vxsubaddhr : 3546Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">; 3547 3548def int_hexagon_S4_vxsubaddw : 3549Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">; 3550 3551def int_hexagon_S5_asrhub_rnd_sat_goodsyntax : 3552Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3553 3554def int_hexagon_S5_asrhub_sat : 3555Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3556 3557def int_hexagon_S5_popcountp : 3558Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">; 3559 3560def int_hexagon_S5_vasrhrnd_goodsyntax : 3561Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3562 3563def int_hexagon_Y2_dccleana : 3564Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleana", []>; 3565 3566def int_hexagon_Y2_dccleaninva : 3567Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleaninva", []>; 3568 3569def int_hexagon_Y2_dcfetch : 3570Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcfetch", []>; 3571 3572def int_hexagon_Y2_dcinva : 3573Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcinva", []>; 3574 3575def int_hexagon_Y2_dczeroa : 3576Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dczeroa", []>; 3577 3578def int_hexagon_Y4_l2fetch : 3579Hexagon__ptri32_Intrinsic<"HEXAGON_Y4_l2fetch", []>; 3580 3581def int_hexagon_Y5_l2fetch : 3582Hexagon__ptri64_Intrinsic<"HEXAGON_Y5_l2fetch", []>; 3583 3584// V60 Scalar Instructions. 3585 3586def int_hexagon_S6_rol_i_p : 3587Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3588 3589def int_hexagon_S6_rol_i_p_acc : 3590Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3591 3592def int_hexagon_S6_rol_i_p_and : 3593Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3594 3595def int_hexagon_S6_rol_i_p_nac : 3596Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3597 3598def int_hexagon_S6_rol_i_p_or : 3599Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3600 3601def int_hexagon_S6_rol_i_p_xacc : 3602Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3603 3604def int_hexagon_S6_rol_i_r : 3605Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3606 3607def int_hexagon_S6_rol_i_r_acc : 3608Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3609 3610def int_hexagon_S6_rol_i_r_and : 3611Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3612 3613def int_hexagon_S6_rol_i_r_nac : 3614Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3615 3616def int_hexagon_S6_rol_i_r_or : 3617Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3618 3619def int_hexagon_S6_rol_i_r_xacc : 3620Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3621 3622// V62 Scalar Instructions. 3623 3624def int_hexagon_M6_vabsdiffb : 3625Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffb">; 3626 3627def int_hexagon_M6_vabsdiffub : 3628Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffub">; 3629 3630def int_hexagon_S6_vsplatrbp : 3631Hexagon_i64_i32_Intrinsic<"HEXAGON_S6_vsplatrbp">; 3632 3633def int_hexagon_S6_vtrunehb_ppp : 3634Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">; 3635 3636def int_hexagon_S6_vtrunohb_ppp : 3637Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">; 3638 3639// V65 Scalar Instructions. 3640 3641def int_hexagon_A6_vcmpbeq_notany : 3642Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">; 3643 3644// V66 Scalar Instructions. 3645 3646def int_hexagon_F2_dfadd : 3647Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd", [IntrNoMem, Throws]>; 3648 3649def int_hexagon_F2_dfsub : 3650Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub", [IntrNoMem, Throws]>; 3651 3652def int_hexagon_M2_mnaci : 3653Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">; 3654 3655def int_hexagon_S2_mask : 3656Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>; 3657 3658// V67 Scalar Instructions. 3659 3660def int_hexagon_A7_clip : 3661Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A7_clip", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3662 3663def int_hexagon_A7_croundd_ri : 3664Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3665 3666def int_hexagon_A7_croundd_rr : 3667Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_rr">; 3668 3669def int_hexagon_A7_vclip : 3670Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_vclip", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3671 3672def int_hexagon_F2_dfmax : 3673Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmax", [IntrNoMem, Throws]>; 3674 3675def int_hexagon_F2_dfmin : 3676Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmin", [IntrNoMem, Throws]>; 3677 3678def int_hexagon_F2_dfmpyfix : 3679Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyfix", [IntrNoMem, Throws]>; 3680 3681def int_hexagon_F2_dfmpyhh : 3682Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpyhh", [IntrNoMem, Throws]>; 3683 3684def int_hexagon_F2_dfmpylh : 3685Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpylh", [IntrNoMem, Throws]>; 3686 3687def int_hexagon_F2_dfmpyll : 3688Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyll", [IntrNoMem, Throws]>; 3689 3690def int_hexagon_M7_dcmpyiw : 3691Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw">; 3692 3693def int_hexagon_M7_dcmpyiw_acc : 3694Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw_acc">; 3695 3696def int_hexagon_M7_dcmpyiwc : 3697Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc">; 3698 3699def int_hexagon_M7_dcmpyiwc_acc : 3700Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc_acc">; 3701 3702def int_hexagon_M7_dcmpyrw : 3703Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw">; 3704 3705def int_hexagon_M7_dcmpyrw_acc : 3706Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw_acc">; 3707 3708def int_hexagon_M7_dcmpyrwc : 3709Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc">; 3710 3711def int_hexagon_M7_dcmpyrwc_acc : 3712Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc_acc">; 3713 3714def int_hexagon_M7_vdmpy : 3715Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_vdmpy">; 3716 3717def int_hexagon_M7_vdmpy_acc : 3718Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_vdmpy_acc">; 3719 3720def int_hexagon_M7_wcmpyiw : 3721Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw">; 3722 3723def int_hexagon_M7_wcmpyiw_rnd : 3724Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw_rnd">; 3725 3726def int_hexagon_M7_wcmpyiwc : 3727Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc">; 3728 3729def int_hexagon_M7_wcmpyiwc_rnd : 3730Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc_rnd">; 3731 3732def int_hexagon_M7_wcmpyrw : 3733Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw">; 3734 3735def int_hexagon_M7_wcmpyrw_rnd : 3736Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw_rnd">; 3737 3738def int_hexagon_M7_wcmpyrwc : 3739Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc">; 3740 3741def int_hexagon_M7_wcmpyrwc_rnd : 3742Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc_rnd">; 3743 3744// V68 Scalar Instructions. 3745 3746def int_hexagon_Y6_dmlink : 3747Hexagon__ptrptr_Intrinsic<"HEXAGON_Y6_dmlink", [IntrArgMemOnly, IntrHasSideEffects]>; 3748 3749def int_hexagon_Y6_dmpause : 3750Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmpause", [IntrArgMemOnly, IntrHasSideEffects]>; 3751 3752def int_hexagon_Y6_dmpoll : 3753Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmpoll", [IntrArgMemOnly, IntrHasSideEffects]>; 3754 3755def int_hexagon_Y6_dmresume : 3756Hexagon__ptr_Intrinsic<"HEXAGON_Y6_dmresume", [IntrArgMemOnly, IntrHasSideEffects]>; 3757 3758def int_hexagon_Y6_dmstart : 3759Hexagon__ptr_Intrinsic<"HEXAGON_Y6_dmstart", [IntrArgMemOnly, IntrHasSideEffects]>; 3760 3761def int_hexagon_Y6_dmwait : 3762Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmwait", [IntrArgMemOnly, IntrHasSideEffects]>; 3763 3764// V60 HVX Instructions. 3765 3766def int_hexagon_V6_extractw : 3767Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">; 3768 3769def int_hexagon_V6_extractw_128B : 3770Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">; 3771 3772def int_hexagon_V6_hi : 3773Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">; 3774 3775def int_hexagon_V6_hi_128B : 3776Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">; 3777 3778def int_hexagon_V6_lo : 3779Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">; 3780 3781def int_hexagon_V6_lo_128B : 3782Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">; 3783 3784def int_hexagon_V6_lvsplatw : 3785Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">; 3786 3787def int_hexagon_V6_lvsplatw_128B : 3788Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">; 3789 3790def int_hexagon_V6_pred_and : 3791Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_and">; 3792 3793def int_hexagon_V6_pred_and_128B : 3794Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_and_128B">; 3795 3796def int_hexagon_V6_pred_and_n : 3797Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_and_n">; 3798 3799def int_hexagon_V6_pred_and_n_128B : 3800Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_and_n_128B">; 3801 3802def int_hexagon_V6_pred_not : 3803Hexagon_v64i1_v64i1_Intrinsic<"HEXAGON_V6_pred_not">; 3804 3805def int_hexagon_V6_pred_not_128B : 3806Hexagon_v128i1_v128i1_Intrinsic<"HEXAGON_V6_pred_not_128B">; 3807 3808def int_hexagon_V6_pred_or : 3809Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_or">; 3810 3811def int_hexagon_V6_pred_or_128B : 3812Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_or_128B">; 3813 3814def int_hexagon_V6_pred_or_n : 3815Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_or_n">; 3816 3817def int_hexagon_V6_pred_or_n_128B : 3818Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_or_n_128B">; 3819 3820def int_hexagon_V6_pred_scalar2 : 3821Hexagon_v64i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2">; 3822 3823def int_hexagon_V6_pred_scalar2_128B : 3824Hexagon_v128i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">; 3825 3826def int_hexagon_V6_pred_xor : 3827Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_xor">; 3828 3829def int_hexagon_V6_pred_xor_128B : 3830Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_xor_128B">; 3831 3832def int_hexagon_V6_vS32b_nqpred_ai : 3833Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai", [IntrWriteMem]>; 3834 3835def int_hexagon_V6_vS32b_nqpred_ai_128B : 3836Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B", [IntrWriteMem]>; 3837 3838def int_hexagon_V6_vS32b_nt_nqpred_ai : 3839Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai", [IntrWriteMem]>; 3840 3841def int_hexagon_V6_vS32b_nt_nqpred_ai_128B : 3842Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B", [IntrWriteMem]>; 3843 3844def int_hexagon_V6_vS32b_nt_qpred_ai : 3845Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai", [IntrWriteMem]>; 3846 3847def int_hexagon_V6_vS32b_nt_qpred_ai_128B : 3848Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B", [IntrWriteMem]>; 3849 3850def int_hexagon_V6_vS32b_qpred_ai : 3851Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai", [IntrWriteMem]>; 3852 3853def int_hexagon_V6_vS32b_qpred_ai_128B : 3854Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B", [IntrWriteMem]>; 3855 3856def int_hexagon_V6_vabsdiffh : 3857Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">; 3858 3859def int_hexagon_V6_vabsdiffh_128B : 3860Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">; 3861 3862def int_hexagon_V6_vabsdiffub : 3863Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffub">; 3864 3865def int_hexagon_V6_vabsdiffub_128B : 3866Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">; 3867 3868def int_hexagon_V6_vabsdiffuh : 3869Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffuh">; 3870 3871def int_hexagon_V6_vabsdiffuh_128B : 3872Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">; 3873 3874def int_hexagon_V6_vabsdiffw : 3875Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffw">; 3876 3877def int_hexagon_V6_vabsdiffw_128B : 3878Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">; 3879 3880def int_hexagon_V6_vabsh : 3881Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">; 3882 3883def int_hexagon_V6_vabsh_128B : 3884Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">; 3885 3886def int_hexagon_V6_vabsh_sat : 3887Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">; 3888 3889def int_hexagon_V6_vabsh_sat_128B : 3890Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">; 3891 3892def int_hexagon_V6_vabsw : 3893Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">; 3894 3895def int_hexagon_V6_vabsw_128B : 3896Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">; 3897 3898def int_hexagon_V6_vabsw_sat : 3899Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">; 3900 3901def int_hexagon_V6_vabsw_sat_128B : 3902Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">; 3903 3904def int_hexagon_V6_vaddb : 3905Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">; 3906 3907def int_hexagon_V6_vaddb_128B : 3908Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">; 3909 3910def int_hexagon_V6_vaddb_dv : 3911Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">; 3912 3913def int_hexagon_V6_vaddb_dv_128B : 3914Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">; 3915 3916def int_hexagon_V6_vaddbnq : 3917Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbnq">; 3918 3919def int_hexagon_V6_vaddbnq_128B : 3920Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbnq_128B">; 3921 3922def int_hexagon_V6_vaddbq : 3923Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbq">; 3924 3925def int_hexagon_V6_vaddbq_128B : 3926Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbq_128B">; 3927 3928def int_hexagon_V6_vaddh : 3929Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">; 3930 3931def int_hexagon_V6_vaddh_128B : 3932Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">; 3933 3934def int_hexagon_V6_vaddh_dv : 3935Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">; 3936 3937def int_hexagon_V6_vaddh_dv_128B : 3938Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">; 3939 3940def int_hexagon_V6_vaddhnq : 3941Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhnq">; 3942 3943def int_hexagon_V6_vaddhnq_128B : 3944Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhnq_128B">; 3945 3946def int_hexagon_V6_vaddhq : 3947Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhq">; 3948 3949def int_hexagon_V6_vaddhq_128B : 3950Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhq_128B">; 3951 3952def int_hexagon_V6_vaddhsat : 3953Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">; 3954 3955def int_hexagon_V6_vaddhsat_128B : 3956Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">; 3957 3958def int_hexagon_V6_vaddhsat_dv : 3959Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">; 3960 3961def int_hexagon_V6_vaddhsat_dv_128B : 3962Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">; 3963 3964def int_hexagon_V6_vaddhw : 3965Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">; 3966 3967def int_hexagon_V6_vaddhw_128B : 3968Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">; 3969 3970def int_hexagon_V6_vaddubh : 3971Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">; 3972 3973def int_hexagon_V6_vaddubh_128B : 3974Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">; 3975 3976def int_hexagon_V6_vaddubsat : 3977Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">; 3978 3979def int_hexagon_V6_vaddubsat_128B : 3980Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">; 3981 3982def int_hexagon_V6_vaddubsat_dv : 3983Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">; 3984 3985def int_hexagon_V6_vaddubsat_dv_128B : 3986Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">; 3987 3988def int_hexagon_V6_vadduhsat : 3989Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">; 3990 3991def int_hexagon_V6_vadduhsat_128B : 3992Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">; 3993 3994def int_hexagon_V6_vadduhsat_dv : 3995Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">; 3996 3997def int_hexagon_V6_vadduhsat_dv_128B : 3998Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">; 3999 4000def int_hexagon_V6_vadduhw : 4001Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">; 4002 4003def int_hexagon_V6_vadduhw_128B : 4004Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">; 4005 4006def int_hexagon_V6_vaddw : 4007Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">; 4008 4009def int_hexagon_V6_vaddw_128B : 4010Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">; 4011 4012def int_hexagon_V6_vaddw_dv : 4013Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">; 4014 4015def int_hexagon_V6_vaddw_dv_128B : 4016Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">; 4017 4018def int_hexagon_V6_vaddwnq : 4019Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwnq">; 4020 4021def int_hexagon_V6_vaddwnq_128B : 4022Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwnq_128B">; 4023 4024def int_hexagon_V6_vaddwq : 4025Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwq">; 4026 4027def int_hexagon_V6_vaddwq_128B : 4028Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwq_128B">; 4029 4030def int_hexagon_V6_vaddwsat : 4031Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">; 4032 4033def int_hexagon_V6_vaddwsat_128B : 4034Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">; 4035 4036def int_hexagon_V6_vaddwsat_dv : 4037Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">; 4038 4039def int_hexagon_V6_vaddwsat_dv_128B : 4040Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">; 4041 4042def int_hexagon_V6_valignb : 4043Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">; 4044 4045def int_hexagon_V6_valignb_128B : 4046Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">; 4047 4048def int_hexagon_V6_valignbi : 4049Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4050 4051def int_hexagon_V6_valignbi_128B : 4052Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4053 4054def int_hexagon_V6_vand : 4055Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">; 4056 4057def int_hexagon_V6_vand_128B : 4058Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">; 4059 4060def int_hexagon_V6_vandqrt : 4061Hexagon_v16i32_v64i1i32_Intrinsic<"HEXAGON_V6_vandqrt">; 4062 4063def int_hexagon_V6_vandqrt_128B : 4064Hexagon_v32i32_v128i1i32_Intrinsic<"HEXAGON_V6_vandqrt_128B">; 4065 4066def int_hexagon_V6_vandqrt_acc : 4067Hexagon_v16i32_v16i32v64i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc">; 4068 4069def int_hexagon_V6_vandqrt_acc_128B : 4070Hexagon_v32i32_v32i32v128i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">; 4071 4072def int_hexagon_V6_vandvrt : 4073Hexagon_v64i1_v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt">; 4074 4075def int_hexagon_V6_vandvrt_128B : 4076Hexagon_v128i1_v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_128B">; 4077 4078def int_hexagon_V6_vandvrt_acc : 4079Hexagon_v64i1_v64i1v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc">; 4080 4081def int_hexagon_V6_vandvrt_acc_128B : 4082Hexagon_v128i1_v128i1v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">; 4083 4084def int_hexagon_V6_vaslh : 4085Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">; 4086 4087def int_hexagon_V6_vaslh_128B : 4088Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">; 4089 4090def int_hexagon_V6_vaslhv : 4091Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">; 4092 4093def int_hexagon_V6_vaslhv_128B : 4094Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">; 4095 4096def int_hexagon_V6_vaslw : 4097Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">; 4098 4099def int_hexagon_V6_vaslw_128B : 4100Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">; 4101 4102def int_hexagon_V6_vaslw_acc : 4103Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">; 4104 4105def int_hexagon_V6_vaslw_acc_128B : 4106Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">; 4107 4108def int_hexagon_V6_vaslwv : 4109Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">; 4110 4111def int_hexagon_V6_vaslwv_128B : 4112Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">; 4113 4114def int_hexagon_V6_vasrh : 4115Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">; 4116 4117def int_hexagon_V6_vasrh_128B : 4118Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">; 4119 4120def int_hexagon_V6_vasrhbrndsat : 4121Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">; 4122 4123def int_hexagon_V6_vasrhbrndsat_128B : 4124Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">; 4125 4126def int_hexagon_V6_vasrhubrndsat : 4127Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">; 4128 4129def int_hexagon_V6_vasrhubrndsat_128B : 4130Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">; 4131 4132def int_hexagon_V6_vasrhubsat : 4133Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">; 4134 4135def int_hexagon_V6_vasrhubsat_128B : 4136Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">; 4137 4138def int_hexagon_V6_vasrhv : 4139Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">; 4140 4141def int_hexagon_V6_vasrhv_128B : 4142Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">; 4143 4144def int_hexagon_V6_vasrw : 4145Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">; 4146 4147def int_hexagon_V6_vasrw_128B : 4148Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">; 4149 4150def int_hexagon_V6_vasrw_acc : 4151Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">; 4152 4153def int_hexagon_V6_vasrw_acc_128B : 4154Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">; 4155 4156def int_hexagon_V6_vasrwh : 4157Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">; 4158 4159def int_hexagon_V6_vasrwh_128B : 4160Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">; 4161 4162def int_hexagon_V6_vasrwhrndsat : 4163Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">; 4164 4165def int_hexagon_V6_vasrwhrndsat_128B : 4166Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">; 4167 4168def int_hexagon_V6_vasrwhsat : 4169Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">; 4170 4171def int_hexagon_V6_vasrwhsat_128B : 4172Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">; 4173 4174def int_hexagon_V6_vasrwuhsat : 4175Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">; 4176 4177def int_hexagon_V6_vasrwuhsat_128B : 4178Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">; 4179 4180def int_hexagon_V6_vasrwv : 4181Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">; 4182 4183def int_hexagon_V6_vasrwv_128B : 4184Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">; 4185 4186def int_hexagon_V6_vassign : 4187Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">; 4188 4189def int_hexagon_V6_vassign_128B : 4190Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">; 4191 4192def int_hexagon_V6_vassignp : 4193Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">; 4194 4195def int_hexagon_V6_vassignp_128B : 4196Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">; 4197 4198def int_hexagon_V6_vavgh : 4199Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">; 4200 4201def int_hexagon_V6_vavgh_128B : 4202Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">; 4203 4204def int_hexagon_V6_vavghrnd : 4205Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">; 4206 4207def int_hexagon_V6_vavghrnd_128B : 4208Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">; 4209 4210def int_hexagon_V6_vavgub : 4211Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">; 4212 4213def int_hexagon_V6_vavgub_128B : 4214Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">; 4215 4216def int_hexagon_V6_vavgubrnd : 4217Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">; 4218 4219def int_hexagon_V6_vavgubrnd_128B : 4220Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">; 4221 4222def int_hexagon_V6_vavguh : 4223Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">; 4224 4225def int_hexagon_V6_vavguh_128B : 4226Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">; 4227 4228def int_hexagon_V6_vavguhrnd : 4229Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">; 4230 4231def int_hexagon_V6_vavguhrnd_128B : 4232Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">; 4233 4234def int_hexagon_V6_vavgw : 4235Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">; 4236 4237def int_hexagon_V6_vavgw_128B : 4238Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">; 4239 4240def int_hexagon_V6_vavgwrnd : 4241Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">; 4242 4243def int_hexagon_V6_vavgwrnd_128B : 4244Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">; 4245 4246def int_hexagon_V6_vcl0h : 4247Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">; 4248 4249def int_hexagon_V6_vcl0h_128B : 4250Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">; 4251 4252def int_hexagon_V6_vcl0w : 4253Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">; 4254 4255def int_hexagon_V6_vcl0w_128B : 4256Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">; 4257 4258def int_hexagon_V6_vcombine : 4259Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">; 4260 4261def int_hexagon_V6_vcombine_128B : 4262Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">; 4263 4264def int_hexagon_V6_vd0 : 4265Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">; 4266 4267def int_hexagon_V6_vd0_128B : 4268Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">; 4269 4270def int_hexagon_V6_vdealb : 4271Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">; 4272 4273def int_hexagon_V6_vdealb_128B : 4274Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">; 4275 4276def int_hexagon_V6_vdealb4w : 4277Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">; 4278 4279def int_hexagon_V6_vdealb4w_128B : 4280Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">; 4281 4282def int_hexagon_V6_vdealh : 4283Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">; 4284 4285def int_hexagon_V6_vdealh_128B : 4286Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">; 4287 4288def int_hexagon_V6_vdealvdd : 4289Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">; 4290 4291def int_hexagon_V6_vdealvdd_128B : 4292Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">; 4293 4294def int_hexagon_V6_vdelta : 4295Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">; 4296 4297def int_hexagon_V6_vdelta_128B : 4298Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">; 4299 4300def int_hexagon_V6_vdmpybus : 4301Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">; 4302 4303def int_hexagon_V6_vdmpybus_128B : 4304Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_128B">; 4305 4306def int_hexagon_V6_vdmpybus_acc : 4307Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc">; 4308 4309def int_hexagon_V6_vdmpybus_acc_128B : 4310Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">; 4311 4312def int_hexagon_V6_vdmpybus_dv : 4313Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv">; 4314 4315def int_hexagon_V6_vdmpybus_dv_128B : 4316Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">; 4317 4318def int_hexagon_V6_vdmpybus_dv_acc : 4319Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">; 4320 4321def int_hexagon_V6_vdmpybus_dv_acc_128B : 4322Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">; 4323 4324def int_hexagon_V6_vdmpyhb : 4325Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb">; 4326 4327def int_hexagon_V6_vdmpyhb_128B : 4328Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">; 4329 4330def int_hexagon_V6_vdmpyhb_acc : 4331Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">; 4332 4333def int_hexagon_V6_vdmpyhb_acc_128B : 4334Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">; 4335 4336def int_hexagon_V6_vdmpyhb_dv : 4337Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">; 4338 4339def int_hexagon_V6_vdmpyhb_dv_128B : 4340Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">; 4341 4342def int_hexagon_V6_vdmpyhb_dv_acc : 4343Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">; 4344 4345def int_hexagon_V6_vdmpyhb_dv_acc_128B : 4346Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">; 4347 4348def int_hexagon_V6_vdmpyhisat : 4349Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">; 4350 4351def int_hexagon_V6_vdmpyhisat_128B : 4352Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">; 4353 4354def int_hexagon_V6_vdmpyhisat_acc : 4355Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">; 4356 4357def int_hexagon_V6_vdmpyhisat_acc_128B : 4358Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">; 4359 4360def int_hexagon_V6_vdmpyhsat : 4361Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">; 4362 4363def int_hexagon_V6_vdmpyhsat_128B : 4364Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">; 4365 4366def int_hexagon_V6_vdmpyhsat_acc : 4367Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">; 4368 4369def int_hexagon_V6_vdmpyhsat_acc_128B : 4370Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">; 4371 4372def int_hexagon_V6_vdmpyhsuisat : 4373Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">; 4374 4375def int_hexagon_V6_vdmpyhsuisat_128B : 4376Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">; 4377 4378def int_hexagon_V6_vdmpyhsuisat_acc : 4379Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">; 4380 4381def int_hexagon_V6_vdmpyhsuisat_acc_128B : 4382Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">; 4383 4384def int_hexagon_V6_vdmpyhsusat : 4385Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">; 4386 4387def int_hexagon_V6_vdmpyhsusat_128B : 4388Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">; 4389 4390def int_hexagon_V6_vdmpyhsusat_acc : 4391Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">; 4392 4393def int_hexagon_V6_vdmpyhsusat_acc_128B : 4394Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">; 4395 4396def int_hexagon_V6_vdmpyhvsat : 4397Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">; 4398 4399def int_hexagon_V6_vdmpyhvsat_128B : 4400Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">; 4401 4402def int_hexagon_V6_vdmpyhvsat_acc : 4403Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">; 4404 4405def int_hexagon_V6_vdmpyhvsat_acc_128B : 4406Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">; 4407 4408def int_hexagon_V6_vdsaduh : 4409Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">; 4410 4411def int_hexagon_V6_vdsaduh_128B : 4412Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">; 4413 4414def int_hexagon_V6_vdsaduh_acc : 4415Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">; 4416 4417def int_hexagon_V6_vdsaduh_acc_128B : 4418Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">; 4419 4420def int_hexagon_V6_veqb : 4421Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb">; 4422 4423def int_hexagon_V6_veqb_128B : 4424Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_128B">; 4425 4426def int_hexagon_V6_veqb_and : 4427Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_and">; 4428 4429def int_hexagon_V6_veqb_and_128B : 4430Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_and_128B">; 4431 4432def int_hexagon_V6_veqb_or : 4433Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_or">; 4434 4435def int_hexagon_V6_veqb_or_128B : 4436Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_or_128B">; 4437 4438def int_hexagon_V6_veqb_xor : 4439Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_xor">; 4440 4441def int_hexagon_V6_veqb_xor_128B : 4442Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_xor_128B">; 4443 4444def int_hexagon_V6_veqh : 4445Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh">; 4446 4447def int_hexagon_V6_veqh_128B : 4448Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_128B">; 4449 4450def int_hexagon_V6_veqh_and : 4451Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_and">; 4452 4453def int_hexagon_V6_veqh_and_128B : 4454Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_and_128B">; 4455 4456def int_hexagon_V6_veqh_or : 4457Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_or">; 4458 4459def int_hexagon_V6_veqh_or_128B : 4460Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_or_128B">; 4461 4462def int_hexagon_V6_veqh_xor : 4463Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_xor">; 4464 4465def int_hexagon_V6_veqh_xor_128B : 4466Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_xor_128B">; 4467 4468def int_hexagon_V6_veqw : 4469Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw">; 4470 4471def int_hexagon_V6_veqw_128B : 4472Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_128B">; 4473 4474def int_hexagon_V6_veqw_and : 4475Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_and">; 4476 4477def int_hexagon_V6_veqw_and_128B : 4478Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_and_128B">; 4479 4480def int_hexagon_V6_veqw_or : 4481Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_or">; 4482 4483def int_hexagon_V6_veqw_or_128B : 4484Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_or_128B">; 4485 4486def int_hexagon_V6_veqw_xor : 4487Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_xor">; 4488 4489def int_hexagon_V6_veqw_xor_128B : 4490Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_xor_128B">; 4491 4492def int_hexagon_V6_vgtb : 4493Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb">; 4494 4495def int_hexagon_V6_vgtb_128B : 4496Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_128B">; 4497 4498def int_hexagon_V6_vgtb_and : 4499Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_and">; 4500 4501def int_hexagon_V6_vgtb_and_128B : 4502Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_and_128B">; 4503 4504def int_hexagon_V6_vgtb_or : 4505Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_or">; 4506 4507def int_hexagon_V6_vgtb_or_128B : 4508Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_or_128B">; 4509 4510def int_hexagon_V6_vgtb_xor : 4511Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_xor">; 4512 4513def int_hexagon_V6_vgtb_xor_128B : 4514Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">; 4515 4516def int_hexagon_V6_vgth : 4517Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth">; 4518 4519def int_hexagon_V6_vgth_128B : 4520Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_128B">; 4521 4522def int_hexagon_V6_vgth_and : 4523Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_and">; 4524 4525def int_hexagon_V6_vgth_and_128B : 4526Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_and_128B">; 4527 4528def int_hexagon_V6_vgth_or : 4529Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_or">; 4530 4531def int_hexagon_V6_vgth_or_128B : 4532Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_or_128B">; 4533 4534def int_hexagon_V6_vgth_xor : 4535Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_xor">; 4536 4537def int_hexagon_V6_vgth_xor_128B : 4538Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_xor_128B">; 4539 4540def int_hexagon_V6_vgtub : 4541Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub">; 4542 4543def int_hexagon_V6_vgtub_128B : 4544Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_128B">; 4545 4546def int_hexagon_V6_vgtub_and : 4547Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_and">; 4548 4549def int_hexagon_V6_vgtub_and_128B : 4550Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_and_128B">; 4551 4552def int_hexagon_V6_vgtub_or : 4553Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_or">; 4554 4555def int_hexagon_V6_vgtub_or_128B : 4556Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_or_128B">; 4557 4558def int_hexagon_V6_vgtub_xor : 4559Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_xor">; 4560 4561def int_hexagon_V6_vgtub_xor_128B : 4562Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">; 4563 4564def int_hexagon_V6_vgtuh : 4565Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh">; 4566 4567def int_hexagon_V6_vgtuh_128B : 4568Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_128B">; 4569 4570def int_hexagon_V6_vgtuh_and : 4571Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_and">; 4572 4573def int_hexagon_V6_vgtuh_and_128B : 4574Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">; 4575 4576def int_hexagon_V6_vgtuh_or : 4577Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_or">; 4578 4579def int_hexagon_V6_vgtuh_or_128B : 4580Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">; 4581 4582def int_hexagon_V6_vgtuh_xor : 4583Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_xor">; 4584 4585def int_hexagon_V6_vgtuh_xor_128B : 4586Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">; 4587 4588def int_hexagon_V6_vgtuw : 4589Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw">; 4590 4591def int_hexagon_V6_vgtuw_128B : 4592Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_128B">; 4593 4594def int_hexagon_V6_vgtuw_and : 4595Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_and">; 4596 4597def int_hexagon_V6_vgtuw_and_128B : 4598Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">; 4599 4600def int_hexagon_V6_vgtuw_or : 4601Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_or">; 4602 4603def int_hexagon_V6_vgtuw_or_128B : 4604Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">; 4605 4606def int_hexagon_V6_vgtuw_xor : 4607Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_xor">; 4608 4609def int_hexagon_V6_vgtuw_xor_128B : 4610Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">; 4611 4612def int_hexagon_V6_vgtw : 4613Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw">; 4614 4615def int_hexagon_V6_vgtw_128B : 4616Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_128B">; 4617 4618def int_hexagon_V6_vgtw_and : 4619Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_and">; 4620 4621def int_hexagon_V6_vgtw_and_128B : 4622Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_and_128B">; 4623 4624def int_hexagon_V6_vgtw_or : 4625Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_or">; 4626 4627def int_hexagon_V6_vgtw_or_128B : 4628Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_or_128B">; 4629 4630def int_hexagon_V6_vgtw_xor : 4631Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_xor">; 4632 4633def int_hexagon_V6_vgtw_xor_128B : 4634Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">; 4635 4636def int_hexagon_V6_vinsertwr : 4637Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">; 4638 4639def int_hexagon_V6_vinsertwr_128B : 4640Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">; 4641 4642def int_hexagon_V6_vlalignb : 4643Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">; 4644 4645def int_hexagon_V6_vlalignb_128B : 4646Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">; 4647 4648def int_hexagon_V6_vlalignbi : 4649Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4650 4651def int_hexagon_V6_vlalignbi_128B : 4652Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4653 4654def int_hexagon_V6_vlsrh : 4655Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">; 4656 4657def int_hexagon_V6_vlsrh_128B : 4658Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">; 4659 4660def int_hexagon_V6_vlsrhv : 4661Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">; 4662 4663def int_hexagon_V6_vlsrhv_128B : 4664Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">; 4665 4666def int_hexagon_V6_vlsrw : 4667Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">; 4668 4669def int_hexagon_V6_vlsrw_128B : 4670Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">; 4671 4672def int_hexagon_V6_vlsrwv : 4673Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">; 4674 4675def int_hexagon_V6_vlsrwv_128B : 4676Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">; 4677 4678def int_hexagon_V6_vlutvvb : 4679Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">; 4680 4681def int_hexagon_V6_vlutvvb_128B : 4682Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">; 4683 4684def int_hexagon_V6_vlutvvb_oracc : 4685Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">; 4686 4687def int_hexagon_V6_vlutvvb_oracc_128B : 4688Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">; 4689 4690def int_hexagon_V6_vlutvwh : 4691Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">; 4692 4693def int_hexagon_V6_vlutvwh_128B : 4694Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">; 4695 4696def int_hexagon_V6_vlutvwh_oracc : 4697Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">; 4698 4699def int_hexagon_V6_vlutvwh_oracc_128B : 4700Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">; 4701 4702def int_hexagon_V6_vmaxh : 4703Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">; 4704 4705def int_hexagon_V6_vmaxh_128B : 4706Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">; 4707 4708def int_hexagon_V6_vmaxub : 4709Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">; 4710 4711def int_hexagon_V6_vmaxub_128B : 4712Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">; 4713 4714def int_hexagon_V6_vmaxuh : 4715Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">; 4716 4717def int_hexagon_V6_vmaxuh_128B : 4718Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">; 4719 4720def int_hexagon_V6_vmaxw : 4721Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">; 4722 4723def int_hexagon_V6_vmaxw_128B : 4724Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">; 4725 4726def int_hexagon_V6_vminh : 4727Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">; 4728 4729def int_hexagon_V6_vminh_128B : 4730Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">; 4731 4732def int_hexagon_V6_vminub : 4733Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">; 4734 4735def int_hexagon_V6_vminub_128B : 4736Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">; 4737 4738def int_hexagon_V6_vminuh : 4739Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">; 4740 4741def int_hexagon_V6_vminuh_128B : 4742Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">; 4743 4744def int_hexagon_V6_vminw : 4745Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">; 4746 4747def int_hexagon_V6_vminw_128B : 4748Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">; 4749 4750def int_hexagon_V6_vmpabus : 4751Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">; 4752 4753def int_hexagon_V6_vmpabus_128B : 4754Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">; 4755 4756def int_hexagon_V6_vmpabus_acc : 4757Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">; 4758 4759def int_hexagon_V6_vmpabus_acc_128B : 4760Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">; 4761 4762def int_hexagon_V6_vmpabusv : 4763Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">; 4764 4765def int_hexagon_V6_vmpabusv_128B : 4766Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">; 4767 4768def int_hexagon_V6_vmpabuuv : 4769Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">; 4770 4771def int_hexagon_V6_vmpabuuv_128B : 4772Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">; 4773 4774def int_hexagon_V6_vmpahb : 4775Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">; 4776 4777def int_hexagon_V6_vmpahb_128B : 4778Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">; 4779 4780def int_hexagon_V6_vmpahb_acc : 4781Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">; 4782 4783def int_hexagon_V6_vmpahb_acc_128B : 4784Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">; 4785 4786def int_hexagon_V6_vmpybus : 4787Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">; 4788 4789def int_hexagon_V6_vmpybus_128B : 4790Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">; 4791 4792def int_hexagon_V6_vmpybus_acc : 4793Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">; 4794 4795def int_hexagon_V6_vmpybus_acc_128B : 4796Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">; 4797 4798def int_hexagon_V6_vmpybusv : 4799Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">; 4800 4801def int_hexagon_V6_vmpybusv_128B : 4802Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">; 4803 4804def int_hexagon_V6_vmpybusv_acc : 4805Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">; 4806 4807def int_hexagon_V6_vmpybusv_acc_128B : 4808Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">; 4809 4810def int_hexagon_V6_vmpybv : 4811Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">; 4812 4813def int_hexagon_V6_vmpybv_128B : 4814Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">; 4815 4816def int_hexagon_V6_vmpybv_acc : 4817Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">; 4818 4819def int_hexagon_V6_vmpybv_acc_128B : 4820Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">; 4821 4822def int_hexagon_V6_vmpyewuh : 4823Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">; 4824 4825def int_hexagon_V6_vmpyewuh_128B : 4826Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">; 4827 4828def int_hexagon_V6_vmpyh : 4829Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">; 4830 4831def int_hexagon_V6_vmpyh_128B : 4832Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">; 4833 4834def int_hexagon_V6_vmpyhsat_acc : 4835Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">; 4836 4837def int_hexagon_V6_vmpyhsat_acc_128B : 4838Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">; 4839 4840def int_hexagon_V6_vmpyhsrs : 4841Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">; 4842 4843def int_hexagon_V6_vmpyhsrs_128B : 4844Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">; 4845 4846def int_hexagon_V6_vmpyhss : 4847Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">; 4848 4849def int_hexagon_V6_vmpyhss_128B : 4850Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">; 4851 4852def int_hexagon_V6_vmpyhus : 4853Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">; 4854 4855def int_hexagon_V6_vmpyhus_128B : 4856Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">; 4857 4858def int_hexagon_V6_vmpyhus_acc : 4859Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">; 4860 4861def int_hexagon_V6_vmpyhus_acc_128B : 4862Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">; 4863 4864def int_hexagon_V6_vmpyhv : 4865Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">; 4866 4867def int_hexagon_V6_vmpyhv_128B : 4868Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">; 4869 4870def int_hexagon_V6_vmpyhv_acc : 4871Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">; 4872 4873def int_hexagon_V6_vmpyhv_acc_128B : 4874Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">; 4875 4876def int_hexagon_V6_vmpyhvsrs : 4877Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">; 4878 4879def int_hexagon_V6_vmpyhvsrs_128B : 4880Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">; 4881 4882def int_hexagon_V6_vmpyieoh : 4883Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">; 4884 4885def int_hexagon_V6_vmpyieoh_128B : 4886Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">; 4887 4888def int_hexagon_V6_vmpyiewh_acc : 4889Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">; 4890 4891def int_hexagon_V6_vmpyiewh_acc_128B : 4892Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">; 4893 4894def int_hexagon_V6_vmpyiewuh : 4895Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">; 4896 4897def int_hexagon_V6_vmpyiewuh_128B : 4898Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">; 4899 4900def int_hexagon_V6_vmpyiewuh_acc : 4901Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">; 4902 4903def int_hexagon_V6_vmpyiewuh_acc_128B : 4904Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">; 4905 4906def int_hexagon_V6_vmpyih : 4907Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">; 4908 4909def int_hexagon_V6_vmpyih_128B : 4910Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">; 4911 4912def int_hexagon_V6_vmpyih_acc : 4913Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">; 4914 4915def int_hexagon_V6_vmpyih_acc_128B : 4916Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">; 4917 4918def int_hexagon_V6_vmpyihb : 4919Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">; 4920 4921def int_hexagon_V6_vmpyihb_128B : 4922Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">; 4923 4924def int_hexagon_V6_vmpyihb_acc : 4925Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">; 4926 4927def int_hexagon_V6_vmpyihb_acc_128B : 4928Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">; 4929 4930def int_hexagon_V6_vmpyiowh : 4931Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">; 4932 4933def int_hexagon_V6_vmpyiowh_128B : 4934Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">; 4935 4936def int_hexagon_V6_vmpyiwb : 4937Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">; 4938 4939def int_hexagon_V6_vmpyiwb_128B : 4940Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">; 4941 4942def int_hexagon_V6_vmpyiwb_acc : 4943Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">; 4944 4945def int_hexagon_V6_vmpyiwb_acc_128B : 4946Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">; 4947 4948def int_hexagon_V6_vmpyiwh : 4949Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">; 4950 4951def int_hexagon_V6_vmpyiwh_128B : 4952Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">; 4953 4954def int_hexagon_V6_vmpyiwh_acc : 4955Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">; 4956 4957def int_hexagon_V6_vmpyiwh_acc_128B : 4958Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">; 4959 4960def int_hexagon_V6_vmpyowh : 4961Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">; 4962 4963def int_hexagon_V6_vmpyowh_128B : 4964Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">; 4965 4966def int_hexagon_V6_vmpyowh_rnd : 4967Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">; 4968 4969def int_hexagon_V6_vmpyowh_rnd_128B : 4970Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">; 4971 4972def int_hexagon_V6_vmpyowh_rnd_sacc : 4973Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">; 4974 4975def int_hexagon_V6_vmpyowh_rnd_sacc_128B : 4976Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">; 4977 4978def int_hexagon_V6_vmpyowh_sacc : 4979Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">; 4980 4981def int_hexagon_V6_vmpyowh_sacc_128B : 4982Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">; 4983 4984def int_hexagon_V6_vmpyub : 4985Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">; 4986 4987def int_hexagon_V6_vmpyub_128B : 4988Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">; 4989 4990def int_hexagon_V6_vmpyub_acc : 4991Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">; 4992 4993def int_hexagon_V6_vmpyub_acc_128B : 4994Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">; 4995 4996def int_hexagon_V6_vmpyubv : 4997Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">; 4998 4999def int_hexagon_V6_vmpyubv_128B : 5000Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">; 5001 5002def int_hexagon_V6_vmpyubv_acc : 5003Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">; 5004 5005def int_hexagon_V6_vmpyubv_acc_128B : 5006Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">; 5007 5008def int_hexagon_V6_vmpyuh : 5009Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">; 5010 5011def int_hexagon_V6_vmpyuh_128B : 5012Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">; 5013 5014def int_hexagon_V6_vmpyuh_acc : 5015Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">; 5016 5017def int_hexagon_V6_vmpyuh_acc_128B : 5018Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">; 5019 5020def int_hexagon_V6_vmpyuhv : 5021Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">; 5022 5023def int_hexagon_V6_vmpyuhv_128B : 5024Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">; 5025 5026def int_hexagon_V6_vmpyuhv_acc : 5027Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">; 5028 5029def int_hexagon_V6_vmpyuhv_acc_128B : 5030Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">; 5031 5032def int_hexagon_V6_vmux : 5033Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vmux">; 5034 5035def int_hexagon_V6_vmux_128B : 5036Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vmux_128B">; 5037 5038def int_hexagon_V6_vnavgh : 5039Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">; 5040 5041def int_hexagon_V6_vnavgh_128B : 5042Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">; 5043 5044def int_hexagon_V6_vnavgub : 5045Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">; 5046 5047def int_hexagon_V6_vnavgub_128B : 5048Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">; 5049 5050def int_hexagon_V6_vnavgw : 5051Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">; 5052 5053def int_hexagon_V6_vnavgw_128B : 5054Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">; 5055 5056def int_hexagon_V6_vnormamth : 5057Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">; 5058 5059def int_hexagon_V6_vnormamth_128B : 5060Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">; 5061 5062def int_hexagon_V6_vnormamtw : 5063Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">; 5064 5065def int_hexagon_V6_vnormamtw_128B : 5066Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">; 5067 5068def int_hexagon_V6_vnot : 5069Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">; 5070 5071def int_hexagon_V6_vnot_128B : 5072Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">; 5073 5074def int_hexagon_V6_vor : 5075Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">; 5076 5077def int_hexagon_V6_vor_128B : 5078Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">; 5079 5080def int_hexagon_V6_vpackeb : 5081Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">; 5082 5083def int_hexagon_V6_vpackeb_128B : 5084Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">; 5085 5086def int_hexagon_V6_vpackeh : 5087Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">; 5088 5089def int_hexagon_V6_vpackeh_128B : 5090Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">; 5091 5092def int_hexagon_V6_vpackhb_sat : 5093Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">; 5094 5095def int_hexagon_V6_vpackhb_sat_128B : 5096Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">; 5097 5098def int_hexagon_V6_vpackhub_sat : 5099Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">; 5100 5101def int_hexagon_V6_vpackhub_sat_128B : 5102Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">; 5103 5104def int_hexagon_V6_vpackob : 5105Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">; 5106 5107def int_hexagon_V6_vpackob_128B : 5108Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">; 5109 5110def int_hexagon_V6_vpackoh : 5111Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">; 5112 5113def int_hexagon_V6_vpackoh_128B : 5114Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">; 5115 5116def int_hexagon_V6_vpackwh_sat : 5117Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">; 5118 5119def int_hexagon_V6_vpackwh_sat_128B : 5120Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">; 5121 5122def int_hexagon_V6_vpackwuh_sat : 5123Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">; 5124 5125def int_hexagon_V6_vpackwuh_sat_128B : 5126Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">; 5127 5128def int_hexagon_V6_vpopcounth : 5129Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">; 5130 5131def int_hexagon_V6_vpopcounth_128B : 5132Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">; 5133 5134def int_hexagon_V6_vrdelta : 5135Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">; 5136 5137def int_hexagon_V6_vrdelta_128B : 5138Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">; 5139 5140def int_hexagon_V6_vrmpybus : 5141Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">; 5142 5143def int_hexagon_V6_vrmpybus_128B : 5144Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_128B">; 5145 5146def int_hexagon_V6_vrmpybus_acc : 5147Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc">; 5148 5149def int_hexagon_V6_vrmpybus_acc_128B : 5150Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">; 5151 5152def int_hexagon_V6_vrmpybusi : 5153Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5154 5155def int_hexagon_V6_vrmpybusi_128B : 5156Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5157 5158def int_hexagon_V6_vrmpybusi_acc : 5159Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5160 5161def int_hexagon_V6_vrmpybusi_acc_128B : 5162Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5163 5164def int_hexagon_V6_vrmpybusv : 5165Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv">; 5166 5167def int_hexagon_V6_vrmpybusv_128B : 5168Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">; 5169 5170def int_hexagon_V6_vrmpybusv_acc : 5171Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">; 5172 5173def int_hexagon_V6_vrmpybusv_acc_128B : 5174Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">; 5175 5176def int_hexagon_V6_vrmpybv : 5177Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">; 5178 5179def int_hexagon_V6_vrmpybv_128B : 5180Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">; 5181 5182def int_hexagon_V6_vrmpybv_acc : 5183Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">; 5184 5185def int_hexagon_V6_vrmpybv_acc_128B : 5186Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">; 5187 5188def int_hexagon_V6_vrmpyub : 5189Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">; 5190 5191def int_hexagon_V6_vrmpyub_128B : 5192Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">; 5193 5194def int_hexagon_V6_vrmpyub_acc : 5195Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">; 5196 5197def int_hexagon_V6_vrmpyub_acc_128B : 5198Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">; 5199 5200def int_hexagon_V6_vrmpyubi : 5201Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5202 5203def int_hexagon_V6_vrmpyubi_128B : 5204Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5205 5206def int_hexagon_V6_vrmpyubi_acc : 5207Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5208 5209def int_hexagon_V6_vrmpyubi_acc_128B : 5210Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5211 5212def int_hexagon_V6_vrmpyubv : 5213Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">; 5214 5215def int_hexagon_V6_vrmpyubv_128B : 5216Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">; 5217 5218def int_hexagon_V6_vrmpyubv_acc : 5219Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">; 5220 5221def int_hexagon_V6_vrmpyubv_acc_128B : 5222Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">; 5223 5224def int_hexagon_V6_vror : 5225Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">; 5226 5227def int_hexagon_V6_vror_128B : 5228Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">; 5229 5230def int_hexagon_V6_vroundhb : 5231Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">; 5232 5233def int_hexagon_V6_vroundhb_128B : 5234Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhb_128B">; 5235 5236def int_hexagon_V6_vroundhub : 5237Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">; 5238 5239def int_hexagon_V6_vroundhub_128B : 5240Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">; 5241 5242def int_hexagon_V6_vroundwh : 5243Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">; 5244 5245def int_hexagon_V6_vroundwh_128B : 5246Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">; 5247 5248def int_hexagon_V6_vroundwuh : 5249Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">; 5250 5251def int_hexagon_V6_vroundwuh_128B : 5252Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">; 5253 5254def int_hexagon_V6_vrsadubi : 5255Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5256 5257def int_hexagon_V6_vrsadubi_128B : 5258Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5259 5260def int_hexagon_V6_vrsadubi_acc : 5261Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5262 5263def int_hexagon_V6_vrsadubi_acc_128B : 5264Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5265 5266def int_hexagon_V6_vsathub : 5267Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">; 5268 5269def int_hexagon_V6_vsathub_128B : 5270Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsathub_128B">; 5271 5272def int_hexagon_V6_vsatwh : 5273Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">; 5274 5275def int_hexagon_V6_vsatwh_128B : 5276Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">; 5277 5278def int_hexagon_V6_vsb : 5279Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">; 5280 5281def int_hexagon_V6_vsb_128B : 5282Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">; 5283 5284def int_hexagon_V6_vsh : 5285Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">; 5286 5287def int_hexagon_V6_vsh_128B : 5288Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">; 5289 5290def int_hexagon_V6_vshufeh : 5291Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">; 5292 5293def int_hexagon_V6_vshufeh_128B : 5294Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">; 5295 5296def int_hexagon_V6_vshuffb : 5297Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">; 5298 5299def int_hexagon_V6_vshuffb_128B : 5300Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">; 5301 5302def int_hexagon_V6_vshuffeb : 5303Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">; 5304 5305def int_hexagon_V6_vshuffeb_128B : 5306Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">; 5307 5308def int_hexagon_V6_vshuffh : 5309Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">; 5310 5311def int_hexagon_V6_vshuffh_128B : 5312Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">; 5313 5314def int_hexagon_V6_vshuffob : 5315Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">; 5316 5317def int_hexagon_V6_vshuffob_128B : 5318Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">; 5319 5320def int_hexagon_V6_vshuffvdd : 5321Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">; 5322 5323def int_hexagon_V6_vshuffvdd_128B : 5324Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">; 5325 5326def int_hexagon_V6_vshufoeb : 5327Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">; 5328 5329def int_hexagon_V6_vshufoeb_128B : 5330Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">; 5331 5332def int_hexagon_V6_vshufoeh : 5333Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">; 5334 5335def int_hexagon_V6_vshufoeh_128B : 5336Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">; 5337 5338def int_hexagon_V6_vshufoh : 5339Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">; 5340 5341def int_hexagon_V6_vshufoh_128B : 5342Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">; 5343 5344def int_hexagon_V6_vsubb : 5345Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">; 5346 5347def int_hexagon_V6_vsubb_128B : 5348Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">; 5349 5350def int_hexagon_V6_vsubb_dv : 5351Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">; 5352 5353def int_hexagon_V6_vsubb_dv_128B : 5354Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">; 5355 5356def int_hexagon_V6_vsubbnq : 5357Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbnq">; 5358 5359def int_hexagon_V6_vsubbnq_128B : 5360Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbnq_128B">; 5361 5362def int_hexagon_V6_vsubbq : 5363Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbq">; 5364 5365def int_hexagon_V6_vsubbq_128B : 5366Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbq_128B">; 5367 5368def int_hexagon_V6_vsubh : 5369Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">; 5370 5371def int_hexagon_V6_vsubh_128B : 5372Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">; 5373 5374def int_hexagon_V6_vsubh_dv : 5375Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">; 5376 5377def int_hexagon_V6_vsubh_dv_128B : 5378Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">; 5379 5380def int_hexagon_V6_vsubhnq : 5381Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhnq">; 5382 5383def int_hexagon_V6_vsubhnq_128B : 5384Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhnq_128B">; 5385 5386def int_hexagon_V6_vsubhq : 5387Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhq">; 5388 5389def int_hexagon_V6_vsubhq_128B : 5390Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhq_128B">; 5391 5392def int_hexagon_V6_vsubhsat : 5393Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">; 5394 5395def int_hexagon_V6_vsubhsat_128B : 5396Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">; 5397 5398def int_hexagon_V6_vsubhsat_dv : 5399Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">; 5400 5401def int_hexagon_V6_vsubhsat_dv_128B : 5402Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">; 5403 5404def int_hexagon_V6_vsubhw : 5405Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">; 5406 5407def int_hexagon_V6_vsubhw_128B : 5408Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">; 5409 5410def int_hexagon_V6_vsububh : 5411Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">; 5412 5413def int_hexagon_V6_vsububh_128B : 5414Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">; 5415 5416def int_hexagon_V6_vsububsat : 5417Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">; 5418 5419def int_hexagon_V6_vsububsat_128B : 5420Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">; 5421 5422def int_hexagon_V6_vsububsat_dv : 5423Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">; 5424 5425def int_hexagon_V6_vsububsat_dv_128B : 5426Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">; 5427 5428def int_hexagon_V6_vsubuhsat : 5429Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">; 5430 5431def int_hexagon_V6_vsubuhsat_128B : 5432Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">; 5433 5434def int_hexagon_V6_vsubuhsat_dv : 5435Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">; 5436 5437def int_hexagon_V6_vsubuhsat_dv_128B : 5438Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">; 5439 5440def int_hexagon_V6_vsubuhw : 5441Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">; 5442 5443def int_hexagon_V6_vsubuhw_128B : 5444Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">; 5445 5446def int_hexagon_V6_vsubw : 5447Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">; 5448 5449def int_hexagon_V6_vsubw_128B : 5450Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">; 5451 5452def int_hexagon_V6_vsubw_dv : 5453Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">; 5454 5455def int_hexagon_V6_vsubw_dv_128B : 5456Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">; 5457 5458def int_hexagon_V6_vsubwnq : 5459Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwnq">; 5460 5461def int_hexagon_V6_vsubwnq_128B : 5462Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwnq_128B">; 5463 5464def int_hexagon_V6_vsubwq : 5465Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwq">; 5466 5467def int_hexagon_V6_vsubwq_128B : 5468Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwq_128B">; 5469 5470def int_hexagon_V6_vsubwsat : 5471Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">; 5472 5473def int_hexagon_V6_vsubwsat_128B : 5474Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">; 5475 5476def int_hexagon_V6_vsubwsat_dv : 5477Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">; 5478 5479def int_hexagon_V6_vsubwsat_dv_128B : 5480Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">; 5481 5482def int_hexagon_V6_vswap : 5483Hexagon_v32i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vswap">; 5484 5485def int_hexagon_V6_vswap_128B : 5486Hexagon_v64i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vswap_128B">; 5487 5488def int_hexagon_V6_vtmpyb : 5489Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">; 5490 5491def int_hexagon_V6_vtmpyb_128B : 5492Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">; 5493 5494def int_hexagon_V6_vtmpyb_acc : 5495Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">; 5496 5497def int_hexagon_V6_vtmpyb_acc_128B : 5498Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">; 5499 5500def int_hexagon_V6_vtmpybus : 5501Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">; 5502 5503def int_hexagon_V6_vtmpybus_128B : 5504Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">; 5505 5506def int_hexagon_V6_vtmpybus_acc : 5507Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">; 5508 5509def int_hexagon_V6_vtmpybus_acc_128B : 5510Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">; 5511 5512def int_hexagon_V6_vtmpyhb : 5513Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">; 5514 5515def int_hexagon_V6_vtmpyhb_128B : 5516Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">; 5517 5518def int_hexagon_V6_vtmpyhb_acc : 5519Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">; 5520 5521def int_hexagon_V6_vtmpyhb_acc_128B : 5522Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">; 5523 5524def int_hexagon_V6_vunpackb : 5525Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">; 5526 5527def int_hexagon_V6_vunpackb_128B : 5528Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">; 5529 5530def int_hexagon_V6_vunpackh : 5531Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">; 5532 5533def int_hexagon_V6_vunpackh_128B : 5534Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">; 5535 5536def int_hexagon_V6_vunpackob : 5537Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">; 5538 5539def int_hexagon_V6_vunpackob_128B : 5540Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">; 5541 5542def int_hexagon_V6_vunpackoh : 5543Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">; 5544 5545def int_hexagon_V6_vunpackoh_128B : 5546Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">; 5547 5548def int_hexagon_V6_vunpackub : 5549Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">; 5550 5551def int_hexagon_V6_vunpackub_128B : 5552Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">; 5553 5554def int_hexagon_V6_vunpackuh : 5555Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">; 5556 5557def int_hexagon_V6_vunpackuh_128B : 5558Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">; 5559 5560def int_hexagon_V6_vxor : 5561Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">; 5562 5563def int_hexagon_V6_vxor_128B : 5564Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">; 5565 5566def int_hexagon_V6_vzb : 5567Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">; 5568 5569def int_hexagon_V6_vzb_128B : 5570Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">; 5571 5572def int_hexagon_V6_vzh : 5573Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">; 5574 5575def int_hexagon_V6_vzh_128B : 5576Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">; 5577 5578// V62 HVX Instructions. 5579 5580def int_hexagon_V6_lvsplatb : 5581Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">; 5582 5583def int_hexagon_V6_lvsplatb_128B : 5584Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">; 5585 5586def int_hexagon_V6_lvsplath : 5587Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">; 5588 5589def int_hexagon_V6_lvsplath_128B : 5590Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">; 5591 5592def int_hexagon_V6_pred_scalar2v2 : 5593Hexagon_v64i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2">; 5594 5595def int_hexagon_V6_pred_scalar2v2_128B : 5596Hexagon_v128i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">; 5597 5598def int_hexagon_V6_shuffeqh : 5599Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_shuffeqh">; 5600 5601def int_hexagon_V6_shuffeqh_128B : 5602Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_shuffeqh_128B">; 5603 5604def int_hexagon_V6_shuffeqw : 5605Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_shuffeqw">; 5606 5607def int_hexagon_V6_shuffeqw_128B : 5608Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_shuffeqw_128B">; 5609 5610def int_hexagon_V6_vaddbsat : 5611Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">; 5612 5613def int_hexagon_V6_vaddbsat_128B : 5614Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_128B">; 5615 5616def int_hexagon_V6_vaddbsat_dv : 5617Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">; 5618 5619def int_hexagon_V6_vaddbsat_dv_128B : 5620Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">; 5621 5622def int_hexagon_V6_vaddcarry : 5623Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic; 5624 5625def int_hexagon_V6_vaddcarry_128B : 5626Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B; 5627 5628def int_hexagon_V6_vaddclbh : 5629Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">; 5630 5631def int_hexagon_V6_vaddclbh_128B : 5632Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">; 5633 5634def int_hexagon_V6_vaddclbw : 5635Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">; 5636 5637def int_hexagon_V6_vaddclbw_128B : 5638Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">; 5639 5640def int_hexagon_V6_vaddhw_acc : 5641Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">; 5642 5643def int_hexagon_V6_vaddhw_acc_128B : 5644Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">; 5645 5646def int_hexagon_V6_vaddubh_acc : 5647Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">; 5648 5649def int_hexagon_V6_vaddubh_acc_128B : 5650Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">; 5651 5652def int_hexagon_V6_vaddububb_sat : 5653Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">; 5654 5655def int_hexagon_V6_vaddububb_sat_128B : 5656Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">; 5657 5658def int_hexagon_V6_vadduhw_acc : 5659Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">; 5660 5661def int_hexagon_V6_vadduhw_acc_128B : 5662Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">; 5663 5664def int_hexagon_V6_vadduwsat : 5665Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">; 5666 5667def int_hexagon_V6_vadduwsat_128B : 5668Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">; 5669 5670def int_hexagon_V6_vadduwsat_dv : 5671Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">; 5672 5673def int_hexagon_V6_vadduwsat_dv_128B : 5674Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">; 5675 5676def int_hexagon_V6_vandnqrt : 5677Hexagon_v16i32_v64i1i32_Intrinsic<"HEXAGON_V6_vandnqrt">; 5678 5679def int_hexagon_V6_vandnqrt_128B : 5680Hexagon_v32i32_v128i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_128B">; 5681 5682def int_hexagon_V6_vandnqrt_acc : 5683Hexagon_v16i32_v16i32v64i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc">; 5684 5685def int_hexagon_V6_vandnqrt_acc_128B : 5686Hexagon_v32i32_v32i32v128i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">; 5687 5688def int_hexagon_V6_vandvnqv : 5689Hexagon_v16i32_v64i1v16i32_Intrinsic<"HEXAGON_V6_vandvnqv">; 5690 5691def int_hexagon_V6_vandvnqv_128B : 5692Hexagon_v32i32_v128i1v32i32_Intrinsic<"HEXAGON_V6_vandvnqv_128B">; 5693 5694def int_hexagon_V6_vandvqv : 5695Hexagon_v16i32_v64i1v16i32_Intrinsic<"HEXAGON_V6_vandvqv">; 5696 5697def int_hexagon_V6_vandvqv_128B : 5698Hexagon_v32i32_v128i1v32i32_Intrinsic<"HEXAGON_V6_vandvqv_128B">; 5699 5700def int_hexagon_V6_vasrhbsat : 5701Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">; 5702 5703def int_hexagon_V6_vasrhbsat_128B : 5704Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">; 5705 5706def int_hexagon_V6_vasruwuhrndsat : 5707Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">; 5708 5709def int_hexagon_V6_vasruwuhrndsat_128B : 5710Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">; 5711 5712def int_hexagon_V6_vasrwuhrndsat : 5713Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">; 5714 5715def int_hexagon_V6_vasrwuhrndsat_128B : 5716Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">; 5717 5718def int_hexagon_V6_vlsrb : 5719Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">; 5720 5721def int_hexagon_V6_vlsrb_128B : 5722Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">; 5723 5724def int_hexagon_V6_vlutvvb_nm : 5725Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">; 5726 5727def int_hexagon_V6_vlutvvb_nm_128B : 5728Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">; 5729 5730def int_hexagon_V6_vlutvvb_oracci : 5731Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5732 5733def int_hexagon_V6_vlutvvb_oracci_128B : 5734Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5735 5736def int_hexagon_V6_vlutvvbi : 5737Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5738 5739def int_hexagon_V6_vlutvvbi_128B : 5740Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5741 5742def int_hexagon_V6_vlutvwh_nm : 5743Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">; 5744 5745def int_hexagon_V6_vlutvwh_nm_128B : 5746Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">; 5747 5748def int_hexagon_V6_vlutvwh_oracci : 5749Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5750 5751def int_hexagon_V6_vlutvwh_oracci_128B : 5752Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5753 5754def int_hexagon_V6_vlutvwhi : 5755Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5756 5757def int_hexagon_V6_vlutvwhi_128B : 5758Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5759 5760def int_hexagon_V6_vmaxb : 5761Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">; 5762 5763def int_hexagon_V6_vmaxb_128B : 5764Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxb_128B">; 5765 5766def int_hexagon_V6_vminb : 5767Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">; 5768 5769def int_hexagon_V6_vminb_128B : 5770Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">; 5771 5772def int_hexagon_V6_vmpauhb : 5773Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">; 5774 5775def int_hexagon_V6_vmpauhb_128B : 5776Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">; 5777 5778def int_hexagon_V6_vmpauhb_acc : 5779Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">; 5780 5781def int_hexagon_V6_vmpauhb_acc_128B : 5782Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">; 5783 5784def int_hexagon_V6_vmpyewuh_64 : 5785Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">; 5786 5787def int_hexagon_V6_vmpyewuh_64_128B : 5788Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">; 5789 5790def int_hexagon_V6_vmpyiwub : 5791Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">; 5792 5793def int_hexagon_V6_vmpyiwub_128B : 5794Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">; 5795 5796def int_hexagon_V6_vmpyiwub_acc : 5797Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">; 5798 5799def int_hexagon_V6_vmpyiwub_acc_128B : 5800Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">; 5801 5802def int_hexagon_V6_vmpyowh_64_acc : 5803Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">; 5804 5805def int_hexagon_V6_vmpyowh_64_acc_128B : 5806Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">; 5807 5808def int_hexagon_V6_vrounduhub : 5809Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">; 5810 5811def int_hexagon_V6_vrounduhub_128B : 5812Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">; 5813 5814def int_hexagon_V6_vrounduwuh : 5815Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">; 5816 5817def int_hexagon_V6_vrounduwuh_128B : 5818Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">; 5819 5820def int_hexagon_V6_vsatuwuh : 5821Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">; 5822 5823def int_hexagon_V6_vsatuwuh_128B : 5824Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">; 5825 5826def int_hexagon_V6_vsubbsat : 5827Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">; 5828 5829def int_hexagon_V6_vsubbsat_128B : 5830Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">; 5831 5832def int_hexagon_V6_vsubbsat_dv : 5833Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">; 5834 5835def int_hexagon_V6_vsubbsat_dv_128B : 5836Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">; 5837 5838def int_hexagon_V6_vsubcarry : 5839Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic; 5840 5841def int_hexagon_V6_vsubcarry_128B : 5842Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B; 5843 5844def int_hexagon_V6_vsubububb_sat : 5845Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">; 5846 5847def int_hexagon_V6_vsubububb_sat_128B : 5848Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">; 5849 5850def int_hexagon_V6_vsubuwsat : 5851Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">; 5852 5853def int_hexagon_V6_vsubuwsat_128B : 5854Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">; 5855 5856def int_hexagon_V6_vsubuwsat_dv : 5857Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">; 5858 5859def int_hexagon_V6_vsubuwsat_dv_128B : 5860Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">; 5861 5862// V65 HVX Instructions. 5863 5864def int_hexagon_V6_vabsb : 5865Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">; 5866 5867def int_hexagon_V6_vabsb_128B : 5868Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_128B">; 5869 5870def int_hexagon_V6_vabsb_sat : 5871Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">; 5872 5873def int_hexagon_V6_vabsb_sat_128B : 5874Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">; 5875 5876def int_hexagon_V6_vaslh_acc : 5877Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">; 5878 5879def int_hexagon_V6_vaslh_acc_128B : 5880Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">; 5881 5882def int_hexagon_V6_vasrh_acc : 5883Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">; 5884 5885def int_hexagon_V6_vasrh_acc_128B : 5886Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">; 5887 5888def int_hexagon_V6_vasruhubrndsat : 5889Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">; 5890 5891def int_hexagon_V6_vasruhubrndsat_128B : 5892Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">; 5893 5894def int_hexagon_V6_vasruhubsat : 5895Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">; 5896 5897def int_hexagon_V6_vasruhubsat_128B : 5898Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">; 5899 5900def int_hexagon_V6_vasruwuhsat : 5901Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">; 5902 5903def int_hexagon_V6_vasruwuhsat_128B : 5904Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">; 5905 5906def int_hexagon_V6_vavgb : 5907Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">; 5908 5909def int_hexagon_V6_vavgb_128B : 5910Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">; 5911 5912def int_hexagon_V6_vavgbrnd : 5913Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">; 5914 5915def int_hexagon_V6_vavgbrnd_128B : 5916Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">; 5917 5918def int_hexagon_V6_vavguw : 5919Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">; 5920 5921def int_hexagon_V6_vavguw_128B : 5922Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">; 5923 5924def int_hexagon_V6_vavguwrnd : 5925Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">; 5926 5927def int_hexagon_V6_vavguwrnd_128B : 5928Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">; 5929 5930def int_hexagon_V6_vdd0 : 5931Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">; 5932 5933def int_hexagon_V6_vdd0_128B : 5934Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">; 5935 5936def int_hexagon_V6_vgathermh : 5937Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermh", [IntrArgMemOnly]>; 5938 5939def int_hexagon_V6_vgathermh_128B : 5940Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermh_128B", [IntrArgMemOnly]>; 5941 5942def int_hexagon_V6_vgathermhq : 5943Hexagon__ptrv64i1i32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermhq", [IntrArgMemOnly]>; 5944 5945def int_hexagon_V6_vgathermhq_128B : 5946Hexagon__ptrv128i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhq_128B", [IntrArgMemOnly]>; 5947 5948def int_hexagon_V6_vgathermhw : 5949Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhw", [IntrArgMemOnly]>; 5950 5951def int_hexagon_V6_vgathermhw_128B : 5952Hexagon__ptri32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhw_128B", [IntrArgMemOnly]>; 5953 5954def int_hexagon_V6_vgathermhwq : 5955Hexagon__ptrv64i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhwq", [IntrArgMemOnly]>; 5956 5957def int_hexagon_V6_vgathermhwq_128B : 5958Hexagon__ptrv128i1i32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhwq_128B", [IntrArgMemOnly]>; 5959 5960def int_hexagon_V6_vgathermw : 5961Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermw", [IntrArgMemOnly]>; 5962 5963def int_hexagon_V6_vgathermw_128B : 5964Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermw_128B", [IntrArgMemOnly]>; 5965 5966def int_hexagon_V6_vgathermwq : 5967Hexagon__ptrv64i1i32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermwq", [IntrArgMemOnly]>; 5968 5969def int_hexagon_V6_vgathermwq_128B : 5970Hexagon__ptrv128i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermwq_128B", [IntrArgMemOnly]>; 5971 5972def int_hexagon_V6_vlut4 : 5973Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">; 5974 5975def int_hexagon_V6_vlut4_128B : 5976Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">; 5977 5978def int_hexagon_V6_vmpabuu : 5979Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">; 5980 5981def int_hexagon_V6_vmpabuu_128B : 5982Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_128B">; 5983 5984def int_hexagon_V6_vmpabuu_acc : 5985Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">; 5986 5987def int_hexagon_V6_vmpabuu_acc_128B : 5988Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">; 5989 5990def int_hexagon_V6_vmpahhsat : 5991Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">; 5992 5993def int_hexagon_V6_vmpahhsat_128B : 5994Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">; 5995 5996def int_hexagon_V6_vmpauhuhsat : 5997Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat">; 5998 5999def int_hexagon_V6_vmpauhuhsat_128B : 6000Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">; 6001 6002def int_hexagon_V6_vmpsuhuhsat : 6003Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">; 6004 6005def int_hexagon_V6_vmpsuhuhsat_128B : 6006Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">; 6007 6008def int_hexagon_V6_vmpyh_acc : 6009Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">; 6010 6011def int_hexagon_V6_vmpyh_acc_128B : 6012Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">; 6013 6014def int_hexagon_V6_vmpyuhe : 6015Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">; 6016 6017def int_hexagon_V6_vmpyuhe_128B : 6018Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">; 6019 6020def int_hexagon_V6_vmpyuhe_acc : 6021Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">; 6022 6023def int_hexagon_V6_vmpyuhe_acc_128B : 6024Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">; 6025 6026def int_hexagon_V6_vnavgb : 6027Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">; 6028 6029def int_hexagon_V6_vnavgb_128B : 6030Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">; 6031 6032def int_hexagon_V6_vprefixqb : 6033Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqb">; 6034 6035def int_hexagon_V6_vprefixqb_128B : 6036Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqb_128B">; 6037 6038def int_hexagon_V6_vprefixqh : 6039Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqh">; 6040 6041def int_hexagon_V6_vprefixqh_128B : 6042Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqh_128B">; 6043 6044def int_hexagon_V6_vprefixqw : 6045Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqw">; 6046 6047def int_hexagon_V6_vprefixqw_128B : 6048Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqw_128B">; 6049 6050def int_hexagon_V6_vscattermh : 6051Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh", [IntrWriteMem]>; 6052 6053def int_hexagon_V6_vscattermh_128B : 6054Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_128B", [IntrWriteMem]>; 6055 6056def int_hexagon_V6_vscattermh_add : 6057Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh_add", [IntrWriteMem]>; 6058 6059def int_hexagon_V6_vscattermh_add_128B : 6060Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_add_128B", [IntrWriteMem]>; 6061 6062def int_hexagon_V6_vscattermhq : 6063Hexagon__v64i1i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhq", [IntrWriteMem]>; 6064 6065def int_hexagon_V6_vscattermhq_128B : 6066Hexagon__v128i1i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhq_128B", [IntrWriteMem]>; 6067 6068def int_hexagon_V6_vscattermhw : 6069Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw", [IntrWriteMem]>; 6070 6071def int_hexagon_V6_vscattermhw_128B : 6072Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_128B", [IntrWriteMem]>; 6073 6074def int_hexagon_V6_vscattermhw_add : 6075Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw_add", [IntrWriteMem]>; 6076 6077def int_hexagon_V6_vscattermhw_add_128B : 6078Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B", [IntrWriteMem]>; 6079 6080def int_hexagon_V6_vscattermhwq : 6081Hexagon__v64i1i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhwq", [IntrWriteMem]>; 6082 6083def int_hexagon_V6_vscattermhwq_128B : 6084Hexagon__v128i1i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhwq_128B", [IntrWriteMem]>; 6085 6086def int_hexagon_V6_vscattermw : 6087Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw", [IntrWriteMem]>; 6088 6089def int_hexagon_V6_vscattermw_128B : 6090Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_128B", [IntrWriteMem]>; 6091 6092def int_hexagon_V6_vscattermw_add : 6093Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw_add", [IntrWriteMem]>; 6094 6095def int_hexagon_V6_vscattermw_add_128B : 6096Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_add_128B", [IntrWriteMem]>; 6097 6098def int_hexagon_V6_vscattermwq : 6099Hexagon__v64i1i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermwq", [IntrWriteMem]>; 6100 6101def int_hexagon_V6_vscattermwq_128B : 6102Hexagon__v128i1i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermwq_128B", [IntrWriteMem]>; 6103 6104// V66 HVX Instructions. 6105 6106def int_hexagon_V6_vaddcarrysat : 6107Hexagon_v16i32_v16i32v16i32v64i1_Intrinsic<"HEXAGON_V6_vaddcarrysat">; 6108 6109def int_hexagon_V6_vaddcarrysat_128B : 6110Hexagon_v32i32_v32i32v32i32v128i1_Intrinsic<"HEXAGON_V6_vaddcarrysat_128B">; 6111 6112def int_hexagon_V6_vasr_into : 6113Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">; 6114 6115def int_hexagon_V6_vasr_into_128B : 6116Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">; 6117 6118def int_hexagon_V6_vrotr : 6119Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">; 6120 6121def int_hexagon_V6_vrotr_128B : 6122Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">; 6123 6124def int_hexagon_V6_vsatdw : 6125Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">; 6126 6127def int_hexagon_V6_vsatdw_128B : 6128Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">; 6129 6130// V68 HVX Instructions. 6131 6132def int_hexagon_V6_v6mpyhubs10 : 6133Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6134 6135def int_hexagon_V6_v6mpyhubs10_128B : 6136Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6137 6138def int_hexagon_V6_v6mpyhubs10_vxx : 6139Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_vxx", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6140 6141def int_hexagon_V6_v6mpyhubs10_vxx_128B : 6142Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_vxx_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6143 6144def int_hexagon_V6_v6mpyvubs10 : 6145Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6146 6147def int_hexagon_V6_v6mpyvubs10_128B : 6148Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6149 6150def int_hexagon_V6_v6mpyvubs10_vxx : 6151Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_vxx", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6152 6153def int_hexagon_V6_v6mpyvubs10_vxx_128B : 6154Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_vxx_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6155 6156def int_hexagon_V6_vabs_hf : 6157Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabs_hf">; 6158 6159def int_hexagon_V6_vabs_hf_128B : 6160Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabs_hf_128B">; 6161 6162def int_hexagon_V6_vabs_sf : 6163Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabs_sf">; 6164 6165def int_hexagon_V6_vabs_sf_128B : 6166Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabs_sf_128B">; 6167 6168def int_hexagon_V6_vadd_hf : 6169Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_hf">; 6170 6171def int_hexagon_V6_vadd_hf_128B : 6172Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_hf_128B">; 6173 6174def int_hexagon_V6_vadd_hf_hf : 6175Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_hf_hf">; 6176 6177def int_hexagon_V6_vadd_hf_hf_128B : 6178Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_hf_hf_128B">; 6179 6180def int_hexagon_V6_vadd_qf16 : 6181Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf16">; 6182 6183def int_hexagon_V6_vadd_qf16_128B : 6184Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf16_128B">; 6185 6186def int_hexagon_V6_vadd_qf16_mix : 6187Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf16_mix">; 6188 6189def int_hexagon_V6_vadd_qf16_mix_128B : 6190Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf16_mix_128B">; 6191 6192def int_hexagon_V6_vadd_qf32 : 6193Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf32">; 6194 6195def int_hexagon_V6_vadd_qf32_128B : 6196Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf32_128B">; 6197 6198def int_hexagon_V6_vadd_qf32_mix : 6199Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf32_mix">; 6200 6201def int_hexagon_V6_vadd_qf32_mix_128B : 6202Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf32_mix_128B">; 6203 6204def int_hexagon_V6_vadd_sf : 6205Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf">; 6206 6207def int_hexagon_V6_vadd_sf_128B : 6208Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_128B">; 6209 6210def int_hexagon_V6_vadd_sf_hf : 6211Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf_hf">; 6212 6213def int_hexagon_V6_vadd_sf_hf_128B : 6214Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_hf_128B">; 6215 6216def int_hexagon_V6_vadd_sf_sf : 6217Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf_sf">; 6218 6219def int_hexagon_V6_vadd_sf_sf_128B : 6220Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_sf_128B">; 6221 6222def int_hexagon_V6_vassign_fp : 6223Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign_fp">; 6224 6225def int_hexagon_V6_vassign_fp_128B : 6226Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_fp_128B">; 6227 6228def int_hexagon_V6_vconv_hf_qf16 : 6229Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf16">; 6230 6231def int_hexagon_V6_vconv_hf_qf16_128B : 6232Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf16_128B">; 6233 6234def int_hexagon_V6_vconv_hf_qf32 : 6235Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf32">; 6236 6237def int_hexagon_V6_vconv_hf_qf32_128B : 6238Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf32_128B">; 6239 6240def int_hexagon_V6_vconv_sf_qf32 : 6241Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_sf_qf32">; 6242 6243def int_hexagon_V6_vconv_sf_qf32_128B : 6244Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_sf_qf32_128B">; 6245 6246def int_hexagon_V6_vcvt_b_hf : 6247Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_b_hf">; 6248 6249def int_hexagon_V6_vcvt_b_hf_128B : 6250Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_b_hf_128B">; 6251 6252def int_hexagon_V6_vcvt_h_hf : 6253Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_h_hf">; 6254 6255def int_hexagon_V6_vcvt_h_hf_128B : 6256Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_h_hf_128B">; 6257 6258def int_hexagon_V6_vcvt_hf_b : 6259Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_b">; 6260 6261def int_hexagon_V6_vcvt_hf_b_128B : 6262Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_b_128B">; 6263 6264def int_hexagon_V6_vcvt_hf_h : 6265Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_h">; 6266 6267def int_hexagon_V6_vcvt_hf_h_128B : 6268Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_h_128B">; 6269 6270def int_hexagon_V6_vcvt_hf_sf : 6271Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_sf">; 6272 6273def int_hexagon_V6_vcvt_hf_sf_128B : 6274Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_sf_128B">; 6275 6276def int_hexagon_V6_vcvt_hf_ub : 6277Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_ub">; 6278 6279def int_hexagon_V6_vcvt_hf_ub_128B : 6280Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_ub_128B">; 6281 6282def int_hexagon_V6_vcvt_hf_uh : 6283Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_uh">; 6284 6285def int_hexagon_V6_vcvt_hf_uh_128B : 6286Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_uh_128B">; 6287 6288def int_hexagon_V6_vcvt_sf_hf : 6289Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_sf_hf">; 6290 6291def int_hexagon_V6_vcvt_sf_hf_128B : 6292Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_sf_hf_128B">; 6293 6294def int_hexagon_V6_vcvt_ub_hf : 6295Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_ub_hf">; 6296 6297def int_hexagon_V6_vcvt_ub_hf_128B : 6298Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_ub_hf_128B">; 6299 6300def int_hexagon_V6_vcvt_uh_hf : 6301Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_uh_hf">; 6302 6303def int_hexagon_V6_vcvt_uh_hf_128B : 6304Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_uh_hf_128B">; 6305 6306def int_hexagon_V6_vdmpy_sf_hf : 6307Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf">; 6308 6309def int_hexagon_V6_vdmpy_sf_hf_128B : 6310Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf_128B">; 6311 6312def int_hexagon_V6_vdmpy_sf_hf_acc : 6313Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf_acc">; 6314 6315def int_hexagon_V6_vdmpy_sf_hf_acc_128B : 6316Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf_acc_128B">; 6317 6318def int_hexagon_V6_vfmax_hf : 6319Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmax_hf">; 6320 6321def int_hexagon_V6_vfmax_hf_128B : 6322Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmax_hf_128B">; 6323 6324def int_hexagon_V6_vfmax_sf : 6325Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmax_sf">; 6326 6327def int_hexagon_V6_vfmax_sf_128B : 6328Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmax_sf_128B">; 6329 6330def int_hexagon_V6_vfmin_hf : 6331Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmin_hf">; 6332 6333def int_hexagon_V6_vfmin_hf_128B : 6334Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmin_hf_128B">; 6335 6336def int_hexagon_V6_vfmin_sf : 6337Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmin_sf">; 6338 6339def int_hexagon_V6_vfmin_sf_128B : 6340Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmin_sf_128B">; 6341 6342def int_hexagon_V6_vfneg_hf : 6343Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vfneg_hf">; 6344 6345def int_hexagon_V6_vfneg_hf_128B : 6346Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vfneg_hf_128B">; 6347 6348def int_hexagon_V6_vfneg_sf : 6349Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vfneg_sf">; 6350 6351def int_hexagon_V6_vfneg_sf_128B : 6352Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vfneg_sf_128B">; 6353 6354def int_hexagon_V6_vgthf : 6355Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf">; 6356 6357def int_hexagon_V6_vgthf_128B : 6358Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_128B">; 6359 6360def int_hexagon_V6_vgthf_and : 6361Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf_and">; 6362 6363def int_hexagon_V6_vgthf_and_128B : 6364Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_and_128B">; 6365 6366def int_hexagon_V6_vgthf_or : 6367Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf_or">; 6368 6369def int_hexagon_V6_vgthf_or_128B : 6370Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_or_128B">; 6371 6372def int_hexagon_V6_vgthf_xor : 6373Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf_xor">; 6374 6375def int_hexagon_V6_vgthf_xor_128B : 6376Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_xor_128B">; 6377 6378def int_hexagon_V6_vgtsf : 6379Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf">; 6380 6381def int_hexagon_V6_vgtsf_128B : 6382Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_128B">; 6383 6384def int_hexagon_V6_vgtsf_and : 6385Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf_and">; 6386 6387def int_hexagon_V6_vgtsf_and_128B : 6388Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_and_128B">; 6389 6390def int_hexagon_V6_vgtsf_or : 6391Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf_or">; 6392 6393def int_hexagon_V6_vgtsf_or_128B : 6394Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_or_128B">; 6395 6396def int_hexagon_V6_vgtsf_xor : 6397Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf_xor">; 6398 6399def int_hexagon_V6_vgtsf_xor_128B : 6400Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_xor_128B">; 6401 6402def int_hexagon_V6_vmax_hf : 6403Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmax_hf">; 6404 6405def int_hexagon_V6_vmax_hf_128B : 6406Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmax_hf_128B">; 6407 6408def int_hexagon_V6_vmax_sf : 6409Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmax_sf">; 6410 6411def int_hexagon_V6_vmax_sf_128B : 6412Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmax_sf_128B">; 6413 6414def int_hexagon_V6_vmin_hf : 6415Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmin_hf">; 6416 6417def int_hexagon_V6_vmin_hf_128B : 6418Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmin_hf_128B">; 6419 6420def int_hexagon_V6_vmin_sf : 6421Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmin_sf">; 6422 6423def int_hexagon_V6_vmin_sf_128B : 6424Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmin_sf_128B">; 6425 6426def int_hexagon_V6_vmpy_hf_hf : 6427Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf">; 6428 6429def int_hexagon_V6_vmpy_hf_hf_128B : 6430Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf_128B">; 6431 6432def int_hexagon_V6_vmpy_hf_hf_acc : 6433Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf_acc">; 6434 6435def int_hexagon_V6_vmpy_hf_hf_acc_128B : 6436Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf_acc_128B">; 6437 6438def int_hexagon_V6_vmpy_qf16 : 6439Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf16">; 6440 6441def int_hexagon_V6_vmpy_qf16_128B : 6442Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_128B">; 6443 6444def int_hexagon_V6_vmpy_qf16_hf : 6445Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_hf">; 6446 6447def int_hexagon_V6_vmpy_qf16_hf_128B : 6448Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_hf_128B">; 6449 6450def int_hexagon_V6_vmpy_qf16_mix_hf : 6451Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_mix_hf">; 6452 6453def int_hexagon_V6_vmpy_qf16_mix_hf_128B : 6454Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_mix_hf_128B">; 6455 6456def int_hexagon_V6_vmpy_qf32 : 6457Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32">; 6458 6459def int_hexagon_V6_vmpy_qf32_128B : 6460Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_128B">; 6461 6462def int_hexagon_V6_vmpy_qf32_hf : 6463Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_hf">; 6464 6465def int_hexagon_V6_vmpy_qf32_hf_128B : 6466Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_hf_128B">; 6467 6468def int_hexagon_V6_vmpy_qf32_mix_hf : 6469Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_mix_hf">; 6470 6471def int_hexagon_V6_vmpy_qf32_mix_hf_128B : 6472Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_mix_hf_128B">; 6473 6474def int_hexagon_V6_vmpy_qf32_qf16 : 6475Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_qf16">; 6476 6477def int_hexagon_V6_vmpy_qf32_qf16_128B : 6478Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_qf16_128B">; 6479 6480def int_hexagon_V6_vmpy_qf32_sf : 6481Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_sf">; 6482 6483def int_hexagon_V6_vmpy_qf32_sf_128B : 6484Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_sf_128B">; 6485 6486def int_hexagon_V6_vmpy_sf_hf : 6487Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf">; 6488 6489def int_hexagon_V6_vmpy_sf_hf_128B : 6490Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf_128B">; 6491 6492def int_hexagon_V6_vmpy_sf_hf_acc : 6493Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf_acc">; 6494 6495def int_hexagon_V6_vmpy_sf_hf_acc_128B : 6496Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf_acc_128B">; 6497 6498def int_hexagon_V6_vmpy_sf_sf : 6499Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_sf">; 6500 6501def int_hexagon_V6_vmpy_sf_sf_128B : 6502Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_sf_128B">; 6503 6504def int_hexagon_V6_vsub_hf : 6505Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_hf">; 6506 6507def int_hexagon_V6_vsub_hf_128B : 6508Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_hf_128B">; 6509 6510def int_hexagon_V6_vsub_hf_hf : 6511Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_hf_hf">; 6512 6513def int_hexagon_V6_vsub_hf_hf_128B : 6514Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_hf_hf_128B">; 6515 6516def int_hexagon_V6_vsub_qf16 : 6517Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf16">; 6518 6519def int_hexagon_V6_vsub_qf16_128B : 6520Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf16_128B">; 6521 6522def int_hexagon_V6_vsub_qf16_mix : 6523Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf16_mix">; 6524 6525def int_hexagon_V6_vsub_qf16_mix_128B : 6526Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf16_mix_128B">; 6527 6528def int_hexagon_V6_vsub_qf32 : 6529Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf32">; 6530 6531def int_hexagon_V6_vsub_qf32_128B : 6532Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf32_128B">; 6533 6534def int_hexagon_V6_vsub_qf32_mix : 6535Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf32_mix">; 6536 6537def int_hexagon_V6_vsub_qf32_mix_128B : 6538Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf32_mix_128B">; 6539 6540def int_hexagon_V6_vsub_sf : 6541Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf">; 6542 6543def int_hexagon_V6_vsub_sf_128B : 6544Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_128B">; 6545 6546def int_hexagon_V6_vsub_sf_hf : 6547Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf_hf">; 6548 6549def int_hexagon_V6_vsub_sf_hf_128B : 6550Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_hf_128B">; 6551 6552def int_hexagon_V6_vsub_sf_sf : 6553Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf_sf">; 6554 6555def int_hexagon_V6_vsub_sf_sf_128B : 6556Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_sf_128B">; 6557 6558// V69 HVX Instructions. 6559 6560def int_hexagon_V6_vasrvuhubrndsat : 6561Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvuhubrndsat">; 6562 6563def int_hexagon_V6_vasrvuhubrndsat_128B : 6564Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvuhubrndsat_128B">; 6565 6566def int_hexagon_V6_vasrvuhubsat : 6567Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvuhubsat">; 6568 6569def int_hexagon_V6_vasrvuhubsat_128B : 6570Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvuhubsat_128B">; 6571 6572def int_hexagon_V6_vasrvwuhrndsat : 6573Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvwuhrndsat">; 6574 6575def int_hexagon_V6_vasrvwuhrndsat_128B : 6576Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvwuhrndsat_128B">; 6577 6578def int_hexagon_V6_vasrvwuhsat : 6579Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvwuhsat">; 6580 6581def int_hexagon_V6_vasrvwuhsat_128B : 6582Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvwuhsat_128B">; 6583 6584def int_hexagon_V6_vmpyuhvs : 6585Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhvs">; 6586 6587def int_hexagon_V6_vmpyuhvs_128B : 6588Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhvs_128B">; 6589 6590