1//===- IntrinsicsLoongArch.td - Defines LoongArch intrinsics *- tablegen -*===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines all of the LoongArch-specific intrinsics. 10// 11//===----------------------------------------------------------------------===// 12 13let TargetPrefix = "loongarch" in { 14 15//===----------------------------------------------------------------------===// 16// Atomics 17 18// T @llvm.<name>.T.<p>(any*, T, T, T imm); 19class MaskedAtomicRMW<LLVMType itype> 20 : Intrinsic<[itype], [llvm_anyptr_ty, itype, itype, itype], 21 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<3>>]>; 22 23// We define 32-bit and 64-bit variants of the above, where T stands for i32 24// or i64 respectively: 25multiclass MaskedAtomicRMWIntrinsics { 26 // i32 @llvm.<name>.i32.<p>(any*, i32, i32, i32 imm); 27 def _i32 : MaskedAtomicRMW<llvm_i32_ty>; 28 // i64 @llvm.<name>.i32.<p>(any*, i64, i64, i64 imm); 29 def _i64 : MaskedAtomicRMW<llvm_i64_ty>; 30} 31 32multiclass MaskedAtomicRMWFiveOpIntrinsics { 33 // TODO: Support cmpxchg on LA32. 34 // i64 @llvm.<name>.i64.<p>(any*, i64, i64, i64, i64 imm); 35 def _i64 : MaskedAtomicRMWFiveArg<llvm_i64_ty>; 36} 37 38defm int_loongarch_masked_atomicrmw_xchg : MaskedAtomicRMWIntrinsics; 39defm int_loongarch_masked_atomicrmw_add : MaskedAtomicRMWIntrinsics; 40defm int_loongarch_masked_atomicrmw_sub : MaskedAtomicRMWIntrinsics; 41defm int_loongarch_masked_atomicrmw_nand : MaskedAtomicRMWIntrinsics; 42defm int_loongarch_masked_atomicrmw_umax : MaskedAtomicRMWIntrinsics; 43defm int_loongarch_masked_atomicrmw_umin : MaskedAtomicRMWIntrinsics; 44defm int_loongarch_masked_atomicrmw_max : MaskedAtomicRMWFiveOpIntrinsics; 45defm int_loongarch_masked_atomicrmw_min : MaskedAtomicRMWFiveOpIntrinsics; 46 47// @llvm.loongarch.masked.cmpxchg.i64.<p>( 48// ptr addr, grlen cmpval, grlen newval, grlen mask, grlenimm ordering) 49defm int_loongarch_masked_cmpxchg : MaskedAtomicRMWFiveOpIntrinsics; 50 51//===----------------------------------------------------------------------===// 52// LoongArch BASE 53 54class BaseInt<list<LLVMType> ret_types, list<LLVMType> param_types, 55 list<IntrinsicProperty> intr_properties = []> 56 : Intrinsic<ret_types, param_types, intr_properties>, 57 ClangBuiltin<!subst("int_loongarch", "__builtin_loongarch", NAME)>; 58 59def int_loongarch_break : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; 60def int_loongarch_cacop_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], 61 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 62def int_loongarch_cacop_w : BaseInt<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 63 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 64def int_loongarch_dbar : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; 65 66def int_loongarch_ibar : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; 67def int_loongarch_movfcsr2gr : BaseInt<[llvm_i32_ty], [llvm_i32_ty], 68 [ImmArg<ArgIndex<0>>]>; 69def int_loongarch_movgr2fcsr : BaseInt<[], [llvm_i32_ty, llvm_i32_ty], 70 [ImmArg<ArgIndex<0>>]>; 71def int_loongarch_syscall : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; 72 73def int_loongarch_crc_w_b_w : BaseInt<[llvm_i32_ty], 74 [llvm_i32_ty, llvm_i32_ty]>; 75def int_loongarch_crc_w_h_w : BaseInt<[llvm_i32_ty], 76 [llvm_i32_ty, llvm_i32_ty]>; 77def int_loongarch_crc_w_w_w : BaseInt<[llvm_i32_ty], 78 [llvm_i32_ty, llvm_i32_ty]>; 79def int_loongarch_crc_w_d_w : BaseInt<[llvm_i32_ty], 80 [llvm_i64_ty, llvm_i32_ty]>; 81 82def int_loongarch_crcc_w_b_w : BaseInt<[llvm_i32_ty], 83 [llvm_i32_ty, llvm_i32_ty]>; 84def int_loongarch_crcc_w_h_w : BaseInt<[llvm_i32_ty], 85 [llvm_i32_ty, llvm_i32_ty]>; 86def int_loongarch_crcc_w_w_w : BaseInt<[llvm_i32_ty], 87 [llvm_i32_ty, llvm_i32_ty]>; 88def int_loongarch_crcc_w_d_w : BaseInt<[llvm_i32_ty], 89 [llvm_i64_ty, llvm_i32_ty]>; 90 91def int_loongarch_csrrd_w : BaseInt<[llvm_i32_ty], [llvm_i32_ty], 92 [ImmArg<ArgIndex<0>>]>; 93def int_loongarch_csrrd_d : BaseInt<[llvm_i64_ty], [llvm_i32_ty], 94 [ImmArg<ArgIndex<0>>]>; 95def int_loongarch_csrwr_w : BaseInt<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 96 [ImmArg<ArgIndex<1>>]>; 97def int_loongarch_csrwr_d : BaseInt<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty], 98 [ImmArg<ArgIndex<1>>]>; 99def int_loongarch_csrxchg_w : BaseInt<[llvm_i32_ty], 100 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 101 [ImmArg<ArgIndex<2>>]>; 102def int_loongarch_csrxchg_d : BaseInt<[llvm_i64_ty], 103 [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty], 104 [ImmArg<ArgIndex<2>>]>; 105 106def int_loongarch_iocsrrd_b : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>; 107def int_loongarch_iocsrrd_h : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>; 108def int_loongarch_iocsrrd_w : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>; 109def int_loongarch_iocsrrd_d : BaseInt<[llvm_i64_ty], [llvm_i32_ty]>; 110 111def int_loongarch_iocsrwr_b : BaseInt<[], [llvm_i32_ty, llvm_i32_ty]>; 112def int_loongarch_iocsrwr_h : BaseInt<[], [llvm_i32_ty, llvm_i32_ty]>; 113def int_loongarch_iocsrwr_w : BaseInt<[], [llvm_i32_ty, llvm_i32_ty]>; 114def int_loongarch_iocsrwr_d : BaseInt<[], [llvm_i64_ty, llvm_i32_ty]>; 115 116def int_loongarch_cpucfg : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>; 117 118def int_loongarch_asrtle_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty]>; 119def int_loongarch_asrtgt_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty]>; 120 121def int_loongarch_lddir_d : BaseInt<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], 122 [ImmArg<ArgIndex<1>>]>; 123def int_loongarch_ldpte_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty], 124 [ImmArg<ArgIndex<1>>]>; 125 126def int_loongarch_frecipe_s : BaseInt<[llvm_float_ty], [llvm_float_ty], 127 [IntrNoMem]>; 128def int_loongarch_frecipe_d : BaseInt<[llvm_double_ty], [llvm_double_ty], 129 [IntrNoMem]>; 130def int_loongarch_frsqrte_s : BaseInt<[llvm_float_ty], [llvm_float_ty], 131 [IntrNoMem]>; 132def int_loongarch_frsqrte_d : BaseInt<[llvm_double_ty], [llvm_double_ty], 133 [IntrNoMem]>; 134} // TargetPrefix = "loongarch" 135 136/// Vector intrinsic 137 138class VecInt<list<LLVMType> ret_types, list<LLVMType> param_types, 139 list<IntrinsicProperty> intr_properties = []> 140 : Intrinsic<ret_types, param_types, intr_properties>, 141 ClangBuiltin<!subst("int_loongarch", "__builtin", NAME)>; 142 143//===----------------------------------------------------------------------===// 144// LSX 145 146let TargetPrefix = "loongarch" in { 147 148foreach inst = ["vadd_b", "vsub_b", 149 "vsadd_b", "vsadd_bu", "vssub_b", "vssub_bu", 150 "vavg_b", "vavg_bu", "vavgr_b", "vavgr_bu", 151 "vabsd_b", "vabsd_bu", "vadda_b", 152 "vmax_b", "vmax_bu", "vmin_b", "vmin_bu", 153 "vmul_b", "vmuh_b", "vmuh_bu", 154 "vdiv_b", "vdiv_bu", "vmod_b", "vmod_bu", "vsigncov_b", 155 "vand_v", "vor_v", "vxor_v", "vnor_v", "vandn_v", "vorn_v", 156 "vsll_b", "vsrl_b", "vsra_b", "vrotr_b", "vsrlr_b", "vsrar_b", 157 "vbitclr_b", "vbitset_b", "vbitrev_b", 158 "vseq_b", "vsle_b", "vsle_bu", "vslt_b", "vslt_bu", 159 "vpackev_b", "vpackod_b", "vpickev_b", "vpickod_b", 160 "vilvl_b", "vilvh_b"] in 161 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty], 162 [llvm_v16i8_ty, llvm_v16i8_ty], 163 [IntrNoMem]>; 164 165foreach inst = ["vadd_h", "vsub_h", 166 "vsadd_h", "vsadd_hu", "vssub_h", "vssub_hu", 167 "vavg_h", "vavg_hu", "vavgr_h", "vavgr_hu", 168 "vabsd_h", "vabsd_hu", "vadda_h", 169 "vmax_h", "vmax_hu", "vmin_h", "vmin_hu", 170 "vmul_h", "vmuh_h", "vmuh_hu", 171 "vdiv_h", "vdiv_hu", "vmod_h", "vmod_hu", "vsigncov_h", 172 "vsll_h", "vsrl_h", "vsra_h", "vrotr_h", "vsrlr_h", "vsrar_h", 173 "vbitclr_h", "vbitset_h", "vbitrev_h", 174 "vseq_h", "vsle_h", "vsle_hu", "vslt_h", "vslt_hu", 175 "vpackev_h", "vpackod_h", "vpickev_h", "vpickod_h", 176 "vilvl_h", "vilvh_h"] in 177 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 178 [llvm_v8i16_ty, llvm_v8i16_ty], 179 [IntrNoMem]>; 180 181foreach inst = ["vadd_w", "vsub_w", 182 "vsadd_w", "vsadd_wu", "vssub_w", "vssub_wu", 183 "vavg_w", "vavg_wu", "vavgr_w", "vavgr_wu", 184 "vabsd_w", "vabsd_wu", "vadda_w", 185 "vmax_w", "vmax_wu", "vmin_w", "vmin_wu", 186 "vmul_w", "vmuh_w", "vmuh_wu", 187 "vdiv_w", "vdiv_wu", "vmod_w", "vmod_wu", "vsigncov_w", 188 "vsll_w", "vsrl_w", "vsra_w", "vrotr_w", "vsrlr_w", "vsrar_w", 189 "vbitclr_w", "vbitset_w", "vbitrev_w", 190 "vseq_w", "vsle_w", "vsle_wu", "vslt_w", "vslt_wu", 191 "vpackev_w", "vpackod_w", "vpickev_w", "vpickod_w", 192 "vilvl_w", "vilvh_w"] in 193 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 194 [llvm_v4i32_ty, llvm_v4i32_ty], 195 [IntrNoMem]>; 196 197foreach inst = ["vadd_d", "vadd_q", "vsub_d", "vsub_q", 198 "vsadd_d", "vsadd_du", "vssub_d", "vssub_du", 199 "vhaddw_q_d", "vhaddw_qu_du", "vhsubw_q_d", "vhsubw_qu_du", 200 "vaddwev_q_d", "vaddwod_q_d", "vsubwev_q_d", "vsubwod_q_d", 201 "vaddwev_q_du", "vaddwod_q_du", "vsubwev_q_du", "vsubwod_q_du", 202 "vaddwev_q_du_d", "vaddwod_q_du_d", 203 "vavg_d", "vavg_du", "vavgr_d", "vavgr_du", 204 "vabsd_d", "vabsd_du", "vadda_d", 205 "vmax_d", "vmax_du", "vmin_d", "vmin_du", 206 "vmul_d", "vmuh_d", "vmuh_du", 207 "vmulwev_q_d", "vmulwod_q_d", "vmulwev_q_du", "vmulwod_q_du", 208 "vmulwev_q_du_d", "vmulwod_q_du_d", 209 "vdiv_d", "vdiv_du", "vmod_d", "vmod_du", "vsigncov_d", 210 "vsll_d", "vsrl_d", "vsra_d", "vrotr_d", "vsrlr_d", "vsrar_d", 211 "vbitclr_d", "vbitset_d", "vbitrev_d", 212 "vseq_d", "vsle_d", "vsle_du", "vslt_d", "vslt_du", 213 "vpackev_d", "vpackod_d", "vpickev_d", "vpickod_d", 214 "vilvl_d", "vilvh_d"] in 215 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], 216 [llvm_v2i64_ty, llvm_v2i64_ty], 217 [IntrNoMem]>; 218 219foreach inst = ["vaddi_bu", "vsubi_bu", 220 "vmaxi_b", "vmaxi_bu", "vmini_b", "vmini_bu", 221 "vsat_b", "vsat_bu", 222 "vandi_b", "vori_b", "vxori_b", "vnori_b", 223 "vslli_b", "vsrli_b", "vsrai_b", "vrotri_b", 224 "vsrlri_b", "vsrari_b", 225 "vbitclri_b", "vbitseti_b", "vbitrevi_b", 226 "vseqi_b", "vslei_b", "vslei_bu", "vslti_b", "vslti_bu", 227 "vreplvei_b", "vbsll_v", "vbsrl_v", "vshuf4i_b"] in 228 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty], 229 [llvm_v16i8_ty, llvm_i32_ty], 230 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 231foreach inst = ["vaddi_hu", "vsubi_hu", 232 "vmaxi_h", "vmaxi_hu", "vmini_h", "vmini_hu", 233 "vsat_h", "vsat_hu", 234 "vslli_h", "vsrli_h", "vsrai_h", "vrotri_h", 235 "vsrlri_h", "vsrari_h", 236 "vbitclri_h", "vbitseti_h", "vbitrevi_h", 237 "vseqi_h", "vslei_h", "vslei_hu", "vslti_h", "vslti_hu", 238 "vreplvei_h", "vshuf4i_h"] in 239 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 240 [llvm_v8i16_ty, llvm_i32_ty], 241 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 242foreach inst = ["vaddi_wu", "vsubi_wu", 243 "vmaxi_w", "vmaxi_wu", "vmini_w", "vmini_wu", 244 "vsat_w", "vsat_wu", 245 "vslli_w", "vsrli_w", "vsrai_w", "vrotri_w", 246 "vsrlri_w", "vsrari_w", 247 "vbitclri_w", "vbitseti_w", "vbitrevi_w", 248 "vseqi_w", "vslei_w", "vslei_wu", "vslti_w", "vslti_wu", 249 "vreplvei_w", "vshuf4i_w"] in 250 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 251 [llvm_v4i32_ty, llvm_i32_ty], 252 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 253foreach inst = ["vaddi_du", "vsubi_du", 254 "vmaxi_d", "vmaxi_du", "vmini_d", "vmini_du", 255 "vsat_d", "vsat_du", 256 "vslli_d", "vsrli_d", "vsrai_d", "vrotri_d", 257 "vsrlri_d", "vsrari_d", 258 "vbitclri_d", "vbitseti_d", "vbitrevi_d", 259 "vseqi_d", "vslei_d", "vslei_du", "vslti_d", "vslti_du", 260 "vreplvei_d"] in 261 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], 262 [llvm_v2i64_ty, llvm_i32_ty], 263 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 264 265foreach inst = ["vhaddw_h_b", "vhaddw_hu_bu", "vhsubw_h_b", "vhsubw_hu_bu", 266 "vaddwev_h_b", "vaddwod_h_b", "vsubwev_h_b", "vsubwod_h_b", 267 "vaddwev_h_bu", "vaddwod_h_bu", "vsubwev_h_bu", "vsubwod_h_bu", 268 "vaddwev_h_bu_b", "vaddwod_h_bu_b", 269 "vmulwev_h_b", "vmulwod_h_b", "vmulwev_h_bu", "vmulwod_h_bu", 270 "vmulwev_h_bu_b", "vmulwod_h_bu_b"] in 271 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 272 [llvm_v16i8_ty, llvm_v16i8_ty], 273 [IntrNoMem]>; 274 275foreach inst = ["vhaddw_w_h", "vhaddw_wu_hu", "vhsubw_w_h", "vhsubw_wu_hu", 276 "vaddwev_w_h", "vaddwod_w_h", "vsubwev_w_h", "vsubwod_w_h", 277 "vaddwev_w_hu", "vaddwod_w_hu", "vsubwev_w_hu", "vsubwod_w_hu", 278 "vaddwev_w_hu_h", "vaddwod_w_hu_h", 279 "vmulwev_w_h", "vmulwod_w_h", "vmulwev_w_hu", "vmulwod_w_hu", 280 "vmulwev_w_hu_h", "vmulwod_w_hu_h"] in 281 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 282 [llvm_v8i16_ty, llvm_v8i16_ty], 283 [IntrNoMem]>; 284 285foreach inst = ["vhaddw_d_w", "vhaddw_du_wu", "vhsubw_d_w", "vhsubw_du_wu", 286 "vaddwev_d_w", "vaddwod_d_w", "vsubwev_d_w", "vsubwod_d_w", 287 "vaddwev_d_wu", "vaddwod_d_wu", "vsubwev_d_wu", "vsubwod_d_wu", 288 "vaddwev_d_wu_w", "vaddwod_d_wu_w", 289 "vmulwev_d_w", "vmulwod_d_w", "vmulwev_d_wu", "vmulwod_d_wu", 290 "vmulwev_d_wu_w", "vmulwod_d_wu_w"] in 291 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], 292 [llvm_v4i32_ty, llvm_v4i32_ty], 293 [IntrNoMem]>; 294 295foreach inst = ["vsrln_b_h", "vsran_b_h", "vsrlrn_b_h", "vsrarn_b_h", 296 "vssrln_b_h", "vssran_b_h", "vssrln_bu_h", "vssran_bu_h", 297 "vssrlrn_b_h", "vssrarn_b_h", "vssrlrn_bu_h", "vssrarn_bu_h"] in 298 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty], 299 [llvm_v8i16_ty, llvm_v8i16_ty], 300 [IntrNoMem]>; 301 302foreach inst = ["vsrln_h_w", "vsran_h_w", "vsrlrn_h_w", "vsrarn_h_w", 303 "vssrln_h_w", "vssran_h_w", "vssrln_hu_w", "vssran_hu_w", 304 "vssrlrn_h_w", "vssrarn_h_w", "vssrlrn_hu_w", "vssrarn_hu_w"] in 305 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 306 [llvm_v4i32_ty, llvm_v4i32_ty], 307 [IntrNoMem]>; 308 309foreach inst = ["vsrln_w_d", "vsran_w_d", "vsrlrn_w_d", "vsrarn_w_d", 310 "vssrln_w_d", "vssran_w_d", "vssrln_wu_d", "vssran_wu_d", 311 "vssrlrn_w_d", "vssrarn_w_d", "vssrlrn_wu_d", "vssrarn_wu_d"] in 312 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 313 [llvm_v2i64_ty, llvm_v2i64_ty], 314 [IntrNoMem]>; 315 316foreach inst = ["vmadd_b", "vmsub_b", "vfrstp_b", "vbitsel_v", "vshuf_b"] in 317 def int_loongarch_lsx_#inst 318 : VecInt<[llvm_v16i8_ty], 319 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], 320 [IntrNoMem]>; 321foreach inst = ["vmadd_h", "vmsub_h", "vfrstp_h", "vshuf_h"] in 322 def int_loongarch_lsx_#inst 323 : VecInt<[llvm_v8i16_ty], 324 [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], 325 [IntrNoMem]>; 326foreach inst = ["vmadd_w", "vmsub_w", "vshuf_w"] in 327 def int_loongarch_lsx_#inst 328 : VecInt<[llvm_v4i32_ty], 329 [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], 330 [IntrNoMem]>; 331foreach inst = ["vmadd_d", "vmsub_d", "vshuf_d"] in 332 def int_loongarch_lsx_#inst 333 : VecInt<[llvm_v2i64_ty], 334 [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty], 335 [IntrNoMem]>; 336 337foreach inst = ["vsrlni_b_h", "vsrani_b_h", "vsrlrni_b_h", "vsrarni_b_h", 338 "vssrlni_b_h", "vssrani_b_h", "vssrlni_bu_h", "vssrani_bu_h", 339 "vssrlrni_b_h", "vssrarni_b_h", "vssrlrni_bu_h", "vssrarni_bu_h", 340 "vfrstpi_b", "vbitseli_b", "vextrins_b"] in 341 def int_loongarch_lsx_#inst 342 : VecInt<[llvm_v16i8_ty], 343 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty], 344 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 345foreach inst = ["vsrlni_h_w", "vsrani_h_w", "vsrlrni_h_w", "vsrarni_h_w", 346 "vssrlni_h_w", "vssrani_h_w", "vssrlni_hu_w", "vssrani_hu_w", 347 "vssrlrni_h_w", "vssrarni_h_w", "vssrlrni_hu_w", "vssrarni_hu_w", 348 "vfrstpi_h", "vextrins_h"] in 349 def int_loongarch_lsx_#inst 350 : VecInt<[llvm_v8i16_ty], 351 [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty], 352 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 353foreach inst = ["vsrlni_w_d", "vsrani_w_d", "vsrlrni_w_d", "vsrarni_w_d", 354 "vssrlni_w_d", "vssrani_w_d", "vssrlni_wu_d", "vssrani_wu_d", 355 "vssrlrni_w_d", "vssrarni_w_d", "vssrlrni_wu_d", "vssrarni_wu_d", 356 "vpermi_w", "vextrins_w"] in 357 def int_loongarch_lsx_#inst 358 : VecInt<[llvm_v4i32_ty], 359 [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], 360 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 361foreach inst = ["vsrlni_d_q", "vsrani_d_q", "vsrlrni_d_q", "vsrarni_d_q", 362 "vssrlni_d_q", "vssrani_d_q", "vssrlni_du_q", "vssrani_du_q", 363 "vssrlrni_d_q", "vssrarni_d_q", "vssrlrni_du_q", "vssrarni_du_q", 364 "vshuf4i_d", "vextrins_d"] in 365 def int_loongarch_lsx_#inst 366 : VecInt<[llvm_v2i64_ty], 367 [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty], 368 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 369 370foreach inst = ["vmaddwev_h_b", "vmaddwod_h_b", "vmaddwev_h_bu", 371 "vmaddwod_h_bu", "vmaddwev_h_bu_b", "vmaddwod_h_bu_b"] in 372 def int_loongarch_lsx_#inst 373 : VecInt<[llvm_v8i16_ty], 374 [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty], 375 [IntrNoMem]>; 376foreach inst = ["vmaddwev_w_h", "vmaddwod_w_h", "vmaddwev_w_hu", 377 "vmaddwod_w_hu", "vmaddwev_w_hu_h", "vmaddwod_w_hu_h"] in 378 def int_loongarch_lsx_#inst 379 : VecInt<[llvm_v4i32_ty], 380 [llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], 381 [IntrNoMem]>; 382foreach inst = ["vmaddwev_d_w", "vmaddwod_d_w", "vmaddwev_d_wu", 383 "vmaddwod_d_wu", "vmaddwev_d_wu_w", "vmaddwod_d_wu_w"] in 384 def int_loongarch_lsx_#inst 385 : VecInt<[llvm_v2i64_ty], 386 [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty], 387 [IntrNoMem]>; 388foreach inst = ["vmaddwev_q_d", "vmaddwod_q_d", "vmaddwev_q_du", 389 "vmaddwod_q_du", "vmaddwev_q_du_d", "vmaddwod_q_du_d"] in 390 def int_loongarch_lsx_#inst 391 : VecInt<[llvm_v2i64_ty], 392 [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty], 393 [IntrNoMem]>; 394 395foreach inst = ["vsllwil_h_b", "vsllwil_hu_bu"] in 396 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 397 [llvm_v16i8_ty, llvm_i32_ty], 398 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 399foreach inst = ["vsllwil_w_h", "vsllwil_wu_hu"] in 400 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 401 [llvm_v8i16_ty, llvm_i32_ty], 402 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 403foreach inst = ["vsllwil_d_w", "vsllwil_du_wu"] in 404 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], 405 [llvm_v4i32_ty, llvm_i32_ty], 406 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 407 408foreach inst = ["vneg_b", "vmskltz_b", "vmskgez_b", "vmsknz_b", 409 "vclo_b", "vclz_b", "vpcnt_b"] in 410 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty], [llvm_v16i8_ty], 411 [IntrNoMem]>; 412foreach inst = ["vneg_h", "vmskltz_h", "vclo_h", "vclz_h", "vpcnt_h"] in 413 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], [llvm_v8i16_ty], 414 [IntrNoMem]>; 415foreach inst = ["vneg_w", "vmskltz_w", "vclo_w", "vclz_w", "vpcnt_w"] in 416 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], [llvm_v4i32_ty], 417 [IntrNoMem]>; 418foreach inst = ["vneg_d", "vexth_q_d", "vexth_qu_du", "vmskltz_d", 419 "vextl_q_d", "vextl_qu_du", "vclo_d", "vclz_d", "vpcnt_d"] in 420 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v2i64_ty], 421 [IntrNoMem]>; 422 423foreach inst = ["vexth_h_b", "vexth_hu_bu"] in 424 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], [llvm_v16i8_ty], 425 [IntrNoMem]>; 426foreach inst = ["vexth_w_h", "vexth_wu_hu"] in 427 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], [llvm_v8i16_ty], 428 [IntrNoMem]>; 429foreach inst = ["vexth_d_w", "vexth_du_wu"] in 430 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v4i32_ty], 431 [IntrNoMem]>; 432 433def int_loongarch_lsx_vldi : VecInt<[llvm_v2i64_ty], [llvm_i32_ty], 434 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 435def int_loongarch_lsx_vrepli_b : VecInt<[llvm_v16i8_ty], [llvm_i32_ty], 436 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 437def int_loongarch_lsx_vrepli_h : VecInt<[llvm_v8i16_ty], [llvm_i32_ty], 438 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 439def int_loongarch_lsx_vrepli_w : VecInt<[llvm_v4i32_ty], [llvm_i32_ty], 440 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 441def int_loongarch_lsx_vrepli_d : VecInt<[llvm_v2i64_ty], [llvm_i32_ty], 442 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 443 444def int_loongarch_lsx_vreplgr2vr_b : VecInt<[llvm_v16i8_ty], [llvm_i32_ty], 445 [IntrNoMem]>; 446def int_loongarch_lsx_vreplgr2vr_h : VecInt<[llvm_v8i16_ty], [llvm_i32_ty], 447 [IntrNoMem]>; 448def int_loongarch_lsx_vreplgr2vr_w : VecInt<[llvm_v4i32_ty], [llvm_i32_ty], 449 [IntrNoMem]>; 450def int_loongarch_lsx_vreplgr2vr_d : VecInt<[llvm_v2i64_ty], [llvm_i64_ty], 451 [IntrNoMem]>; 452 453def int_loongarch_lsx_vinsgr2vr_b 454 : VecInt<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], 455 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 456def int_loongarch_lsx_vinsgr2vr_h 457 : VecInt<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty, llvm_i32_ty], 458 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 459def int_loongarch_lsx_vinsgr2vr_w 460 : VecInt<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty], 461 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 462def int_loongarch_lsx_vinsgr2vr_d 463 : VecInt<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i64_ty, llvm_i32_ty], 464 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 465 466def int_loongarch_lsx_vreplve_b 467 : VecInt<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>; 468def int_loongarch_lsx_vreplve_h 469 : VecInt<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>; 470def int_loongarch_lsx_vreplve_w 471 : VecInt<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>; 472def int_loongarch_lsx_vreplve_d 473 : VecInt<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; 474 475foreach inst = ["vpickve2gr_b", "vpickve2gr_bu" ] in 476 def int_loongarch_lsx_#inst : VecInt<[llvm_i32_ty], 477 [llvm_v16i8_ty, llvm_i32_ty], 478 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 479foreach inst = ["vpickve2gr_h", "vpickve2gr_hu" ] in 480 def int_loongarch_lsx_#inst : VecInt<[llvm_i32_ty], 481 [llvm_v8i16_ty, llvm_i32_ty], 482 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 483foreach inst = ["vpickve2gr_w", "vpickve2gr_wu" ] in 484 def int_loongarch_lsx_#inst : VecInt<[llvm_i32_ty], 485 [llvm_v4i32_ty, llvm_i32_ty], 486 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 487foreach inst = ["vpickve2gr_d", "vpickve2gr_du" ] in 488 def int_loongarch_lsx_#inst : VecInt<[llvm_i64_ty], 489 [llvm_v2i64_ty, llvm_i32_ty], 490 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 491 492def int_loongarch_lsx_bz_b : VecInt<[llvm_i32_ty], [llvm_v16i8_ty], 493 [IntrNoMem]>; 494def int_loongarch_lsx_bz_h : VecInt<[llvm_i32_ty], [llvm_v8i16_ty], 495 [IntrNoMem]>; 496def int_loongarch_lsx_bz_w : VecInt<[llvm_i32_ty], [llvm_v4i32_ty], 497 [IntrNoMem]>; 498def int_loongarch_lsx_bz_d : VecInt<[llvm_i32_ty], [llvm_v2i64_ty], 499 [IntrNoMem]>; 500def int_loongarch_lsx_bz_v : VecInt<[llvm_i32_ty], [llvm_v16i8_ty], 501 [IntrNoMem]>; 502 503def int_loongarch_lsx_bnz_v : VecInt<[llvm_i32_ty], [llvm_v16i8_ty], 504 [IntrNoMem]>; 505def int_loongarch_lsx_bnz_b : VecInt<[llvm_i32_ty], [llvm_v16i8_ty], 506 [IntrNoMem]>; 507def int_loongarch_lsx_bnz_h : VecInt<[llvm_i32_ty], [llvm_v8i16_ty], 508 [IntrNoMem]>; 509def int_loongarch_lsx_bnz_w : VecInt<[llvm_i32_ty], [llvm_v4i32_ty], 510 [IntrNoMem]>; 511def int_loongarch_lsx_bnz_d : VecInt<[llvm_i32_ty], [llvm_v2i64_ty], 512 [IntrNoMem]>; 513 514// LSX Float 515 516foreach inst = ["vfadd_s", "vfsub_s", "vfmul_s", "vfdiv_s", 517 "vfmax_s", "vfmin_s", "vfmaxa_s", "vfmina_s"] in 518 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], 519 [llvm_v4f32_ty, llvm_v4f32_ty], 520 [IntrNoMem]>; 521foreach inst = ["vfadd_d", "vfsub_d", "vfmul_d", "vfdiv_d", 522 "vfmax_d", "vfmin_d", "vfmaxa_d", "vfmina_d"] in 523 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], 524 [llvm_v2f64_ty, llvm_v2f64_ty], 525 [IntrNoMem]>; 526 527foreach inst = ["vfmadd_s", "vfmsub_s", "vfnmadd_s", "vfnmsub_s"] in 528 def int_loongarch_lsx_#inst 529 : VecInt<[llvm_v4f32_ty], 530 [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], 531 [IntrNoMem]>; 532foreach inst = ["vfmadd_d", "vfmsub_d", "vfnmadd_d", "vfnmsub_d"] in 533 def int_loongarch_lsx_#inst 534 : VecInt<[llvm_v2f64_ty], 535 [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], 536 [IntrNoMem]>; 537 538foreach inst = ["vflogb_s", "vfsqrt_s", "vfrecip_s", "vfrsqrt_s", "vfrint_s", 539 "vfrecipe_s", "vfrsqrte_s", 540 "vfrintrne_s", "vfrintrz_s", "vfrintrp_s", "vfrintrm_s"] in 541 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], [llvm_v4f32_ty], 542 [IntrNoMem]>; 543foreach inst = ["vflogb_d", "vfsqrt_d", "vfrecip_d", "vfrsqrt_d", "vfrint_d", 544 "vfrecipe_d", "vfrsqrte_d", 545 "vfrintrne_d", "vfrintrz_d", "vfrintrp_d", "vfrintrm_d"] in 546 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v2f64_ty], 547 [IntrNoMem]>; 548 549foreach inst = ["vfcvtl_s_h", "vfcvth_s_h"] in 550 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], [llvm_v8i16_ty], 551 [IntrNoMem]>; 552foreach inst = ["vfcvtl_d_s", "vfcvth_d_s"] in 553 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v4f32_ty], 554 [IntrNoMem]>; 555 556foreach inst = ["vftintrne_w_s", "vftintrz_w_s", "vftintrp_w_s", "vftintrm_w_s", 557 "vftint_w_s", "vftintrz_wu_s", "vftint_wu_s", "vfclass_s"] in 558 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], [llvm_v4f32_ty], 559 [IntrNoMem]>; 560foreach inst = ["vftintrne_l_d", "vftintrz_l_d", "vftintrp_l_d", "vftintrm_l_d", 561 "vftint_l_d", "vftintrz_lu_d", "vftint_lu_d", "vfclass_d"] in 562 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v2f64_ty], 563 [IntrNoMem]>; 564 565foreach inst = ["vftintrnel_l_s", "vftintrneh_l_s", "vftintrzl_l_s", 566 "vftintrzh_l_s", "vftintrpl_l_s", "vftintrph_l_s", 567 "vftintrml_l_s", "vftintrmh_l_s", "vftintl_l_s", 568 "vftinth_l_s"] in 569 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v4f32_ty], 570 [IntrNoMem]>; 571 572foreach inst = ["vffint_s_w", "vffint_s_wu"] in 573 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], [llvm_v4i32_ty], 574 [IntrNoMem]>; 575foreach inst = ["vffint_d_l", "vffint_d_lu"] in 576 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v2i64_ty], 577 [IntrNoMem]>; 578 579foreach inst = ["vffintl_d_w", "vffinth_d_w"] in 580 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v4i32_ty], 581 [IntrNoMem]>; 582 583foreach inst = ["vffint_s_l"] in 584 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], 585 [llvm_v2i64_ty, llvm_v2i64_ty], 586 [IntrNoMem]>; 587foreach inst = ["vftintrne_w_d", "vftintrz_w_d", "vftintrp_w_d", "vftintrm_w_d", 588 "vftint_w_d"] in 589 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 590 [llvm_v2f64_ty, llvm_v2f64_ty], 591 [IntrNoMem]>; 592 593foreach inst = ["vfcvt_h_s"] in 594 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 595 [llvm_v4f32_ty, llvm_v4f32_ty], 596 [IntrNoMem]>; 597foreach inst = ["vfcvt_s_d"] in 598 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], 599 [llvm_v2f64_ty, llvm_v2f64_ty], 600 [IntrNoMem]>; 601 602foreach inst = ["vfcmp_caf_s", "vfcmp_cun_s", "vfcmp_ceq_s", "vfcmp_cueq_s", 603 "vfcmp_clt_s", "vfcmp_cult_s", "vfcmp_cle_s", "vfcmp_cule_s", 604 "vfcmp_cne_s", "vfcmp_cor_s", "vfcmp_cune_s", 605 "vfcmp_saf_s", "vfcmp_sun_s", "vfcmp_seq_s", "vfcmp_sueq_s", 606 "vfcmp_slt_s", "vfcmp_sult_s", "vfcmp_sle_s", "vfcmp_sule_s", 607 "vfcmp_sne_s", "vfcmp_sor_s", "vfcmp_sune_s"] in 608 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 609 [llvm_v4f32_ty, llvm_v4f32_ty], 610 [IntrNoMem]>; 611foreach inst = ["vfcmp_caf_d", "vfcmp_cun_d", "vfcmp_ceq_d", "vfcmp_cueq_d", 612 "vfcmp_clt_d", "vfcmp_cult_d", "vfcmp_cle_d", "vfcmp_cule_d", 613 "vfcmp_cne_d", "vfcmp_cor_d", "vfcmp_cune_d", 614 "vfcmp_saf_d", "vfcmp_sun_d", "vfcmp_seq_d", "vfcmp_sueq_d", 615 "vfcmp_slt_d", "vfcmp_sult_d", "vfcmp_sle_d", "vfcmp_sule_d", 616 "vfcmp_sne_d", "vfcmp_sor_d", "vfcmp_sune_d"] in 617 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], 618 [llvm_v2f64_ty, llvm_v2f64_ty], 619 [IntrNoMem]>; 620 621// LSX load/store 622def int_loongarch_lsx_vld 623 : VecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty], 624 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 625def int_loongarch_lsx_vldx 626 : VecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i64_ty], 627 [IntrReadMem, IntrArgMemOnly]>; 628def int_loongarch_lsx_vldrepl_b 629 : VecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty], 630 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 631def int_loongarch_lsx_vldrepl_h 632 : VecInt<[llvm_v8i16_ty], [llvm_ptr_ty, llvm_i32_ty], 633 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 634def int_loongarch_lsx_vldrepl_w 635 : VecInt<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty], 636 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 637def int_loongarch_lsx_vldrepl_d 638 : VecInt<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_i32_ty], 639 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 640 641def int_loongarch_lsx_vst 642 : VecInt<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i32_ty], 643 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>]>; 644def int_loongarch_lsx_vstx 645 : VecInt<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i64_ty], 646 [IntrWriteMem, IntrArgMemOnly]>; 647def int_loongarch_lsx_vstelm_b 648 : VecInt<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 649 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 650def int_loongarch_lsx_vstelm_h 651 : VecInt<[], [llvm_v8i16_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 652 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 653def int_loongarch_lsx_vstelm_w 654 : VecInt<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 655 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 656def int_loongarch_lsx_vstelm_d 657 : VecInt<[], [llvm_v2i64_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 658 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 659 660} // TargetPrefix = "loongarch" 661 662//===----------------------------------------------------------------------===// 663// LASX 664 665let TargetPrefix = "loongarch" in { 666foreach inst = ["xvadd_b", "xvsub_b", 667 "xvsadd_b", "xvsadd_bu", "xvssub_b", "xvssub_bu", 668 "xvavg_b", "xvavg_bu", "xvavgr_b", "xvavgr_bu", 669 "xvabsd_b", "xvabsd_bu", "xvadda_b", 670 "xvmax_b", "xvmax_bu", "xvmin_b", "xvmin_bu", 671 "xvmul_b", "xvmuh_b", "xvmuh_bu", 672 "xvdiv_b", "xvdiv_bu", "xvmod_b", "xvmod_bu", "xvsigncov_b", 673 "xvand_v", "xvor_v", "xvxor_v", "xvnor_v", "xvandn_v", "xvorn_v", 674 "xvsll_b", "xvsrl_b", "xvsra_b", "xvrotr_b", "xvsrlr_b", "xvsrar_b", 675 "xvbitclr_b", "xvbitset_b", "xvbitrev_b", 676 "xvseq_b", "xvsle_b", "xvsle_bu", "xvslt_b", "xvslt_bu", 677 "xvpackev_b", "xvpackod_b", "xvpickev_b", "xvpickod_b", 678 "xvilvl_b", "xvilvh_b"] in 679 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty], 680 [llvm_v32i8_ty, llvm_v32i8_ty], 681 [IntrNoMem]>; 682 683foreach inst = ["xvadd_h", "xvsub_h", 684 "xvsadd_h", "xvsadd_hu", "xvssub_h", "xvssub_hu", 685 "xvavg_h", "xvavg_hu", "xvavgr_h", "xvavgr_hu", 686 "xvabsd_h", "xvabsd_hu", "xvadda_h", 687 "xvmax_h", "xvmax_hu", "xvmin_h", "xvmin_hu", 688 "xvmul_h", "xvmuh_h", "xvmuh_hu", 689 "xvdiv_h", "xvdiv_hu", "xvmod_h", "xvmod_hu", "xvsigncov_h", 690 "xvsll_h", "xvsrl_h", "xvsra_h", "xvrotr_h", "xvsrlr_h", "xvsrar_h", 691 "xvbitclr_h", "xvbitset_h", "xvbitrev_h", 692 "xvseq_h", "xvsle_h", "xvsle_hu", "xvslt_h", "xvslt_hu", 693 "xvpackev_h", "xvpackod_h", "xvpickev_h", "xvpickod_h", 694 "xvilvl_h", "xvilvh_h"] in 695 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 696 [llvm_v16i16_ty, llvm_v16i16_ty], 697 [IntrNoMem]>; 698 699foreach inst = ["xvadd_w", "xvsub_w", 700 "xvsadd_w", "xvsadd_wu", "xvssub_w", "xvssub_wu", 701 "xvavg_w", "xvavg_wu", "xvavgr_w", "xvavgr_wu", 702 "xvabsd_w", "xvabsd_wu", "xvadda_w", 703 "xvmax_w", "xvmax_wu", "xvmin_w", "xvmin_wu", 704 "xvmul_w", "xvmuh_w", "xvmuh_wu", 705 "xvdiv_w", "xvdiv_wu", "xvmod_w", "xvmod_wu", "xvsigncov_w", 706 "xvsll_w", "xvsrl_w", "xvsra_w", "xvrotr_w", "xvsrlr_w", "xvsrar_w", 707 "xvbitclr_w", "xvbitset_w", "xvbitrev_w", 708 "xvseq_w", "xvsle_w", "xvsle_wu", "xvslt_w", "xvslt_wu", 709 "xvpackev_w", "xvpackod_w", "xvpickev_w", "xvpickod_w", 710 "xvilvl_w", "xvilvh_w", "xvperm_w"] in 711 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 712 [llvm_v8i32_ty, llvm_v8i32_ty], 713 [IntrNoMem]>; 714 715foreach inst = ["xvadd_d", "xvadd_q", "xvsub_d", "xvsub_q", 716 "xvsadd_d", "xvsadd_du", "xvssub_d", "xvssub_du", 717 "xvhaddw_q_d", "xvhaddw_qu_du", "xvhsubw_q_d", "xvhsubw_qu_du", 718 "xvaddwev_q_d", "xvaddwod_q_d", "xvsubwev_q_d", "xvsubwod_q_d", 719 "xvaddwev_q_du", "xvaddwod_q_du", "xvsubwev_q_du", "xvsubwod_q_du", 720 "xvaddwev_q_du_d", "xvaddwod_q_du_d", 721 "xvavg_d", "xvavg_du", "xvavgr_d", "xvavgr_du", 722 "xvabsd_d", "xvabsd_du", "xvadda_d", 723 "xvmax_d", "xvmax_du", "xvmin_d", "xvmin_du", 724 "xvmul_d", "xvmuh_d", "xvmuh_du", 725 "xvmulwev_q_d", "xvmulwod_q_d", "xvmulwev_q_du", "xvmulwod_q_du", 726 "xvmulwev_q_du_d", "xvmulwod_q_du_d", 727 "xvdiv_d", "xvdiv_du", "xvmod_d", "xvmod_du", "xvsigncov_d", 728 "xvsll_d", "xvsrl_d", "xvsra_d", "xvrotr_d", "xvsrlr_d", "xvsrar_d", 729 "xvbitclr_d", "xvbitset_d", "xvbitrev_d", 730 "xvseq_d", "xvsle_d", "xvsle_du", "xvslt_d", "xvslt_du", 731 "xvpackev_d", "xvpackod_d", "xvpickev_d", "xvpickod_d", 732 "xvilvl_d", "xvilvh_d"] in 733 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], 734 [llvm_v4i64_ty, llvm_v4i64_ty], 735 [IntrNoMem]>; 736 737foreach inst = ["xvaddi_bu", "xvsubi_bu", 738 "xvmaxi_b", "xvmaxi_bu", "xvmini_b", "xvmini_bu", 739 "xvsat_b", "xvsat_bu", 740 "xvandi_b", "xvori_b", "xvxori_b", "xvnori_b", 741 "xvslli_b", "xvsrli_b", "xvsrai_b", "xvrotri_b", 742 "xvsrlri_b", "xvsrari_b", 743 "xvbitclri_b", "xvbitseti_b", "xvbitrevi_b", 744 "xvseqi_b", "xvslei_b", "xvslei_bu", "xvslti_b", "xvslti_bu", 745 "xvrepl128vei_b", "xvbsll_v", "xvbsrl_v", "xvshuf4i_b"] in 746 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty], 747 [llvm_v32i8_ty, llvm_i32_ty], 748 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 749foreach inst = ["xvaddi_hu", "xvsubi_hu", 750 "xvmaxi_h", "xvmaxi_hu", "xvmini_h", "xvmini_hu", 751 "xvsat_h", "xvsat_hu", 752 "xvslli_h", "xvsrli_h", "xvsrai_h", "xvrotri_h", 753 "xvsrlri_h", "xvsrari_h", 754 "xvbitclri_h", "xvbitseti_h", "xvbitrevi_h", 755 "xvseqi_h", "xvslei_h", "xvslei_hu", "xvslti_h", "xvslti_hu", 756 "xvrepl128vei_h", "xvshuf4i_h"] in 757 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 758 [llvm_v16i16_ty, llvm_i32_ty], 759 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 760foreach inst = ["xvaddi_wu", "xvsubi_wu", 761 "xvmaxi_w", "xvmaxi_wu", "xvmini_w", "xvmini_wu", 762 "xvsat_w", "xvsat_wu", 763 "xvslli_w", "xvsrli_w", "xvsrai_w", "xvrotri_w", 764 "xvsrlri_w", "xvsrari_w", 765 "xvbitclri_w", "xvbitseti_w", "xvbitrevi_w", 766 "xvseqi_w", "xvslei_w", "xvslei_wu", "xvslti_w", "xvslti_wu", 767 "xvrepl128vei_w", "xvshuf4i_w", "xvpickve_w"] in 768 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 769 [llvm_v8i32_ty, llvm_i32_ty], 770 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 771foreach inst = ["xvaddi_du", "xvsubi_du", 772 "xvmaxi_d", "xvmaxi_du", "xvmini_d", "xvmini_du", 773 "xvsat_d", "xvsat_du", 774 "xvslli_d", "xvsrli_d", "xvsrai_d", "xvrotri_d", 775 "xvsrlri_d", "xvsrari_d", 776 "xvbitclri_d", "xvbitseti_d", "xvbitrevi_d", 777 "xvseqi_d", "xvslei_d", "xvslei_du", "xvslti_d", "xvslti_du", 778 "xvrepl128vei_d", "xvpermi_d", "xvpickve_d"] in 779 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], 780 [llvm_v4i64_ty, llvm_i32_ty], 781 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 782 783foreach inst = ["xvhaddw_h_b", "xvhaddw_hu_bu", "xvhsubw_h_b", "xvhsubw_hu_bu", 784 "xvaddwev_h_b", "xvaddwod_h_b", "xvsubwev_h_b", "xvsubwod_h_b", 785 "xvaddwev_h_bu", "xvaddwod_h_bu", "xvsubwev_h_bu", "xvsubwod_h_bu", 786 "xvaddwev_h_bu_b", "xvaddwod_h_bu_b", 787 "xvmulwev_h_b", "xvmulwod_h_b", "xvmulwev_h_bu", "xvmulwod_h_bu", 788 "xvmulwev_h_bu_b", "xvmulwod_h_bu_b"] in 789 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 790 [llvm_v32i8_ty, llvm_v32i8_ty], 791 [IntrNoMem]>; 792 793foreach inst = ["xvhaddw_w_h", "xvhaddw_wu_hu", "xvhsubw_w_h", "xvhsubw_wu_hu", 794 "xvaddwev_w_h", "xvaddwod_w_h", "xvsubwev_w_h", "xvsubwod_w_h", 795 "xvaddwev_w_hu", "xvaddwod_w_hu", "xvsubwev_w_hu", "xvsubwod_w_hu", 796 "xvaddwev_w_hu_h", "xvaddwod_w_hu_h", 797 "xvmulwev_w_h", "xvmulwod_w_h", "xvmulwev_w_hu", "xvmulwod_w_hu", 798 "xvmulwev_w_hu_h", "xvmulwod_w_hu_h"] in 799 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 800 [llvm_v16i16_ty, llvm_v16i16_ty], 801 [IntrNoMem]>; 802 803foreach inst = ["xvhaddw_d_w", "xvhaddw_du_wu", "xvhsubw_d_w", "xvhsubw_du_wu", 804 "xvaddwev_d_w", "xvaddwod_d_w", "xvsubwev_d_w", "xvsubwod_d_w", 805 "xvaddwev_d_wu", "xvaddwod_d_wu", "xvsubwev_d_wu", "xvsubwod_d_wu", 806 "xvaddwev_d_wu_w", "xvaddwod_d_wu_w", 807 "xvmulwev_d_w", "xvmulwod_d_w", "xvmulwev_d_wu", "xvmulwod_d_wu", 808 "xvmulwev_d_wu_w", "xvmulwod_d_wu_w"] in 809 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], 810 [llvm_v8i32_ty, llvm_v8i32_ty], 811 [IntrNoMem]>; 812 813foreach inst = ["xvsrln_b_h", "xvsran_b_h", "xvsrlrn_b_h", "xvsrarn_b_h", 814 "xvssrln_b_h", "xvssran_b_h", "xvssrln_bu_h", "xvssran_bu_h", 815 "xvssrlrn_b_h", "xvssrarn_b_h", "xvssrlrn_bu_h", "xvssrarn_bu_h"] in 816 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty], 817 [llvm_v16i16_ty, llvm_v16i16_ty], 818 [IntrNoMem]>; 819 820foreach inst = ["xvsrln_h_w", "xvsran_h_w", "xvsrlrn_h_w", "xvsrarn_h_w", 821 "xvssrln_h_w", "xvssran_h_w", "xvssrln_hu_w", "xvssran_hu_w", 822 "xvssrlrn_h_w", "xvssrarn_h_w", "xvssrlrn_hu_w", "xvssrarn_hu_w"] in 823 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 824 [llvm_v8i32_ty, llvm_v8i32_ty], 825 [IntrNoMem]>; 826 827foreach inst = ["xvsrln_w_d", "xvsran_w_d", "xvsrlrn_w_d", "xvsrarn_w_d", 828 "xvssrln_w_d", "xvssran_w_d", "xvssrln_wu_d", "xvssran_wu_d", 829 "xvssrlrn_w_d", "xvssrarn_w_d", "xvssrlrn_wu_d", "xvssrarn_wu_d"] in 830 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 831 [llvm_v4i64_ty, llvm_v4i64_ty], 832 [IntrNoMem]>; 833 834foreach inst = ["xvmadd_b", "xvmsub_b", "xvfrstp_b", "xvbitsel_v", "xvshuf_b"] in 835 def int_loongarch_lasx_#inst 836 : VecInt<[llvm_v32i8_ty], 837 [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty], 838 [IntrNoMem]>; 839foreach inst = ["xvmadd_h", "xvmsub_h", "xvfrstp_h", "xvshuf_h"] in 840 def int_loongarch_lasx_#inst 841 : VecInt<[llvm_v16i16_ty], 842 [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty], 843 [IntrNoMem]>; 844foreach inst = ["xvmadd_w", "xvmsub_w", "xvshuf_w"] in 845 def int_loongarch_lasx_#inst 846 : VecInt<[llvm_v8i32_ty], 847 [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty], 848 [IntrNoMem]>; 849foreach inst = ["xvmadd_d", "xvmsub_d", "xvshuf_d"] in 850 def int_loongarch_lasx_#inst 851 : VecInt<[llvm_v4i64_ty], 852 [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty], 853 [IntrNoMem]>; 854 855foreach inst = ["xvsrlni_b_h", "xvsrani_b_h", "xvsrlrni_b_h", "xvsrarni_b_h", 856 "xvssrlni_b_h", "xvssrani_b_h", "xvssrlni_bu_h", "xvssrani_bu_h", 857 "xvssrlrni_b_h", "xvssrarni_b_h", "xvssrlrni_bu_h", "xvssrarni_bu_h", 858 "xvfrstpi_b", "xvbitseli_b", "xvextrins_b", "xvpermi_q"] in 859 def int_loongarch_lasx_#inst 860 : VecInt<[llvm_v32i8_ty], 861 [llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty], 862 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 863foreach inst = ["xvsrlni_h_w", "xvsrani_h_w", "xvsrlrni_h_w", "xvsrarni_h_w", 864 "xvssrlni_h_w", "xvssrani_h_w", "xvssrlni_hu_w", "xvssrani_hu_w", 865 "xvssrlrni_h_w", "xvssrarni_h_w", "xvssrlrni_hu_w", "xvssrarni_hu_w", 866 "xvfrstpi_h", "xvextrins_h"] in 867 def int_loongarch_lasx_#inst 868 : VecInt<[llvm_v16i16_ty], 869 [llvm_v16i16_ty, llvm_v16i16_ty, llvm_i32_ty], 870 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 871foreach inst = ["xvsrlni_w_d", "xvsrani_w_d", "xvsrlrni_w_d", "xvsrarni_w_d", 872 "xvssrlni_w_d", "xvssrani_w_d", "xvssrlni_wu_d", "xvssrani_wu_d", 873 "xvssrlrni_w_d", "xvssrarni_w_d", "xvssrlrni_wu_d", "xvssrarni_wu_d", 874 "xvpermi_w", "xvextrins_w", "xvinsve0_w"] in 875 def int_loongarch_lasx_#inst 876 : VecInt<[llvm_v8i32_ty], 877 [llvm_v8i32_ty, llvm_v8i32_ty, llvm_i32_ty], 878 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 879foreach inst = ["xvsrlni_d_q", "xvsrani_d_q", "xvsrlrni_d_q", "xvsrarni_d_q", 880 "xvssrlni_d_q", "xvssrani_d_q", "xvssrlni_du_q", "xvssrani_du_q", 881 "xvssrlrni_d_q", "xvssrarni_d_q", "xvssrlrni_du_q", "xvssrarni_du_q", 882 "xvshuf4i_d", "xvextrins_d", "xvinsve0_d"] in 883 def int_loongarch_lasx_#inst 884 : VecInt<[llvm_v4i64_ty], 885 [llvm_v4i64_ty, llvm_v4i64_ty, llvm_i32_ty], 886 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 887 888foreach inst = ["xvmaddwev_h_b", "xvmaddwod_h_b", "xvmaddwev_h_bu", 889 "xvmaddwod_h_bu", "xvmaddwev_h_bu_b", "xvmaddwod_h_bu_b"] in 890 def int_loongarch_lasx_#inst 891 : VecInt<[llvm_v16i16_ty], 892 [llvm_v16i16_ty, llvm_v32i8_ty, llvm_v32i8_ty], 893 [IntrNoMem]>; 894foreach inst = ["xvmaddwev_w_h", "xvmaddwod_w_h", "xvmaddwev_w_hu", 895 "xvmaddwod_w_hu", "xvmaddwev_w_hu_h", "xvmaddwod_w_hu_h"] in 896 def int_loongarch_lasx_#inst 897 : VecInt<[llvm_v8i32_ty], 898 [llvm_v8i32_ty, llvm_v16i16_ty, llvm_v16i16_ty], 899 [IntrNoMem]>; 900foreach inst = ["xvmaddwev_d_w", "xvmaddwod_d_w", "xvmaddwev_d_wu", 901 "xvmaddwod_d_wu", "xvmaddwev_d_wu_w", "xvmaddwod_d_wu_w"] in 902 def int_loongarch_lasx_#inst 903 : VecInt<[llvm_v4i64_ty], 904 [llvm_v4i64_ty, llvm_v8i32_ty, llvm_v8i32_ty], 905 [IntrNoMem]>; 906foreach inst = ["xvmaddwev_q_d", "xvmaddwod_q_d", "xvmaddwev_q_du", 907 "xvmaddwod_q_du", "xvmaddwev_q_du_d", "xvmaddwod_q_du_d"] in 908 def int_loongarch_lasx_#inst 909 : VecInt<[llvm_v4i64_ty], 910 [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty], 911 [IntrNoMem]>; 912 913foreach inst = ["xvsllwil_h_b", "xvsllwil_hu_bu"] in 914 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 915 [llvm_v32i8_ty, llvm_i32_ty], 916 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 917foreach inst = ["xvsllwil_w_h", "xvsllwil_wu_hu"] in 918 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 919 [llvm_v16i16_ty, llvm_i32_ty], 920 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 921foreach inst = ["xvsllwil_d_w", "xvsllwil_du_wu"] in 922 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], 923 [llvm_v8i32_ty, llvm_i32_ty], 924 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 925 926foreach inst = ["xvneg_b", "xvmskltz_b", "xvmskgez_b", "xvmsknz_b", 927 "xvclo_b", "xvclz_b", "xvpcnt_b", 928 "xvreplve0_b", "xvreplve0_q"] in 929 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty], [llvm_v32i8_ty], 930 [IntrNoMem]>; 931foreach inst = ["xvneg_h", "xvmskltz_h", "xvclo_h", "xvclz_h", "xvpcnt_h", 932 "xvreplve0_h"] in 933 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], [llvm_v16i16_ty], 934 [IntrNoMem]>; 935foreach inst = ["xvneg_w", "xvmskltz_w", "xvclo_w", "xvclz_w", "xvpcnt_w", 936 "xvreplve0_w"] in 937 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v8i32_ty], 938 [IntrNoMem]>; 939foreach inst = ["xvneg_d", "xvexth_q_d", "xvexth_qu_du", "xvmskltz_d", 940 "xvextl_q_d", "xvextl_qu_du", "xvclo_d", "xvclz_d", "xvpcnt_d", 941 "xvreplve0_d"] in 942 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v4i64_ty], 943 [IntrNoMem]>; 944 945foreach inst = ["xvexth_h_b", "xvexth_hu_bu", "vext2xv_h_b", "vext2xv_hu_bu"] in 946 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], [llvm_v32i8_ty], 947 [IntrNoMem]>; 948foreach inst = ["xvexth_w_h", "xvexth_wu_hu", "vext2xv_w_h", "vext2xv_wu_hu"] in 949 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v16i16_ty], 950 [IntrNoMem]>; 951foreach inst = ["xvexth_d_w", "xvexth_du_wu", "vext2xv_d_w", "vext2xv_du_wu"] in 952 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v8i32_ty], 953 [IntrNoMem]>; 954 955foreach inst = ["vext2xv_w_b", "vext2xv_wu_bu"] in 956 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v32i8_ty], 957 [IntrNoMem]>; 958foreach inst = ["vext2xv_d_h", "vext2xv_du_hu"] in 959 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v16i16_ty], 960 [IntrNoMem]>; 961 962foreach inst = ["vext2xv_d_b", "vext2xv_du_bu"] in 963 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v32i8_ty], 964 [IntrNoMem]>; 965 966def int_loongarch_lasx_xvldi : VecInt<[llvm_v4i64_ty], [llvm_i32_ty], 967 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 968def int_loongarch_lasx_xvrepli_b : VecInt<[llvm_v32i8_ty], [llvm_i32_ty], 969 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 970def int_loongarch_lasx_xvrepli_h : VecInt<[llvm_v16i16_ty], [llvm_i32_ty], 971 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 972def int_loongarch_lasx_xvrepli_w : VecInt<[llvm_v8i32_ty], [llvm_i32_ty], 973 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 974def int_loongarch_lasx_xvrepli_d : VecInt<[llvm_v4i64_ty], [llvm_i32_ty], 975 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 976 977def int_loongarch_lasx_xvreplgr2vr_b : VecInt<[llvm_v32i8_ty], [llvm_i32_ty], 978 [IntrNoMem]>; 979def int_loongarch_lasx_xvreplgr2vr_h : VecInt<[llvm_v16i16_ty], [llvm_i32_ty], 980 [IntrNoMem]>; 981def int_loongarch_lasx_xvreplgr2vr_w : VecInt<[llvm_v8i32_ty], [llvm_i32_ty], 982 [IntrNoMem]>; 983def int_loongarch_lasx_xvreplgr2vr_d : VecInt<[llvm_v4i64_ty], [llvm_i64_ty], 984 [IntrNoMem]>; 985 986def int_loongarch_lasx_xvinsgr2vr_w 987 : VecInt<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty], 988 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 989def int_loongarch_lasx_xvinsgr2vr_d 990 : VecInt<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_i64_ty, llvm_i32_ty], 991 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 992 993def int_loongarch_lasx_xvreplve_b 994 : VecInt<[llvm_v32i8_ty], [llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>; 995def int_loongarch_lasx_xvreplve_h 996 : VecInt<[llvm_v16i16_ty], [llvm_v16i16_ty, llvm_i32_ty], [IntrNoMem]>; 997def int_loongarch_lasx_xvreplve_w 998 : VecInt<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_i32_ty], [IntrNoMem]>; 999def int_loongarch_lasx_xvreplve_d 1000 : VecInt<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_i32_ty], [IntrNoMem]>; 1001 1002foreach inst = ["xvpickve2gr_w", "xvpickve2gr_wu" ] in 1003 def int_loongarch_lasx_#inst : VecInt<[llvm_i32_ty], 1004 [llvm_v8i32_ty, llvm_i32_ty], 1005 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1006foreach inst = ["xvpickve2gr_d", "xvpickve2gr_du" ] in 1007 def int_loongarch_lasx_#inst : VecInt<[llvm_i64_ty], 1008 [llvm_v4i64_ty, llvm_i32_ty], 1009 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1010 1011def int_loongarch_lasx_xbz_b : VecInt<[llvm_i32_ty], [llvm_v32i8_ty], 1012 [IntrNoMem]>; 1013def int_loongarch_lasx_xbz_h : VecInt<[llvm_i32_ty], [llvm_v16i16_ty], 1014 [IntrNoMem]>; 1015def int_loongarch_lasx_xbz_w : VecInt<[llvm_i32_ty], [llvm_v8i32_ty], 1016 [IntrNoMem]>; 1017def int_loongarch_lasx_xbz_d : VecInt<[llvm_i32_ty], [llvm_v4i64_ty], 1018 [IntrNoMem]>; 1019def int_loongarch_lasx_xbz_v : VecInt<[llvm_i32_ty], [llvm_v32i8_ty], 1020 [IntrNoMem]>; 1021 1022def int_loongarch_lasx_xbnz_v : VecInt<[llvm_i32_ty], [llvm_v32i8_ty], 1023 [IntrNoMem]>; 1024def int_loongarch_lasx_xbnz_b : VecInt<[llvm_i32_ty], [llvm_v32i8_ty], 1025 [IntrNoMem]>; 1026def int_loongarch_lasx_xbnz_h : VecInt<[llvm_i32_ty], [llvm_v16i16_ty], 1027 [IntrNoMem]>; 1028def int_loongarch_lasx_xbnz_w : VecInt<[llvm_i32_ty], [llvm_v8i32_ty], 1029 [IntrNoMem]>; 1030def int_loongarch_lasx_xbnz_d : VecInt<[llvm_i32_ty], [llvm_v4i64_ty], 1031 [IntrNoMem]>; 1032 1033// LASX Float 1034 1035foreach inst = ["xvfadd_s", "xvfsub_s", "xvfmul_s", "xvfdiv_s", 1036 "xvfmax_s", "xvfmin_s", "xvfmaxa_s", "xvfmina_s"] in 1037 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], 1038 [llvm_v8f32_ty, llvm_v8f32_ty], 1039 [IntrNoMem]>; 1040foreach inst = ["xvfadd_d", "xvfsub_d", "xvfmul_d", "xvfdiv_d", 1041 "xvfmax_d", "xvfmin_d", "xvfmaxa_d", "xvfmina_d"] in 1042 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], 1043 [llvm_v4f64_ty, llvm_v4f64_ty], 1044 [IntrNoMem]>; 1045 1046foreach inst = ["xvfmadd_s", "xvfmsub_s", "xvfnmadd_s", "xvfnmsub_s"] in 1047 def int_loongarch_lasx_#inst 1048 : VecInt<[llvm_v8f32_ty], 1049 [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty], 1050 [IntrNoMem]>; 1051foreach inst = ["xvfmadd_d", "xvfmsub_d", "xvfnmadd_d", "xvfnmsub_d"] in 1052 def int_loongarch_lasx_#inst 1053 : VecInt<[llvm_v4f64_ty], 1054 [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty], 1055 [IntrNoMem]>; 1056 1057foreach inst = ["xvflogb_s", "xvfsqrt_s", "xvfrecip_s", "xvfrsqrt_s", "xvfrint_s", 1058 "xvfrecipe_s", "xvfrsqrte_s", 1059 "xvfrintrne_s", "xvfrintrz_s", "xvfrintrp_s", "xvfrintrm_s"] in 1060 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], [llvm_v8f32_ty], 1061 [IntrNoMem]>; 1062foreach inst = ["xvflogb_d", "xvfsqrt_d", "xvfrecip_d", "xvfrsqrt_d", "xvfrint_d", 1063 "xvfrecipe_d", "xvfrsqrte_d", 1064 "xvfrintrne_d", "xvfrintrz_d", "xvfrintrp_d", "xvfrintrm_d"] in 1065 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v4f64_ty], 1066 [IntrNoMem]>; 1067 1068foreach inst = ["xvfcvtl_s_h", "xvfcvth_s_h"] in 1069 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], [llvm_v16i16_ty], 1070 [IntrNoMem]>; 1071foreach inst = ["xvfcvtl_d_s", "xvfcvth_d_s"] in 1072 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v8f32_ty], 1073 [IntrNoMem]>; 1074 1075foreach inst = ["xvftintrne_w_s", "xvftintrz_w_s", "xvftintrp_w_s", "xvftintrm_w_s", 1076 "xvftint_w_s", "xvftintrz_wu_s", "xvftint_wu_s", "xvfclass_s"] in 1077 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v8f32_ty], 1078 [IntrNoMem]>; 1079foreach inst = ["xvftintrne_l_d", "xvftintrz_l_d", "xvftintrp_l_d", "xvftintrm_l_d", 1080 "xvftint_l_d", "xvftintrz_lu_d", "xvftint_lu_d", "xvfclass_d"] in 1081 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v4f64_ty], 1082 [IntrNoMem]>; 1083 1084foreach inst = ["xvftintrnel_l_s", "xvftintrneh_l_s", "xvftintrzl_l_s", 1085 "xvftintrzh_l_s", "xvftintrpl_l_s", "xvftintrph_l_s", 1086 "xvftintrml_l_s", "xvftintrmh_l_s", "xvftintl_l_s", 1087 "xvftinth_l_s"] in 1088 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v8f32_ty], 1089 [IntrNoMem]>; 1090 1091foreach inst = ["xvffint_s_w", "xvffint_s_wu"] in 1092 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], [llvm_v8i32_ty], 1093 [IntrNoMem]>; 1094foreach inst = ["xvffint_d_l", "xvffint_d_lu"] in 1095 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v4i64_ty], 1096 [IntrNoMem]>; 1097 1098foreach inst = ["xvffintl_d_w", "xvffinth_d_w"] in 1099 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v8i32_ty], 1100 [IntrNoMem]>; 1101 1102foreach inst = ["xvffint_s_l"] in 1103 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], 1104 [llvm_v4i64_ty, llvm_v4i64_ty], 1105 [IntrNoMem]>; 1106foreach inst = ["xvftintrne_w_d", "xvftintrz_w_d", "xvftintrp_w_d", "xvftintrm_w_d", 1107 "xvftint_w_d"] in 1108 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 1109 [llvm_v4f64_ty, llvm_v4f64_ty], 1110 [IntrNoMem]>; 1111 1112foreach inst = ["xvfcvt_h_s"] in 1113 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 1114 [llvm_v8f32_ty, llvm_v8f32_ty], 1115 [IntrNoMem]>; 1116foreach inst = ["xvfcvt_s_d"] in 1117 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], 1118 [llvm_v4f64_ty, llvm_v4f64_ty], 1119 [IntrNoMem]>; 1120 1121foreach inst = ["xvfcmp_caf_s", "xvfcmp_cun_s", "xvfcmp_ceq_s", "xvfcmp_cueq_s", 1122 "xvfcmp_clt_s", "xvfcmp_cult_s", "xvfcmp_cle_s", "xvfcmp_cule_s", 1123 "xvfcmp_cne_s", "xvfcmp_cor_s", "xvfcmp_cune_s", 1124 "xvfcmp_saf_s", "xvfcmp_sun_s", "xvfcmp_seq_s", "xvfcmp_sueq_s", 1125 "xvfcmp_slt_s", "xvfcmp_sult_s", "xvfcmp_sle_s", "xvfcmp_sule_s", 1126 "xvfcmp_sne_s", "xvfcmp_sor_s", "xvfcmp_sune_s"] in 1127 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 1128 [llvm_v8f32_ty, llvm_v8f32_ty], 1129 [IntrNoMem]>; 1130foreach inst = ["xvfcmp_caf_d", "xvfcmp_cun_d", "xvfcmp_ceq_d", "xvfcmp_cueq_d", 1131 "xvfcmp_clt_d", "xvfcmp_cult_d", "xvfcmp_cle_d", "xvfcmp_cule_d", 1132 "xvfcmp_cne_d", "xvfcmp_cor_d", "xvfcmp_cune_d", 1133 "xvfcmp_saf_d", "xvfcmp_sun_d", "xvfcmp_seq_d", "xvfcmp_sueq_d", 1134 "xvfcmp_slt_d", "xvfcmp_sult_d", "xvfcmp_sle_d", "xvfcmp_sule_d", 1135 "xvfcmp_sne_d", "xvfcmp_sor_d", "xvfcmp_sune_d"] in 1136 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], 1137 [llvm_v4f64_ty, llvm_v4f64_ty], 1138 [IntrNoMem]>; 1139 1140def int_loongarch_lasx_xvpickve_w_f 1141 : VecInt<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_i32_ty], 1142 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1143def int_loongarch_lasx_xvpickve_d_f 1144 : VecInt<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_i32_ty], 1145 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1146 1147// LASX load/store 1148def int_loongarch_lasx_xvld 1149 : VecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i32_ty], 1150 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 1151def int_loongarch_lasx_xvldx 1152 : VecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i64_ty], 1153 [IntrReadMem, IntrArgMemOnly]>; 1154def int_loongarch_lasx_xvldrepl_b 1155 : VecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i32_ty], 1156 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 1157def int_loongarch_lasx_xvldrepl_h 1158 : VecInt<[llvm_v16i16_ty], [llvm_ptr_ty, llvm_i32_ty], 1159 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 1160def int_loongarch_lasx_xvldrepl_w 1161 : VecInt<[llvm_v8i32_ty], [llvm_ptr_ty, llvm_i32_ty], 1162 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 1163def int_loongarch_lasx_xvldrepl_d 1164 : VecInt<[llvm_v4i64_ty], [llvm_ptr_ty, llvm_i32_ty], 1165 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 1166 1167def int_loongarch_lasx_xvst 1168 : VecInt<[], [llvm_v32i8_ty, llvm_ptr_ty, llvm_i32_ty], 1169 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>]>; 1170def int_loongarch_lasx_xvstx 1171 : VecInt<[], [llvm_v32i8_ty, llvm_ptr_ty, llvm_i64_ty], 1172 [IntrWriteMem, IntrArgMemOnly]>; 1173def int_loongarch_lasx_xvstelm_b 1174 : VecInt<[], [llvm_v32i8_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 1175 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1176def int_loongarch_lasx_xvstelm_h 1177 : VecInt<[], [llvm_v16i16_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 1178 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1179def int_loongarch_lasx_xvstelm_w 1180 : VecInt<[], [llvm_v8i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 1181 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1182def int_loongarch_lasx_xvstelm_d 1183 : VecInt<[], [llvm_v4i64_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 1184 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1185} // TargetPrefix = "loongarch" 1186