1//===- IntrinsicsLoongArch.td - Defines LoongArch intrinsics *- tablegen -*===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines all of the LoongArch-specific intrinsics.
10//
11//===----------------------------------------------------------------------===//
12
13let TargetPrefix = "loongarch" in {
14
15//===----------------------------------------------------------------------===//
16// Atomics
17
18// T @llvm.<name>.T.<p>(any*, T, T, T imm);
19class MaskedAtomicRMW<LLVMType itype>
20    : Intrinsic<[itype], [llvm_anyptr_ty, itype, itype, itype],
21                [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<3>>]>;
22
23// We define 32-bit and 64-bit variants of the above, where T stands for i32
24// or i64 respectively:
25multiclass MaskedAtomicRMWIntrinsics {
26  // i32 @llvm.<name>.i32.<p>(any*, i32, i32, i32 imm);
27  def _i32 : MaskedAtomicRMW<llvm_i32_ty>;
28  // i64 @llvm.<name>.i32.<p>(any*, i64, i64, i64 imm);
29  def _i64 : MaskedAtomicRMW<llvm_i64_ty>;
30}
31
32multiclass MaskedAtomicRMWFiveOpIntrinsics {
33  // TODO: Support cmpxchg on LA32.
34  // i64 @llvm.<name>.i64.<p>(any*, i64, i64, i64, i64 imm);
35  def _i64 : MaskedAtomicRMWFiveArg<llvm_i64_ty>;
36}
37
38defm int_loongarch_masked_atomicrmw_xchg : MaskedAtomicRMWIntrinsics;
39defm int_loongarch_masked_atomicrmw_add : MaskedAtomicRMWIntrinsics;
40defm int_loongarch_masked_atomicrmw_sub : MaskedAtomicRMWIntrinsics;
41defm int_loongarch_masked_atomicrmw_nand : MaskedAtomicRMWIntrinsics;
42defm int_loongarch_masked_atomicrmw_umax : MaskedAtomicRMWIntrinsics;
43defm int_loongarch_masked_atomicrmw_umin : MaskedAtomicRMWIntrinsics;
44defm int_loongarch_masked_atomicrmw_max : MaskedAtomicRMWFiveOpIntrinsics;
45defm int_loongarch_masked_atomicrmw_min : MaskedAtomicRMWFiveOpIntrinsics;
46
47// @llvm.loongarch.masked.cmpxchg.i64.<p>(
48//   ptr addr, grlen cmpval, grlen newval, grlen mask, grlenimm ordering)
49defm int_loongarch_masked_cmpxchg : MaskedAtomicRMWFiveOpIntrinsics;
50
51//===----------------------------------------------------------------------===//
52// LoongArch BASE
53
54def int_loongarch_break : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
55def int_loongarch_cacop_d : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty],
56    [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
57def int_loongarch_cacop_w : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
58    [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
59def int_loongarch_dbar : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
60def int_loongarch_ibar : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
61def int_loongarch_movfcsr2gr : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
62                               [ImmArg<ArgIndex<0>>]>;
63def int_loongarch_movgr2fcsr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty],
64                               [ImmArg<ArgIndex<0>>]>;
65def int_loongarch_syscall : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
66
67def int_loongarch_crc_w_b_w : Intrinsic<[llvm_i32_ty],
68                                        [llvm_i32_ty, llvm_i32_ty]>;
69def int_loongarch_crc_w_h_w : Intrinsic<[llvm_i32_ty],
70                                        [llvm_i32_ty, llvm_i32_ty]>;
71def int_loongarch_crc_w_w_w : Intrinsic<[llvm_i32_ty],
72                                        [llvm_i32_ty, llvm_i32_ty]>;
73def int_loongarch_crc_w_d_w : Intrinsic<[llvm_i32_ty],
74                                        [llvm_i64_ty, llvm_i32_ty]>;
75
76def int_loongarch_crcc_w_b_w : Intrinsic<[llvm_i32_ty],
77                                         [llvm_i32_ty, llvm_i32_ty]>;
78def int_loongarch_crcc_w_h_w : Intrinsic<[llvm_i32_ty],
79                                         [llvm_i32_ty, llvm_i32_ty]>;
80def int_loongarch_crcc_w_w_w : Intrinsic<[llvm_i32_ty],
81                                         [llvm_i32_ty, llvm_i32_ty]>;
82def int_loongarch_crcc_w_d_w : Intrinsic<[llvm_i32_ty],
83                                         [llvm_i64_ty, llvm_i32_ty]>;
84
85def int_loongarch_csrrd_w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
86                                      [ImmArg<ArgIndex<0>>]>;
87def int_loongarch_csrrd_d : Intrinsic<[llvm_i64_ty], [llvm_i32_ty],
88                                      [ImmArg<ArgIndex<0>>]>;
89def int_loongarch_csrwr_w : Intrinsic<[llvm_i32_ty],
90                                      [llvm_i32_ty, llvm_i32_ty],
91                                      [ImmArg<ArgIndex<1>>]>;
92def int_loongarch_csrwr_d : Intrinsic<[llvm_i64_ty],
93                                      [llvm_i64_ty, llvm_i32_ty],
94                                      [ImmArg<ArgIndex<1>>]>;
95def int_loongarch_csrxchg_w : Intrinsic<[llvm_i32_ty],
96                                        [llvm_i32_ty, llvm_i32_ty,
97                                         llvm_i32_ty],
98                                        [ImmArg<ArgIndex<2>>]>;
99def int_loongarch_csrxchg_d : Intrinsic<[llvm_i64_ty],
100                                        [llvm_i64_ty, llvm_i64_ty,
101                                         llvm_i32_ty],
102                                        [ImmArg<ArgIndex<2>>]>;
103
104def int_loongarch_iocsrrd_b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>;
105def int_loongarch_iocsrrd_h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>;
106def int_loongarch_iocsrrd_w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>;
107def int_loongarch_iocsrrd_d : Intrinsic<[llvm_i64_ty], [llvm_i32_ty]>;
108
109def int_loongarch_iocsrwr_b : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>;
110def int_loongarch_iocsrwr_h : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>;
111def int_loongarch_iocsrwr_w : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>;
112def int_loongarch_iocsrwr_d : Intrinsic<[], [llvm_i64_ty, llvm_i32_ty]>;
113
114def int_loongarch_cpucfg : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>;
115
116def int_loongarch_asrtle_d : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty]>;
117def int_loongarch_asrtgt_d : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty]>;
118
119def int_loongarch_lddir_d : Intrinsic<[llvm_i64_ty],
120                                      [llvm_i64_ty, llvm_i64_ty],
121                                      [ImmArg<ArgIndex<1>>]>;
122def int_loongarch_ldpte_d : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty],
123                                          [ImmArg<ArgIndex<1>>]>;
124} // TargetPrefix = "loongarch"
125