1//===- IntrinsicsRISCVXCV.td - CORE-V intrinsics -----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines all of the CORE-V vendor intrinsics for RISC-V. 10// 11//===----------------------------------------------------------------------===// 12 13class ScalarCoreVBitManipGprGprIntrinsic 14 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 15 [IntrNoMem, IntrSpeculatable]>; 16 17class ScalarCoreVBitManipGprIntrinsic 18 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], 19 [IntrNoMem, IntrSpeculatable]>; 20 21let TargetPrefix = "riscv" in { 22 def int_riscv_cv_bitmanip_extract : ScalarCoreVBitManipGprGprIntrinsic; 23 def int_riscv_cv_bitmanip_extractu : ScalarCoreVBitManipGprGprIntrinsic; 24 def int_riscv_cv_bitmanip_bclr : ScalarCoreVBitManipGprGprIntrinsic; 25 def int_riscv_cv_bitmanip_bset : ScalarCoreVBitManipGprGprIntrinsic; 26 27 def int_riscv_cv_bitmanip_insert 28 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 29 [IntrNoMem, IntrSpeculatable]>; 30 31 def int_riscv_cv_bitmanip_clb : ScalarCoreVBitManipGprIntrinsic; 32 33 def int_riscv_cv_bitmanip_bitrev 34 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 35 [IntrNoMem, IntrWillReturn, IntrSpeculatable, 36 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 37} // TargetPrefix = "riscv" 38