1//===- IntrinsicsRISCVXTHead.td - T-Head intrinsics --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines all of the T-Head vendor intrinsics for RISC-V. 10// 11//===----------------------------------------------------------------------===// 12 13let TargetPrefix = "riscv" in { 14 15 class TH_VdotTernaryWideMasked 16 : DefaultAttrsIntrinsic< [llvm_anyvector_ty], 17 [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty, 18 LLVMScalarOrSameVectorWidth<2, llvm_i1_ty>, 19 llvm_anyint_ty, LLVMMatchType<3>], 20 [ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic { 21 let ScalarOperand = 1; 22 let VLOperand = 4; 23 } 24 25 multiclass TH_VdotTernaryWide { 26 def "int_riscv_" # NAME : RISCVTernaryWideUnMasked; 27 def "int_riscv_" # NAME # "_mask" : TH_VdotTernaryWideMasked; 28 } 29 30 defm th_vmaqa : TH_VdotTernaryWide; 31 defm th_vmaqau : TH_VdotTernaryWide; 32 defm th_vmaqasu : TH_VdotTernaryWide; 33 defm th_vmaqaus : TH_VdotTernaryWide; 34} 35