1//===-- IR/VPIntrinsics.def - Describes llvm.vp.* Intrinsics -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains descriptions of the various Vector Predication intrinsics.
10// This is used as a central place for enumerating the different instructions
11// and should eventually be the place to put comments about the instructions.
12//
13//===----------------------------------------------------------------------===//
14
15// NOTE: NO INCLUDE GUARD DESIRED!
16
17// Provide definitions of macros so that users of this file do not have to
18// define everything to use it...
19//
20// Register a VP intrinsic and begin its property scope.
21// All VP intrinsic scopes are top level, ie it is illegal to place a
22// BEGIN_REGISTER_VP_INTRINSIC within a VP intrinsic scope.
23// \p VPID     The VP intrinsic id.
24// \p MASKPOS  The mask operand position.
25// \p EVLPOS   The explicit vector length operand position.
26#ifndef BEGIN_REGISTER_VP_INTRINSIC
27#define BEGIN_REGISTER_VP_INTRINSIC(VPID, MASKPOS, EVLPOS)
28#endif
29
30// End the property scope of a VP intrinsic.
31#ifndef END_REGISTER_VP_INTRINSIC
32#define END_REGISTER_VP_INTRINSIC(VPID)
33#endif
34
35// Register a new VP SDNode and begin its property scope.
36// When the SDNode scope is nested within a VP intrinsic scope, it is
37// implicitly registered as the canonical SDNode for this VP intrinsic. There
38// is one VP intrinsic that maps directly to one SDNode that goes by the
39// same name.  Since the operands are also the same, we open the property
40// scopes for both the VPIntrinsic and the SDNode at once.
41// \p SDOPC     The SelectionDAG Node id (eg VP_ADD).
42// \p LEGALPOS The operand position of the SDNode that is used for legalizing
43//             this SDNode. This can be `-1`, in which case the return type of
44//             the SDNode is used.
45// \p TDNAME   The name of the TableGen definition of this SDNode.
46// \p MASKPOS  The mask operand position.
47// \p EVLPOS   The explicit vector length operand position.
48#ifndef BEGIN_REGISTER_VP_SDNODE
49#define BEGIN_REGISTER_VP_SDNODE(SDOPC, LEGALPOS, TDNAME, MASKPOS, EVLPOS)
50#endif
51
52// End the property scope of a new VP SDNode.
53#ifndef END_REGISTER_VP_SDNODE
54#define END_REGISTER_VP_SDNODE(SDOPC)
55#endif
56
57// Helper macros for the common "1:1 - Intrinsic : SDNode" case.
58//
59// There is one VP intrinsic that maps directly to one SDNode that goes by the
60// same name.  Since the operands are also the same, we open the property
61// scopes for both the VPIntrinsic and the SDNode at once.
62//
63// \p INTRIN   The canonical name (eg `vp_add`, which at the same time is the
64//             name of the intrinsic and the TableGen def of the SDNode).
65// \p MASKPOS  The mask operand position.
66// \p EVLPOS   The explicit vector length operand position.
67// \p SDOPC    The SelectionDAG Node id (eg VP_ADD).
68// \p LEGALPOS The operand position of the SDNode that is used for legalizing
69//             this SDNode. This can be `-1`, in which case the return type of
70//             the SDNode is used.
71#define BEGIN_REGISTER_VP(INTRIN, MASKPOS, EVLPOS, SDOPC, LEGALPOS) \
72BEGIN_REGISTER_VP_INTRINSIC(INTRIN, MASKPOS, EVLPOS) \
73BEGIN_REGISTER_VP_SDNODE(SDOPC, LEGALPOS, INTRIN, MASKPOS, EVLPOS)
74
75#define END_REGISTER_VP(INTRIN, SDOPC) \
76END_REGISTER_VP_INTRINSIC(INTRIN) \
77END_REGISTER_VP_SDNODE(SDOPC)
78
79
80// The following macros attach properties to the scope they are placed in. This
81// assigns the property to the VP Intrinsic and/or SDNode that belongs to the
82// scope.
83//
84// Property Macros {
85
86// The intrinsic and/or SDNode has the same function as this LLVM IR Opcode.
87// \p OPC  The standard IR opcode.
88#ifndef HANDLE_VP_TO_OPC
89#define HANDLE_VP_TO_OPC(OPC)
90#endif
91
92// Whether the intrinsic may have a rounding mode or exception behavior operand
93// bundle.
94// \p HASROUND   '1' if the intrinsic can have a rounding mode operand bundle,
95//               '0' otherwise.
96// \p HASEXCEPT  '1' if the intrinsic can have an exception behavior operand
97//               bundle, '0' otherwise.
98// \p INTRINID  The constrained fp intrinsic this VP intrinsic corresponds to.
99#ifndef HANDLE_VP_TO_CONSTRAINEDFP
100#define HANDLE_VP_TO_CONSTRAINEDFP(HASROUND, HASEXCEPT, INTRINID)
101#endif
102
103// Map this VP intrinsic to its canonical functional intrinsic.
104#ifndef HANDLE_VP_TO_INTRIN
105#define HANDLE_VP_TO_INTRIN(ID)
106#endif
107
108// This VP Intrinsic is a memory operation
109// The pointer arg is at POINTERPOS and the data arg is at DATAPOS.
110#ifndef HANDLE_VP_IS_MEMOP
111#define HANDLE_VP_IS_MEMOP(VPID, POINTERPOS, DATAPOS)
112#endif
113
114/// } Property Macros
115
116///// Integer Arithmetic {
117
118// Specialized helper macro for integer binary operators (%x, %y, %mask, %evl).
119#ifdef HELPER_REGISTER_BINARY_INT_VP
120#error "The internal helper macro HELPER_REGISTER_BINARY_INT_VP is already defined!"
121#endif
122#define HELPER_REGISTER_BINARY_INT_VP(INTRIN, SDOPC, OPC) \
123BEGIN_REGISTER_VP(INTRIN, 2, 3, SDOPC, -1) \
124HANDLE_VP_TO_OPC(OPC) \
125END_REGISTER_VP(INTRIN, SDOPC)
126
127
128
129// llvm.vp.add(x,y,mask,vlen)
130HELPER_REGISTER_BINARY_INT_VP(vp_add, VP_ADD, Add)
131
132// llvm.vp.and(x,y,mask,vlen)
133HELPER_REGISTER_BINARY_INT_VP(vp_and, VP_AND, And)
134
135// llvm.vp.ashr(x,y,mask,vlen)
136HELPER_REGISTER_BINARY_INT_VP(vp_ashr, VP_ASHR, AShr)
137
138// llvm.vp.lshr(x,y,mask,vlen)
139HELPER_REGISTER_BINARY_INT_VP(vp_lshr, VP_LSHR, LShr)
140
141// llvm.vp.mul(x,y,mask,vlen)
142HELPER_REGISTER_BINARY_INT_VP(vp_mul, VP_MUL, Mul)
143
144// llvm.vp.or(x,y,mask,vlen)
145HELPER_REGISTER_BINARY_INT_VP(vp_or, VP_OR, Or)
146
147// llvm.vp.sdiv(x,y,mask,vlen)
148HELPER_REGISTER_BINARY_INT_VP(vp_sdiv, VP_SDIV, SDiv)
149
150// llvm.vp.shl(x,y,mask,vlen)
151HELPER_REGISTER_BINARY_INT_VP(vp_shl, VP_SHL, Shl)
152
153// llvm.vp.srem(x,y,mask,vlen)
154HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem)
155
156// llvm.vp.sub(x,y,mask,vlen)
157HELPER_REGISTER_BINARY_INT_VP(vp_sub, VP_SUB, Sub)
158
159// llvm.vp.udiv(x,y,mask,vlen)
160HELPER_REGISTER_BINARY_INT_VP(vp_udiv, VP_UDIV, UDiv)
161
162// llvm.vp.urem(x,y,mask,vlen)
163HELPER_REGISTER_BINARY_INT_VP(vp_urem, VP_UREM, URem)
164
165// llvm.vp.xor(x,y,mask,vlen)
166HELPER_REGISTER_BINARY_INT_VP(vp_xor, VP_XOR, Xor)
167
168#undef HELPER_REGISTER_BINARY_INT_VP
169
170///// } Integer Arithmetic
171
172///// Floating-Point Arithmetic {
173
174// Specialized helper macro for floating-point binary operators
175// <operation>(%x, %y, %mask, %evl).
176#ifdef HELPER_REGISTER_BINARY_FP_VP
177#error                                                                         \
178    "The internal helper macro HELPER_REGISTER_BINARY_FP_VP is already defined!"
179#endif
180#define HELPER_REGISTER_BINARY_FP_VP(OPSUFFIX, SDOPC, OPC)                     \
181  BEGIN_REGISTER_VP(vp_##OPSUFFIX, 2, 3, SDOPC, -1)                            \
182  HANDLE_VP_TO_OPC(OPC)                                                        \
183  HANDLE_VP_TO_CONSTRAINEDFP(1, 1, experimental_constrained_##OPSUFFIX)        \
184  END_REGISTER_VP(vp_##OPSUFFIX, SDOPC)
185
186// llvm.vp.fadd(x,y,mask,vlen)
187HELPER_REGISTER_BINARY_FP_VP(fadd, VP_FADD, FAdd)
188
189// llvm.vp.fsub(x,y,mask,vlen)
190HELPER_REGISTER_BINARY_FP_VP(fsub, VP_FSUB, FSub)
191
192// llvm.vp.fmul(x,y,mask,vlen)
193HELPER_REGISTER_BINARY_FP_VP(fmul, VP_FMUL, FMul)
194
195// llvm.vp.fdiv(x,y,mask,vlen)
196HELPER_REGISTER_BINARY_FP_VP(fdiv, VP_FDIV, FDiv)
197
198// llvm.vp.frem(x,y,mask,vlen)
199HELPER_REGISTER_BINARY_FP_VP(frem, VP_FREM, FRem)
200
201#undef HELPER_REGISTER_BINARY_FP_VP
202
203///// } Floating-Point Arithmetic
204
205///// Memory Operations {
206// llvm.vp.store(ptr,val,mask,vlen)
207BEGIN_REGISTER_VP(vp_store, 2, 3, VP_STORE, 0)
208HANDLE_VP_TO_OPC(Store)
209HANDLE_VP_TO_INTRIN(masked_store)
210HANDLE_VP_IS_MEMOP(vp_store, 1, 0)
211END_REGISTER_VP(vp_store, VP_STORE)
212
213// llvm.vp.scatter(ptr,val,mask,vlen)
214BEGIN_REGISTER_VP(vp_scatter, 2, 3, VP_SCATTER, 0)
215HANDLE_VP_TO_INTRIN(masked_scatter)
216HANDLE_VP_IS_MEMOP(vp_scatter, 1, 0)
217END_REGISTER_VP(vp_scatter, VP_SCATTER)
218
219// llvm.vp.load(ptr,mask,vlen)
220BEGIN_REGISTER_VP(vp_load, 1, 2, VP_LOAD, -1)
221HANDLE_VP_TO_OPC(Load)
222HANDLE_VP_TO_INTRIN(masked_load)
223HANDLE_VP_IS_MEMOP(vp_load, 0, None)
224END_REGISTER_VP(vp_load, VP_LOAD)
225
226// llvm.vp.gather(ptr,mask,vlen)
227BEGIN_REGISTER_VP(vp_gather, 1, 2, VP_GATHER, -1)
228HANDLE_VP_TO_INTRIN(masked_gather)
229HANDLE_VP_IS_MEMOP(vp_gather, 0, None)
230END_REGISTER_VP(vp_gather, VP_GATHER)
231
232///// } Memory Operations
233
234
235#undef BEGIN_REGISTER_VP
236#undef BEGIN_REGISTER_VP_INTRINSIC
237#undef BEGIN_REGISTER_VP_SDNODE
238#undef END_REGISTER_VP
239#undef END_REGISTER_VP_INTRINSIC
240#undef END_REGISTER_VP_SDNODE
241#undef HANDLE_VP_TO_OPC
242#undef HANDLE_VP_TO_CONSTRAINEDFP
243#undef HANDLE_VP_TO_INTRIN
244#undef HANDLE_VP_IS_MEMOP
245