1 //===- llvm/MC/MCInstrAnalysis.h - InstrDesc target hooks -------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the MCInstrAnalysis class which the MCTargetDescs can 10 // derive from to give additional information to MC. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_MC_MCINSTRANALYSIS_H 15 #define LLVM_MC_MCINSTRANALYSIS_H 16 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/Optional.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include <cstdint> 23 #include <vector> 24 25 namespace llvm { 26 27 class MCRegisterInfo; 28 class Triple; 29 30 class MCInstrAnalysis { 31 protected: 32 friend class Target; 33 34 const MCInstrInfo *Info; 35 36 public: 37 MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {} 38 virtual ~MCInstrAnalysis() = default; 39 40 virtual bool isBranch(const MCInst &Inst) const { 41 return Info->get(Inst.getOpcode()).isBranch(); 42 } 43 44 virtual bool isConditionalBranch(const MCInst &Inst) const { 45 return Info->get(Inst.getOpcode()).isConditionalBranch(); 46 } 47 48 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 49 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); 50 } 51 52 virtual bool isIndirectBranch(const MCInst &Inst) const { 53 return Info->get(Inst.getOpcode()).isIndirectBranch(); 54 } 55 56 virtual bool isCall(const MCInst &Inst) const { 57 return Info->get(Inst.getOpcode()).isCall(); 58 } 59 60 virtual bool isReturn(const MCInst &Inst) const { 61 return Info->get(Inst.getOpcode()).isReturn(); 62 } 63 64 virtual bool isTerminator(const MCInst &Inst) const { 65 return Info->get(Inst.getOpcode()).isTerminator(); 66 } 67 68 /// Returns true if at least one of the register writes performed by 69 /// \param Inst implicitly clears the upper portion of all super-registers. 70 /// 71 /// Example: on X86-64, a write to EAX implicitly clears the upper half of 72 /// RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit 73 /// instruction implicitly clears the upper portion of the correspondent 74 /// YMM register. 75 /// 76 /// This method also updates an APInt which is used as mask of register 77 /// writes. There is one bit for every explicit/implicit write performed by 78 /// the instruction. If a write implicitly clears its super-registers, then 79 /// the corresponding bit is set (vic. the corresponding bit is cleared). 80 /// 81 /// The first bits in the APint are related to explicit writes. The remaining 82 /// bits are related to implicit writes. The sequence of writes follows the 83 /// machine operand sequence. For implicit writes, the sequence is defined by 84 /// the MCInstrDesc. 85 /// 86 /// The assumption is that the bit-width of the APInt is correctly set by 87 /// the caller. The default implementation conservatively assumes that none of 88 /// the writes clears the upper portion of a super-register. 89 virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI, 90 const MCInst &Inst, 91 APInt &Writes) const; 92 93 /// Returns true if MI is a dependency breaking zero-idiom for the given 94 /// subtarget. 95 /// 96 /// Mask is used to identify input operands that have their dependency 97 /// broken. Each bit of the mask is associated with a specific input operand. 98 /// Bits associated with explicit input operands are laid out first in the 99 /// mask; implicit operands come after explicit operands. 100 /// 101 /// Dependencies are broken only for operands that have their corresponding bit 102 /// set. Operands that have their bit cleared, or that don't have a 103 /// corresponding bit in the mask don't have their dependency broken. Note 104 /// that Mask may not be big enough to describe all operands. The assumption 105 /// for operands that don't have a correspondent bit in the mask is that those 106 /// are still data dependent. 107 /// 108 /// The only exception to the rule is for when Mask has all zeroes. 109 /// A zero mask means: dependencies are broken for all explicit register 110 /// operands. 111 virtual bool isZeroIdiom(const MCInst &MI, APInt &Mask, 112 unsigned CPUID) const { 113 return false; 114 } 115 116 /// Returns true if MI is a dependency breaking instruction for the 117 /// subtarget associated with CPUID . 118 /// 119 /// The value computed by a dependency breaking instruction is not dependent 120 /// on the inputs. An example of dependency breaking instruction on X86 is 121 /// `XOR %eax, %eax`. 122 /// 123 /// If MI is a dependency breaking instruction for subtarget CPUID, then Mask 124 /// can be inspected to identify independent operands. 125 /// 126 /// Essentially, each bit of the mask corresponds to an input operand. 127 /// Explicit operands are laid out first in the mask; implicit operands follow 128 /// explicit operands. Bits are set for operands that are independent. 129 /// 130 /// Note that the number of bits in Mask may not be equivalent to the sum of 131 /// explicit and implicit operands in MI. Operands that don't have a 132 /// corresponding bit in Mask are assumed "not independente". 133 /// 134 /// The only exception is for when Mask is all zeroes. That means: explicit 135 /// input operands of MI are independent. 136 virtual bool isDependencyBreaking(const MCInst &MI, APInt &Mask, 137 unsigned CPUID) const { 138 return isZeroIdiom(MI, Mask, CPUID); 139 } 140 141 /// Returns true if MI is a candidate for move elimination. 142 /// 143 /// Different subtargets may apply different constraints to optimizable 144 /// register moves. For example, on most X86 subtargets, a candidate for move 145 /// elimination cannot specify the same register for both source and 146 /// destination. 147 virtual bool isOptimizableRegisterMove(const MCInst &MI, 148 unsigned CPUID) const { 149 return false; 150 } 151 152 /// Given a branch instruction try to get the address the branch 153 /// targets. Return true on success, and the address in Target. 154 virtual bool 155 evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 156 uint64_t &Target) const; 157 158 /// Given an instruction tries to get the address of a memory operand. Returns 159 /// the address on success. 160 virtual Optional<uint64_t> 161 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, 162 uint64_t Addr, uint64_t Size) const; 163 164 /// Given an instruction with a memory operand that could require relocation, 165 /// returns the offset within the instruction of that relocation. 166 virtual Optional<uint64_t> 167 getMemoryOperandRelocationOffset(const MCInst &Inst, uint64_t Size) const; 168 169 /// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries. 170 virtual std::vector<std::pair<uint64_t, uint64_t>> 171 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 172 uint64_t GotPltSectionVA, const Triple &TargetTriple) const { 173 return {}; 174 } 175 }; 176 177 } // end namespace llvm 178 179 #endif // LLVM_MC_MCINSTRANALYSIS_H 180