1 //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file describes an abstract interface used to get information about a 10 // target machines register file. This information is used for a variety of 11 // purposed, especially register allocation. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_MC_MCREGISTERINFO_H 16 #define LLVM_MC_MCREGISTERINFO_H 17 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/ADT/iterator.h" 20 #include "llvm/ADT/iterator_range.h" 21 #include "llvm/MC/LaneBitmask.h" 22 #include "llvm/MC/MCRegister.h" 23 #include <cassert> 24 #include <cstdint> 25 #include <iterator> 26 #include <utility> 27 28 namespace llvm { 29 30 class MCRegUnitIterator; 31 class MCSubRegIterator; 32 class MCSuperRegIterator; 33 34 /// MCRegisterClass - Base class of TargetRegisterClass. 35 class MCRegisterClass { 36 public: 37 using iterator = const MCPhysReg*; 38 using const_iterator = const MCPhysReg*; 39 40 const iterator RegsBegin; 41 const uint8_t *const RegSet; 42 const uint32_t NameIdx; 43 const uint16_t RegsSize; 44 const uint16_t RegSetSize; 45 const uint16_t ID; 46 const uint16_t RegSizeInBits; 47 const int8_t CopyCost; 48 const bool Allocatable; 49 50 /// getID() - Return the register class ID number. 51 /// 52 unsigned getID() const { return ID; } 53 54 /// begin/end - Return all of the registers in this class. 55 /// 56 iterator begin() const { return RegsBegin; } 57 iterator end() const { return RegsBegin + RegsSize; } 58 59 /// getNumRegs - Return the number of registers in this class. 60 /// 61 unsigned getNumRegs() const { return RegsSize; } 62 63 /// getRegister - Return the specified register in the class. 64 /// 65 unsigned getRegister(unsigned i) const { 66 assert(i < getNumRegs() && "Register number out of range!"); 67 return RegsBegin[i]; 68 } 69 70 /// contains - Return true if the specified register is included in this 71 /// register class. This does not include virtual registers. 72 bool contains(MCRegister Reg) const { 73 unsigned RegNo = unsigned(Reg); 74 unsigned InByte = RegNo % 8; 75 unsigned Byte = RegNo / 8; 76 if (Byte >= RegSetSize) 77 return false; 78 return (RegSet[Byte] & (1 << InByte)) != 0; 79 } 80 81 /// contains - Return true if both registers are in this class. 82 bool contains(MCRegister Reg1, MCRegister Reg2) const { 83 return contains(Reg1) && contains(Reg2); 84 } 85 86 /// Return the size of the physical register in bits if we are able to 87 /// determine it. This always returns zero for registers of targets that use 88 /// HW modes, as we need more information to determine the size of registers 89 /// in such cases. Use TargetRegisterInfo to cover them. 90 unsigned getSizeInBits() const { return RegSizeInBits; } 91 92 /// getCopyCost - Return the cost of copying a value between two registers in 93 /// this class. A negative number means the register class is very expensive 94 /// to copy e.g. status flag register classes. 95 int getCopyCost() const { return CopyCost; } 96 97 /// isAllocatable - Return true if this register class may be used to create 98 /// virtual registers. 99 bool isAllocatable() const { return Allocatable; } 100 }; 101 102 /// MCRegisterDesc - This record contains information about a particular 103 /// register. The SubRegs field is a zero terminated array of registers that 104 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers 105 /// of AX. The SuperRegs field is a zero terminated array of registers that are 106 /// super-registers of the specific register, e.g. RAX, EAX, are 107 /// super-registers of AX. 108 /// 109 struct MCRegisterDesc { 110 uint32_t Name; // Printable name for the reg (for debugging) 111 uint32_t SubRegs; // Sub-register set, described above 112 uint32_t SuperRegs; // Super-register set, described above 113 114 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each 115 // sub-register in SubRegs. 116 uint32_t SubRegIndices; 117 118 // Points to the list of register units. The low bits hold the first regunit 119 // number, the high bits hold an offset into DiffLists. See MCRegUnitIterator. 120 uint32_t RegUnits; 121 122 /// Index into list with lane mask sequences. The sequence contains a lanemask 123 /// for every register unit. 124 uint16_t RegUnitLaneMasks; 125 }; 126 127 /// MCRegisterInfo base class - We assume that the target defines a static 128 /// array of MCRegisterDesc objects that represent all of the machine 129 /// registers that the target has. As such, we simply have to track a pointer 130 /// to this array so that we can turn register number into a register 131 /// descriptor. 132 /// 133 /// Note this class is designed to be a base class of TargetRegisterInfo, which 134 /// is the interface used by codegen. However, specific targets *should never* 135 /// specialize this class. MCRegisterInfo should only contain getters to access 136 /// TableGen generated physical register data. It must not be extended with 137 /// virtual methods. 138 /// 139 class MCRegisterInfo { 140 public: 141 using regclass_iterator = const MCRegisterClass *; 142 143 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 144 /// performed with a binary search. 145 struct DwarfLLVMRegPair { 146 unsigned FromReg; 147 unsigned ToReg; 148 149 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } 150 }; 151 152 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg 153 /// index, -1 in any being invalid. 154 struct SubRegCoveredBits { 155 uint16_t Offset; 156 uint16_t Size; 157 }; 158 159 private: 160 const MCRegisterDesc *Desc; // Pointer to the descriptor array 161 unsigned NumRegs; // Number of entries in the array 162 MCRegister RAReg; // Return address register 163 MCRegister PCReg; // Program counter register 164 const MCRegisterClass *Classes; // Pointer to the regclass array 165 unsigned NumClasses; // Number of entries in the array 166 unsigned NumRegUnits; // Number of regunits. 167 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table. 168 const int16_t *DiffLists; // Pointer to the difflists array 169 const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences 170 // for register units. 171 const char *RegStrings; // Pointer to the string table. 172 const char *RegClassStrings; // Pointer to the class strings. 173 const uint16_t *SubRegIndices; // Pointer to the subreg lookup 174 // array. 175 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered 176 // bit ranges array. 177 unsigned NumSubRegIndices; // Number of subreg indices. 178 const uint16_t *RegEncodingTable; // Pointer to array of register 179 // encodings. 180 181 unsigned L2DwarfRegsSize; 182 unsigned EHL2DwarfRegsSize; 183 unsigned Dwarf2LRegsSize; 184 unsigned EHDwarf2LRegsSize; 185 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping 186 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 187 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping 188 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 189 DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping 190 DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping 191 192 /// Iterator class that can traverse the differentially encoded values in 193 /// DiffLists. Don't use this class directly, use one of the adaptors below. 194 class DiffListIterator 195 : public iterator_facade_base<DiffListIterator, std::forward_iterator_tag, 196 unsigned> { 197 unsigned Val = 0; 198 const int16_t *List = nullptr; 199 200 public: 201 /// Constructs an invalid iterator, which is also the end iterator. 202 /// Call init() to point to something useful. 203 DiffListIterator() = default; 204 205 /// Point the iterator to InitVal, decoding subsequent values from DiffList. 206 void init(unsigned InitVal, const int16_t *DiffList) { 207 Val = InitVal; 208 List = DiffList; 209 } 210 211 /// Returns true if this iterator is not yet at the end. 212 bool isValid() const { return List; } 213 214 /// Dereference the iterator to get the value at the current position. 215 const unsigned &operator*() const { return Val; } 216 217 using DiffListIterator::iterator_facade_base::operator++; 218 /// Pre-increment to move to the next position. 219 DiffListIterator &operator++() { 220 assert(isValid() && "Cannot move off the end of the list."); 221 int16_t D = *List++; 222 Val += D; 223 // The end of the list is encoded as a 0 differential. 224 if (!D) 225 List = nullptr; 226 return *this; 227 } 228 229 bool operator==(const DiffListIterator &Other) const { 230 return List == Other.List; 231 } 232 }; 233 234 public: 235 /// Return an iterator range over all sub-registers of \p Reg, excluding \p 236 /// Reg. 237 iterator_range<MCSubRegIterator> subregs(MCRegister Reg) const; 238 239 /// Return an iterator range over all sub-registers of \p Reg, including \p 240 /// Reg. 241 iterator_range<MCSubRegIterator> subregs_inclusive(MCRegister Reg) const; 242 243 /// Return an iterator range over all super-registers of \p Reg, excluding \p 244 /// Reg. 245 iterator_range<MCSuperRegIterator> superregs(MCRegister Reg) const; 246 247 /// Return an iterator range over all super-registers of \p Reg, including \p 248 /// Reg. 249 iterator_range<MCSuperRegIterator> superregs_inclusive(MCRegister Reg) const; 250 251 /// Return an iterator range over all sub- and super-registers of \p Reg, 252 /// including \p Reg. 253 detail::concat_range<const MCPhysReg, iterator_range<MCSubRegIterator>, 254 iterator_range<MCSuperRegIterator>> 255 sub_and_superregs_inclusive(MCRegister Reg) const; 256 257 /// Returns an iterator range over all regunits for \p Reg. 258 iterator_range<MCRegUnitIterator> regunits(MCRegister Reg) const; 259 260 // These iterators are allowed to sub-class DiffListIterator and access 261 // internal list pointers. 262 friend class MCSubRegIterator; 263 friend class MCSubRegIndexIterator; 264 friend class MCSuperRegIterator; 265 friend class MCRegUnitIterator; 266 friend class MCRegUnitMaskIterator; 267 friend class MCRegUnitRootIterator; 268 269 /// Initialize MCRegisterInfo, called by TableGen 270 /// auto-generated routines. *DO NOT USE*. 271 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 272 unsigned PC, const MCRegisterClass *C, unsigned NC, 273 const MCPhysReg (*RURoots)[2], unsigned NRU, 274 const int16_t *DL, const LaneBitmask *RUMS, 275 const char *Strings, const char *ClassStrings, 276 const uint16_t *SubIndices, unsigned NumIndices, 277 const SubRegCoveredBits *SubIdxRanges, 278 const uint16_t *RET) { 279 Desc = D; 280 NumRegs = NR; 281 RAReg = RA; 282 PCReg = PC; 283 Classes = C; 284 DiffLists = DL; 285 RegUnitMaskSequences = RUMS; 286 RegStrings = Strings; 287 RegClassStrings = ClassStrings; 288 NumClasses = NC; 289 RegUnitRoots = RURoots; 290 NumRegUnits = NRU; 291 SubRegIndices = SubIndices; 292 NumSubRegIndices = NumIndices; 293 SubRegIdxRanges = SubIdxRanges; 294 RegEncodingTable = RET; 295 296 // Initialize DWARF register mapping variables 297 EHL2DwarfRegs = nullptr; 298 EHL2DwarfRegsSize = 0; 299 L2DwarfRegs = nullptr; 300 L2DwarfRegsSize = 0; 301 EHDwarf2LRegs = nullptr; 302 EHDwarf2LRegsSize = 0; 303 Dwarf2LRegs = nullptr; 304 Dwarf2LRegsSize = 0; 305 } 306 307 /// Used to initialize LLVM register to Dwarf 308 /// register number mapping. Called by TableGen auto-generated routines. 309 /// *DO NOT USE*. 310 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, 311 bool isEH) { 312 if (isEH) { 313 EHL2DwarfRegs = Map; 314 EHL2DwarfRegsSize = Size; 315 } else { 316 L2DwarfRegs = Map; 317 L2DwarfRegsSize = Size; 318 } 319 } 320 321 /// Used to initialize Dwarf register to LLVM 322 /// register number mapping. Called by TableGen auto-generated routines. 323 /// *DO NOT USE*. 324 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, 325 bool isEH) { 326 if (isEH) { 327 EHDwarf2LRegs = Map; 328 EHDwarf2LRegsSize = Size; 329 } else { 330 Dwarf2LRegs = Map; 331 Dwarf2LRegsSize = Size; 332 } 333 } 334 335 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 336 /// number mapping. By default the SEH register number is just the same 337 /// as the LLVM register number. 338 /// FIXME: TableGen these numbers. Currently this requires target specific 339 /// initialization code. 340 void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) { 341 L2SEHRegs[LLVMReg] = SEHReg; 342 } 343 344 void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) { 345 L2CVRegs[LLVMReg] = CVReg; 346 } 347 348 /// This method should return the register where the return 349 /// address can be found. 350 MCRegister getRARegister() const { 351 return RAReg; 352 } 353 354 /// Return the register which is the program counter. 355 MCRegister getProgramCounter() const { 356 return PCReg; 357 } 358 359 const MCRegisterDesc &operator[](MCRegister RegNo) const { 360 assert(RegNo < NumRegs && 361 "Attempting to access record for invalid register number!"); 362 return Desc[RegNo]; 363 } 364 365 /// Provide a get method, equivalent to [], but more useful with a 366 /// pointer to this object. 367 const MCRegisterDesc &get(MCRegister RegNo) const { 368 return operator[](RegNo); 369 } 370 371 /// Returns the physical register number of sub-register "Index" 372 /// for physical register RegNo. Return zero if the sub-register does not 373 /// exist. 374 MCRegister getSubReg(MCRegister Reg, unsigned Idx) const; 375 376 /// Return a super-register of the specified register 377 /// Reg so its sub-register of index SubIdx is Reg. 378 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, 379 const MCRegisterClass *RC) const; 380 381 /// For a given register pair, return the sub-register index 382 /// if the second register is a sub-register of the first. Return zero 383 /// otherwise. 384 unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const; 385 386 /// Get the size of the bit range covered by a sub-register index. 387 /// If the index isn't continuous, return the sum of the sizes of its parts. 388 /// If the index is used to access subregisters of different sizes, return -1. 389 unsigned getSubRegIdxSize(unsigned Idx) const; 390 391 /// Get the offset of the bit range covered by a sub-register index. 392 /// If an Offset doesn't make sense (the index isn't continuous, or is used to 393 /// access sub-registers at different offsets), return -1. 394 unsigned getSubRegIdxOffset(unsigned Idx) const; 395 396 /// Return the human-readable symbolic target-specific name for the 397 /// specified physical register. 398 const char *getName(MCRegister RegNo) const { 399 return RegStrings + get(RegNo).Name; 400 } 401 402 /// Return the number of registers this target has (useful for 403 /// sizing arrays holding per register information) 404 unsigned getNumRegs() const { 405 return NumRegs; 406 } 407 408 /// Return the number of sub-register indices 409 /// understood by the target. Index 0 is reserved for the no-op sub-register, 410 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers. 411 unsigned getNumSubRegIndices() const { 412 return NumSubRegIndices; 413 } 414 415 /// Return the number of (native) register units in the 416 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They 417 /// can be accessed through MCRegUnitIterator defined below. 418 unsigned getNumRegUnits() const { 419 return NumRegUnits; 420 } 421 422 /// Map a target register to an equivalent dwarf register 423 /// number. Returns -1 if there is no equivalent value. The second 424 /// parameter allows targets to use different numberings for EH info and 425 /// debugging info. 426 int getDwarfRegNum(MCRegister RegNum, bool isEH) const; 427 428 /// Map a dwarf register back to a target register. Returns std::nullopt is 429 /// there is no mapping. 430 std::optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const; 431 432 /// Map a target EH register number to an equivalent DWARF register 433 /// number. 434 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const; 435 436 /// Map a target register to an equivalent SEH register 437 /// number. Returns LLVM register number if there is no equivalent value. 438 int getSEHRegNum(MCRegister RegNum) const; 439 440 /// Map a target register to an equivalent CodeView register 441 /// number. 442 int getCodeViewRegNum(MCRegister RegNum) const; 443 444 regclass_iterator regclass_begin() const { return Classes; } 445 regclass_iterator regclass_end() const { return Classes+NumClasses; } 446 iterator_range<regclass_iterator> regclasses() const { 447 return make_range(regclass_begin(), regclass_end()); 448 } 449 450 unsigned getNumRegClasses() const { 451 return (unsigned)(regclass_end()-regclass_begin()); 452 } 453 454 /// Returns the register class associated with the enumeration 455 /// value. See class MCOperandInfo. 456 const MCRegisterClass& getRegClass(unsigned i) const { 457 assert(i < getNumRegClasses() && "Register Class ID out of range"); 458 return Classes[i]; 459 } 460 461 const char *getRegClassName(const MCRegisterClass *Class) const { 462 return RegClassStrings + Class->NameIdx; 463 } 464 465 /// Returns the encoding for RegNo 466 uint16_t getEncodingValue(MCRegister RegNo) const { 467 assert(RegNo < NumRegs && 468 "Attempting to get encoding for invalid register number!"); 469 return RegEncodingTable[RegNo]; 470 } 471 472 /// Returns true if RegB is a sub-register of RegA. 473 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { 474 return isSuperRegister(RegB, RegA); 475 } 476 477 /// Returns true if RegB is a super-register of RegA. 478 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const; 479 480 /// Returns true if RegB is a sub-register of RegA or if RegB == RegA. 481 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { 482 return isSuperRegisterEq(RegB, RegA); 483 } 484 485 /// Returns true if RegB is a super-register of RegA or if 486 /// RegB == RegA. 487 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { 488 return RegA == RegB || isSuperRegister(RegA, RegB); 489 } 490 491 /// Returns true if RegB is a super-register or sub-register of RegA 492 /// or if RegB == RegA. 493 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { 494 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); 495 } 496 497 /// Returns true if the two registers are equal or alias each other. 498 bool regsOverlap(MCRegister RegA, MCRegister RegB) const; 499 }; 500 501 //===----------------------------------------------------------------------===// 502 // Register List Iterators 503 //===----------------------------------------------------------------------===// 504 505 // MCRegisterInfo provides lists of super-registers, sub-registers, and 506 // aliasing registers. Use these iterator classes to traverse the lists. 507 508 /// MCSubRegIterator enumerates all sub-registers of Reg. 509 /// If IncludeSelf is set, Reg itself is included in the list. 510 class MCSubRegIterator 511 : public iterator_adaptor_base<MCSubRegIterator, 512 MCRegisterInfo::DiffListIterator, 513 std::forward_iterator_tag, const MCPhysReg> { 514 // Cache the current value, so that we can return a reference to it. 515 MCPhysReg Val; 516 517 public: 518 /// Constructs an end iterator. 519 MCSubRegIterator() = default; 520 521 MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, 522 bool IncludeSelf = false) { 523 assert(MCRegister::isPhysicalRegister(Reg.id())); 524 I.init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SubRegs); 525 // Initially, the iterator points to Reg itself. 526 Val = MCPhysReg(*I); 527 if (!IncludeSelf) 528 ++*this; 529 } 530 531 const MCPhysReg &operator*() const { return Val; } 532 533 using iterator_adaptor_base::operator++; 534 MCSubRegIterator &operator++() { 535 Val = MCPhysReg(*++I); 536 return *this; 537 } 538 539 /// Returns true if this iterator is not yet at the end. 540 bool isValid() const { return I.isValid(); } 541 }; 542 543 /// Iterator that enumerates the sub-registers of a Reg and the associated 544 /// sub-register indices. 545 class MCSubRegIndexIterator { 546 MCSubRegIterator SRIter; 547 const uint16_t *SRIndex; 548 549 public: 550 /// Constructs an iterator that traverses subregisters and their 551 /// associated subregister indices. 552 MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI) 553 : SRIter(Reg, MCRI) { 554 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; 555 } 556 557 /// Returns current sub-register. 558 MCRegister getSubReg() const { 559 return *SRIter; 560 } 561 562 /// Returns sub-register index of the current sub-register. 563 unsigned getSubRegIndex() const { 564 return *SRIndex; 565 } 566 567 /// Returns true if this iterator is not yet at the end. 568 bool isValid() const { return SRIter.isValid(); } 569 570 /// Moves to the next position. 571 void operator++() { 572 ++SRIter; 573 ++SRIndex; 574 } 575 }; 576 577 /// MCSuperRegIterator enumerates all super-registers of Reg. 578 /// If IncludeSelf is set, Reg itself is included in the list. 579 class MCSuperRegIterator 580 : public iterator_adaptor_base<MCSuperRegIterator, 581 MCRegisterInfo::DiffListIterator, 582 std::forward_iterator_tag, const MCPhysReg> { 583 // Cache the current value, so that we can return a reference to it. 584 MCPhysReg Val; 585 586 public: 587 /// Constructs an end iterator. 588 MCSuperRegIterator() = default; 589 590 MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, 591 bool IncludeSelf = false) { 592 assert(MCRegister::isPhysicalRegister(Reg.id())); 593 I.init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SuperRegs); 594 // Initially, the iterator points to Reg itself. 595 Val = MCPhysReg(*I); 596 if (!IncludeSelf) 597 ++*this; 598 } 599 600 const MCPhysReg &operator*() const { return Val; } 601 602 using iterator_adaptor_base::operator++; 603 MCSuperRegIterator &operator++() { 604 Val = MCPhysReg(*++I); 605 return *this; 606 } 607 608 /// Returns true if this iterator is not yet at the end. 609 bool isValid() const { return I.isValid(); } 610 }; 611 612 // Definition for isSuperRegister. Put it down here since it needs the 613 // iterator defined above in addition to the MCRegisterInfo class itself. 614 inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{ 615 return is_contained(superregs(RegA), RegB); 616 } 617 618 //===----------------------------------------------------------------------===// 619 // Register Units 620 //===----------------------------------------------------------------------===// 621 622 // MCRegUnitIterator enumerates a list of register units for Reg. The list is 623 // in ascending numerical order. 624 class MCRegUnitIterator 625 : public iterator_adaptor_base<MCRegUnitIterator, 626 MCRegisterInfo::DiffListIterator, 627 std::forward_iterator_tag, const MCRegUnit> { 628 // The value must be kept in sync with RegisterInfoEmitter.cpp. 629 static constexpr unsigned RegUnitBits = 12; 630 // Cache the current value, so that we can return a reference to it. 631 MCRegUnit Val; 632 633 public: 634 /// Constructs an end iterator. 635 MCRegUnitIterator() = default; 636 637 MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) { 638 assert(Reg && "Null register has no regunits"); 639 assert(MCRegister::isPhysicalRegister(Reg.id())); 640 // Decode the RegUnits MCRegisterDesc field. 641 unsigned RU = MCRI->get(Reg).RegUnits; 642 unsigned FirstRU = RU & ((1u << RegUnitBits) - 1); 643 unsigned Offset = RU >> RegUnitBits; 644 I.init(FirstRU, MCRI->DiffLists + Offset); 645 Val = MCRegUnit(*I); 646 } 647 648 const MCRegUnit &operator*() const { return Val; } 649 650 using iterator_adaptor_base::operator++; 651 MCRegUnitIterator &operator++() { 652 Val = MCRegUnit(*++I); 653 return *this; 654 } 655 656 /// Returns true if this iterator is not yet at the end. 657 bool isValid() const { return I.isValid(); } 658 }; 659 660 /// MCRegUnitMaskIterator enumerates a list of register units and their 661 /// associated lane masks for Reg. The register units are in ascending 662 /// numerical order. 663 class MCRegUnitMaskIterator { 664 MCRegUnitIterator RUIter; 665 const LaneBitmask *MaskListIter; 666 667 public: 668 MCRegUnitMaskIterator() = default; 669 670 /// Constructs an iterator that traverses the register units and their 671 /// associated LaneMasks in Reg. 672 MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI) 673 : RUIter(Reg, MCRI) { 674 uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks; 675 MaskListIter = &MCRI->RegUnitMaskSequences[Idx]; 676 } 677 678 /// Returns a (RegUnit, LaneMask) pair. 679 std::pair<unsigned,LaneBitmask> operator*() const { 680 return std::make_pair(*RUIter, *MaskListIter); 681 } 682 683 /// Returns true if this iterator is not yet at the end. 684 bool isValid() const { return RUIter.isValid(); } 685 686 /// Moves to the next position. 687 void operator++() { 688 ++MaskListIter; 689 ++RUIter; 690 } 691 }; 692 693 // Each register unit has one or two root registers. The complete set of 694 // registers containing a register unit is the union of the roots and their 695 // super-registers. All registers aliasing Unit can be visited like this: 696 // 697 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { 698 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI) 699 // visit(*SI); 700 // } 701 702 /// MCRegUnitRootIterator enumerates the root registers of a register unit. 703 class MCRegUnitRootIterator { 704 uint16_t Reg0 = 0; 705 uint16_t Reg1 = 0; 706 707 public: 708 MCRegUnitRootIterator() = default; 709 710 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { 711 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); 712 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; 713 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; 714 } 715 716 /// Dereference to get the current root register. 717 unsigned operator*() const { 718 return Reg0; 719 } 720 721 /// Check if the iterator is at the end of the list. 722 bool isValid() const { 723 return Reg0; 724 } 725 726 /// Preincrement to move to the next root register. 727 void operator++() { 728 assert(isValid() && "Cannot move off the end of the list."); 729 Reg0 = Reg1; 730 Reg1 = 0; 731 } 732 }; 733 734 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is 735 /// set, Reg itself is included in the list. This iterator does not guarantee 736 /// any ordering or that entries are unique. 737 class MCRegAliasIterator { 738 private: 739 MCRegister Reg; 740 const MCRegisterInfo *MCRI; 741 bool IncludeSelf; 742 743 MCRegUnitIterator RI; 744 MCRegUnitRootIterator RRI; 745 MCSuperRegIterator SI; 746 747 public: 748 MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI, 749 bool IncludeSelf) 750 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) { 751 // Initialize the iterators. 752 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) { 753 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) { 754 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) { 755 if (!(!IncludeSelf && Reg == *SI)) 756 return; 757 } 758 } 759 } 760 } 761 762 bool isValid() const { return RI.isValid(); } 763 764 MCRegister operator*() const { 765 assert(SI.isValid() && "Cannot dereference an invalid iterator."); 766 return *SI; 767 } 768 769 void advance() { 770 // Assuming SI is valid. 771 ++SI; 772 if (SI.isValid()) return; 773 774 ++RRI; 775 if (RRI.isValid()) { 776 SI = MCSuperRegIterator(*RRI, MCRI, true); 777 return; 778 } 779 780 ++RI; 781 if (RI.isValid()) { 782 RRI = MCRegUnitRootIterator(*RI, MCRI); 783 SI = MCSuperRegIterator(*RRI, MCRI, true); 784 } 785 } 786 787 void operator++() { 788 assert(isValid() && "Cannot move off the end of the list."); 789 do advance(); 790 while (!IncludeSelf && isValid() && *SI == Reg); 791 } 792 }; 793 794 inline iterator_range<MCSubRegIterator> 795 MCRegisterInfo::subregs(MCRegister Reg) const { 796 return make_range({Reg, this, /*IncludeSelf=*/false}, MCSubRegIterator()); 797 } 798 799 inline iterator_range<MCSubRegIterator> 800 MCRegisterInfo::subregs_inclusive(MCRegister Reg) const { 801 return make_range({Reg, this, /*IncludeSelf=*/true}, MCSubRegIterator()); 802 } 803 804 inline iterator_range<MCSuperRegIterator> 805 MCRegisterInfo::superregs(MCRegister Reg) const { 806 return make_range({Reg, this, /*IncludeSelf=*/false}, MCSuperRegIterator()); 807 } 808 809 inline iterator_range<MCSuperRegIterator> 810 MCRegisterInfo::superregs_inclusive(MCRegister Reg) const { 811 return make_range({Reg, this, /*IncludeSelf=*/true}, MCSuperRegIterator()); 812 } 813 814 inline detail::concat_range<const MCPhysReg, iterator_range<MCSubRegIterator>, 815 iterator_range<MCSuperRegIterator>> 816 MCRegisterInfo::sub_and_superregs_inclusive(MCRegister Reg) const { 817 return concat<const MCPhysReg>(subregs_inclusive(Reg), superregs(Reg)); 818 } 819 820 inline iterator_range<MCRegUnitIterator> 821 MCRegisterInfo::regunits(MCRegister Reg) const { 822 return make_range({Reg, this}, MCRegUnitIterator()); 823 } 824 825 } // end namespace llvm 826 827 #endif // LLVM_MC_MCREGISTERINFO_H 828