1 //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file describes an abstract interface used to get information about a 10 // target machines register file. This information is used for a variety of 11 // purposed, especially register allocation. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_MC_MCREGISTERINFO_H 16 #define LLVM_MC_MCREGISTERINFO_H 17 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/ADT/iterator.h" 20 #include "llvm/ADT/iterator_range.h" 21 #include "llvm/MC/LaneBitmask.h" 22 #include "llvm/MC/MCRegister.h" 23 #include <cassert> 24 #include <cstdint> 25 #include <iterator> 26 #include <utility> 27 28 namespace llvm { 29 30 /// MCRegisterClass - Base class of TargetRegisterClass. 31 class MCRegisterClass { 32 public: 33 using iterator = const MCPhysReg*; 34 using const_iterator = const MCPhysReg*; 35 36 const iterator RegsBegin; 37 const uint8_t *const RegSet; 38 const uint32_t NameIdx; 39 const uint16_t RegsSize; 40 const uint16_t RegSetSize; 41 const uint16_t ID; 42 const int8_t CopyCost; 43 const bool Allocatable; 44 45 /// getID() - Return the register class ID number. 46 /// 47 unsigned getID() const { return ID; } 48 49 /// begin/end - Return all of the registers in this class. 50 /// 51 iterator begin() const { return RegsBegin; } 52 iterator end() const { return RegsBegin + RegsSize; } 53 54 /// getNumRegs - Return the number of registers in this class. 55 /// 56 unsigned getNumRegs() const { return RegsSize; } 57 58 /// getRegister - Return the specified register in the class. 59 /// 60 unsigned getRegister(unsigned i) const { 61 assert(i < getNumRegs() && "Register number out of range!"); 62 return RegsBegin[i]; 63 } 64 65 /// contains - Return true if the specified register is included in this 66 /// register class. This does not include virtual registers. 67 bool contains(MCRegister Reg) const { 68 unsigned RegNo = unsigned(Reg); 69 unsigned InByte = RegNo % 8; 70 unsigned Byte = RegNo / 8; 71 if (Byte >= RegSetSize) 72 return false; 73 return (RegSet[Byte] & (1 << InByte)) != 0; 74 } 75 76 /// contains - Return true if both registers are in this class. 77 bool contains(MCRegister Reg1, MCRegister Reg2) const { 78 return contains(Reg1) && contains(Reg2); 79 } 80 81 /// getCopyCost - Return the cost of copying a value between two registers in 82 /// this class. A negative number means the register class is very expensive 83 /// to copy e.g. status flag register classes. 84 int getCopyCost() const { return CopyCost; } 85 86 /// isAllocatable - Return true if this register class may be used to create 87 /// virtual registers. 88 bool isAllocatable() const { return Allocatable; } 89 }; 90 91 /// MCRegisterDesc - This record contains information about a particular 92 /// register. The SubRegs field is a zero terminated array of registers that 93 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers 94 /// of AX. The SuperRegs field is a zero terminated array of registers that are 95 /// super-registers of the specific register, e.g. RAX, EAX, are 96 /// super-registers of AX. 97 /// 98 struct MCRegisterDesc { 99 uint32_t Name; // Printable name for the reg (for debugging) 100 uint32_t SubRegs; // Sub-register set, described above 101 uint32_t SuperRegs; // Super-register set, described above 102 103 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each 104 // sub-register in SubRegs. 105 uint32_t SubRegIndices; 106 107 // RegUnits - Points to the list of register units. The low 4 bits holds the 108 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. 109 uint32_t RegUnits; 110 111 /// Index into list with lane mask sequences. The sequence contains a lanemask 112 /// for every register unit. 113 uint16_t RegUnitLaneMasks; 114 }; 115 116 /// MCRegisterInfo base class - We assume that the target defines a static 117 /// array of MCRegisterDesc objects that represent all of the machine 118 /// registers that the target has. As such, we simply have to track a pointer 119 /// to this array so that we can turn register number into a register 120 /// descriptor. 121 /// 122 /// Note this class is designed to be a base class of TargetRegisterInfo, which 123 /// is the interface used by codegen. However, specific targets *should never* 124 /// specialize this class. MCRegisterInfo should only contain getters to access 125 /// TableGen generated physical register data. It must not be extended with 126 /// virtual methods. 127 /// 128 class MCRegisterInfo { 129 public: 130 using regclass_iterator = const MCRegisterClass *; 131 132 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 133 /// performed with a binary search. 134 struct DwarfLLVMRegPair { 135 unsigned FromReg; 136 unsigned ToReg; 137 138 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } 139 }; 140 141 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg 142 /// index, -1 in any being invalid. 143 struct SubRegCoveredBits { 144 uint16_t Offset; 145 uint16_t Size; 146 }; 147 148 private: 149 const MCRegisterDesc *Desc; // Pointer to the descriptor array 150 unsigned NumRegs; // Number of entries in the array 151 MCRegister RAReg; // Return address register 152 MCRegister PCReg; // Program counter register 153 const MCRegisterClass *Classes; // Pointer to the regclass array 154 unsigned NumClasses; // Number of entries in the array 155 unsigned NumRegUnits; // Number of regunits. 156 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table. 157 const MCPhysReg *DiffLists; // Pointer to the difflists array 158 const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences 159 // for register units. 160 const char *RegStrings; // Pointer to the string table. 161 const char *RegClassStrings; // Pointer to the class strings. 162 const uint16_t *SubRegIndices; // Pointer to the subreg lookup 163 // array. 164 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered 165 // bit ranges array. 166 unsigned NumSubRegIndices; // Number of subreg indices. 167 const uint16_t *RegEncodingTable; // Pointer to array of register 168 // encodings. 169 170 unsigned L2DwarfRegsSize; 171 unsigned EHL2DwarfRegsSize; 172 unsigned Dwarf2LRegsSize; 173 unsigned EHDwarf2LRegsSize; 174 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping 175 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 176 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping 177 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 178 DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping 179 DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping 180 181 public: 182 // Forward declaration to become a friend class of DiffListIterator. 183 template <class SubT> class mc_difflist_iterator; 184 185 /// DiffListIterator - Base iterator class that can traverse the 186 /// differentially encoded register and regunit lists in DiffLists. 187 /// Don't use this class directly, use one of the specialized sub-classes 188 /// defined below. 189 class DiffListIterator { 190 uint16_t Val = 0; 191 const MCPhysReg *List = nullptr; 192 193 protected: 194 /// Create an invalid iterator. Call init() to point to something useful. 195 DiffListIterator() = default; 196 197 /// init - Point the iterator to InitVal, decoding subsequent values from 198 /// DiffList. The iterator will initially point to InitVal, sub-classes are 199 /// responsible for skipping the seed value if it is not part of the list. 200 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { 201 Val = InitVal; 202 List = DiffList; 203 } 204 205 /// advance - Move to the next list position, return the applied 206 /// differential. This function does not detect the end of the list, that 207 /// is the caller's responsibility (by checking for a 0 return value). 208 MCRegister advance() { 209 assert(isValid() && "Cannot move off the end of the list."); 210 MCPhysReg D = *List++; 211 Val += D; 212 return D; 213 } 214 215 public: 216 /// isValid - returns true if this iterator is not yet at the end. 217 bool isValid() const { return List; } 218 219 /// Dereference the iterator to get the value at the current position. 220 MCRegister operator*() const { return Val; } 221 222 /// Pre-increment to move to the next position. 223 void operator++() { 224 // The end of the list is encoded as a 0 differential. 225 if (!advance()) 226 List = nullptr; 227 } 228 229 template <class SubT> friend class MCRegisterInfo::mc_difflist_iterator; 230 }; 231 232 /// Forward iterator using DiffListIterator. 233 template <class SubT> 234 class mc_difflist_iterator 235 : public iterator_facade_base<mc_difflist_iterator<SubT>, 236 std::forward_iterator_tag, MCPhysReg> { 237 MCRegisterInfo::DiffListIterator Iter; 238 /// Current value as MCPhysReg, so we can return a reference to it. 239 MCPhysReg Val; 240 241 protected: 242 mc_difflist_iterator(MCRegisterInfo::DiffListIterator Iter) : Iter(Iter) {} 243 244 // Allow conversion between instantiations where valid. 245 mc_difflist_iterator(MCRegister Reg, const MCPhysReg *DiffList) { 246 Iter.init(Reg, DiffList); 247 Val = *Iter; 248 } 249 250 public: 251 // Allow default construction to build variables, but this doesn't build 252 // a useful iterator. 253 mc_difflist_iterator() = default; 254 255 /// Return an iterator past the last element. 256 static SubT end() { 257 SubT End; 258 End.Iter.List = nullptr; 259 return End; 260 } 261 262 bool operator==(const mc_difflist_iterator &Arg) const { 263 return Iter.List == Arg.Iter.List; 264 } 265 266 const MCPhysReg &operator*() const { return Val; } 267 268 using mc_difflist_iterator::iterator_facade_base::operator++; 269 void operator++() { 270 assert(Iter.List && "Cannot increment the end iterator!"); 271 ++Iter; 272 Val = *Iter; 273 } 274 }; 275 276 /// Forward iterator over all sub-registers. 277 /// TODO: Replace remaining uses of MCSubRegIterator. 278 class mc_subreg_iterator : public mc_difflist_iterator<mc_subreg_iterator> { 279 public: 280 mc_subreg_iterator(MCRegisterInfo::DiffListIterator Iter) 281 : mc_difflist_iterator(Iter) {} 282 mc_subreg_iterator() = default; 283 mc_subreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI) 284 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {} 285 }; 286 287 /// Forward iterator over all super-registers. 288 /// TODO: Replace remaining uses of MCSuperRegIterator. 289 class mc_superreg_iterator 290 : public mc_difflist_iterator<mc_superreg_iterator> { 291 public: 292 mc_superreg_iterator(MCRegisterInfo::DiffListIterator Iter) 293 : mc_difflist_iterator(Iter) {} 294 mc_superreg_iterator() = default; 295 mc_superreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI) 296 : mc_difflist_iterator(Reg, 297 MCRI->DiffLists + MCRI->get(Reg).SuperRegs) {} 298 }; 299 300 /// Return an iterator range over all sub-registers of \p Reg, excluding \p 301 /// Reg. 302 iterator_range<mc_subreg_iterator> subregs(MCRegister Reg) const { 303 return make_range(std::next(mc_subreg_iterator(Reg, this)), 304 mc_subreg_iterator::end()); 305 } 306 307 /// Return an iterator range over all sub-registers of \p Reg, including \p 308 /// Reg. 309 iterator_range<mc_subreg_iterator> subregs_inclusive(MCRegister Reg) const { 310 return make_range({Reg, this}, mc_subreg_iterator::end()); 311 } 312 313 /// Return an iterator range over all super-registers of \p Reg, excluding \p 314 /// Reg. 315 iterator_range<mc_superreg_iterator> superregs(MCRegister Reg) const { 316 return make_range(std::next(mc_superreg_iterator(Reg, this)), 317 mc_superreg_iterator::end()); 318 } 319 320 /// Return an iterator range over all super-registers of \p Reg, including \p 321 /// Reg. 322 iterator_range<mc_superreg_iterator> 323 superregs_inclusive(MCRegister Reg) const { 324 return make_range({Reg, this}, mc_superreg_iterator::end()); 325 } 326 327 /// Return an iterator range over all sub- and super-registers of \p Reg, 328 /// including \p Reg. 329 detail::concat_range<const MCPhysReg, iterator_range<mc_subreg_iterator>, 330 iterator_range<mc_superreg_iterator>> 331 sub_and_superregs_inclusive(MCRegister Reg) const { 332 return concat<const MCPhysReg>(subregs_inclusive(Reg), superregs(Reg)); 333 } 334 335 // These iterators are allowed to sub-class DiffListIterator and access 336 // internal list pointers. 337 friend class MCSubRegIterator; 338 friend class MCSubRegIndexIterator; 339 friend class MCSuperRegIterator; 340 friend class MCRegUnitIterator; 341 friend class MCRegUnitMaskIterator; 342 friend class MCRegUnitRootIterator; 343 344 /// Initialize MCRegisterInfo, called by TableGen 345 /// auto-generated routines. *DO NOT USE*. 346 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 347 unsigned PC, 348 const MCRegisterClass *C, unsigned NC, 349 const MCPhysReg (*RURoots)[2], 350 unsigned NRU, 351 const MCPhysReg *DL, 352 const LaneBitmask *RUMS, 353 const char *Strings, 354 const char *ClassStrings, 355 const uint16_t *SubIndices, 356 unsigned NumIndices, 357 const SubRegCoveredBits *SubIdxRanges, 358 const uint16_t *RET) { 359 Desc = D; 360 NumRegs = NR; 361 RAReg = RA; 362 PCReg = PC; 363 Classes = C; 364 DiffLists = DL; 365 RegUnitMaskSequences = RUMS; 366 RegStrings = Strings; 367 RegClassStrings = ClassStrings; 368 NumClasses = NC; 369 RegUnitRoots = RURoots; 370 NumRegUnits = NRU; 371 SubRegIndices = SubIndices; 372 NumSubRegIndices = NumIndices; 373 SubRegIdxRanges = SubIdxRanges; 374 RegEncodingTable = RET; 375 376 // Initialize DWARF register mapping variables 377 EHL2DwarfRegs = nullptr; 378 EHL2DwarfRegsSize = 0; 379 L2DwarfRegs = nullptr; 380 L2DwarfRegsSize = 0; 381 EHDwarf2LRegs = nullptr; 382 EHDwarf2LRegsSize = 0; 383 Dwarf2LRegs = nullptr; 384 Dwarf2LRegsSize = 0; 385 } 386 387 /// Used to initialize LLVM register to Dwarf 388 /// register number mapping. Called by TableGen auto-generated routines. 389 /// *DO NOT USE*. 390 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, 391 bool isEH) { 392 if (isEH) { 393 EHL2DwarfRegs = Map; 394 EHL2DwarfRegsSize = Size; 395 } else { 396 L2DwarfRegs = Map; 397 L2DwarfRegsSize = Size; 398 } 399 } 400 401 /// Used to initialize Dwarf register to LLVM 402 /// register number mapping. Called by TableGen auto-generated routines. 403 /// *DO NOT USE*. 404 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, 405 bool isEH) { 406 if (isEH) { 407 EHDwarf2LRegs = Map; 408 EHDwarf2LRegsSize = Size; 409 } else { 410 Dwarf2LRegs = Map; 411 Dwarf2LRegsSize = Size; 412 } 413 } 414 415 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 416 /// number mapping. By default the SEH register number is just the same 417 /// as the LLVM register number. 418 /// FIXME: TableGen these numbers. Currently this requires target specific 419 /// initialization code. 420 void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) { 421 L2SEHRegs[LLVMReg] = SEHReg; 422 } 423 424 void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) { 425 L2CVRegs[LLVMReg] = CVReg; 426 } 427 428 /// This method should return the register where the return 429 /// address can be found. 430 MCRegister getRARegister() const { 431 return RAReg; 432 } 433 434 /// Return the register which is the program counter. 435 MCRegister getProgramCounter() const { 436 return PCReg; 437 } 438 439 const MCRegisterDesc &operator[](MCRegister RegNo) const { 440 assert(RegNo < NumRegs && 441 "Attempting to access record for invalid register number!"); 442 return Desc[RegNo]; 443 } 444 445 /// Provide a get method, equivalent to [], but more useful with a 446 /// pointer to this object. 447 const MCRegisterDesc &get(MCRegister RegNo) const { 448 return operator[](RegNo); 449 } 450 451 /// Returns the physical register number of sub-register "Index" 452 /// for physical register RegNo. Return zero if the sub-register does not 453 /// exist. 454 MCRegister getSubReg(MCRegister Reg, unsigned Idx) const; 455 456 /// Return a super-register of the specified register 457 /// Reg so its sub-register of index SubIdx is Reg. 458 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, 459 const MCRegisterClass *RC) const; 460 461 /// For a given register pair, return the sub-register index 462 /// if the second register is a sub-register of the first. Return zero 463 /// otherwise. 464 unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const; 465 466 /// Get the size of the bit range covered by a sub-register index. 467 /// If the index isn't continuous, return the sum of the sizes of its parts. 468 /// If the index is used to access subregisters of different sizes, return -1. 469 unsigned getSubRegIdxSize(unsigned Idx) const; 470 471 /// Get the offset of the bit range covered by a sub-register index. 472 /// If an Offset doesn't make sense (the index isn't continuous, or is used to 473 /// access sub-registers at different offsets), return -1. 474 unsigned getSubRegIdxOffset(unsigned Idx) const; 475 476 /// Return the human-readable symbolic target-specific name for the 477 /// specified physical register. 478 const char *getName(MCRegister RegNo) const { 479 return RegStrings + get(RegNo).Name; 480 } 481 482 /// Return the number of registers this target has (useful for 483 /// sizing arrays holding per register information) 484 unsigned getNumRegs() const { 485 return NumRegs; 486 } 487 488 /// Return the number of sub-register indices 489 /// understood by the target. Index 0 is reserved for the no-op sub-register, 490 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers. 491 unsigned getNumSubRegIndices() const { 492 return NumSubRegIndices; 493 } 494 495 /// Return the number of (native) register units in the 496 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They 497 /// can be accessed through MCRegUnitIterator defined below. 498 unsigned getNumRegUnits() const { 499 return NumRegUnits; 500 } 501 502 /// Map a target register to an equivalent dwarf register 503 /// number. Returns -1 if there is no equivalent value. The second 504 /// parameter allows targets to use different numberings for EH info and 505 /// debugging info. 506 int getDwarfRegNum(MCRegister RegNum, bool isEH) const; 507 508 /// Map a dwarf register back to a target register. Returns None is there is 509 /// no mapping. 510 Optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const; 511 512 /// Map a target EH register number to an equivalent DWARF register 513 /// number. 514 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const; 515 516 /// Map a target register to an equivalent SEH register 517 /// number. Returns LLVM register number if there is no equivalent value. 518 int getSEHRegNum(MCRegister RegNum) const; 519 520 /// Map a target register to an equivalent CodeView register 521 /// number. 522 int getCodeViewRegNum(MCRegister RegNum) const; 523 524 regclass_iterator regclass_begin() const { return Classes; } 525 regclass_iterator regclass_end() const { return Classes+NumClasses; } 526 iterator_range<regclass_iterator> regclasses() const { 527 return make_range(regclass_begin(), regclass_end()); 528 } 529 530 unsigned getNumRegClasses() const { 531 return (unsigned)(regclass_end()-regclass_begin()); 532 } 533 534 /// Returns the register class associated with the enumeration 535 /// value. See class MCOperandInfo. 536 const MCRegisterClass& getRegClass(unsigned i) const { 537 assert(i < getNumRegClasses() && "Register Class ID out of range"); 538 return Classes[i]; 539 } 540 541 const char *getRegClassName(const MCRegisterClass *Class) const { 542 return RegClassStrings + Class->NameIdx; 543 } 544 545 /// Returns the encoding for RegNo 546 uint16_t getEncodingValue(MCRegister RegNo) const { 547 assert(RegNo < NumRegs && 548 "Attempting to get encoding for invalid register number!"); 549 return RegEncodingTable[RegNo]; 550 } 551 552 /// Returns true if RegB is a sub-register of RegA. 553 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { 554 return isSuperRegister(RegB, RegA); 555 } 556 557 /// Returns true if RegB is a super-register of RegA. 558 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const; 559 560 /// Returns true if RegB is a sub-register of RegA or if RegB == RegA. 561 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { 562 return isSuperRegisterEq(RegB, RegA); 563 } 564 565 /// Returns true if RegB is a super-register of RegA or if 566 /// RegB == RegA. 567 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { 568 return RegA == RegB || isSuperRegister(RegA, RegB); 569 } 570 571 /// Returns true if RegB is a super-register or sub-register of RegA 572 /// or if RegB == RegA. 573 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { 574 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); 575 } 576 }; 577 578 //===----------------------------------------------------------------------===// 579 // Register List Iterators 580 //===----------------------------------------------------------------------===// 581 582 // MCRegisterInfo provides lists of super-registers, sub-registers, and 583 // aliasing registers. Use these iterator classes to traverse the lists. 584 585 /// MCSubRegIterator enumerates all sub-registers of Reg. 586 /// If IncludeSelf is set, Reg itself is included in the list. 587 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator { 588 public: 589 MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, 590 bool IncludeSelf = false) { 591 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs); 592 // Initially, the iterator points to Reg itself. 593 if (!IncludeSelf) 594 ++*this; 595 } 596 }; 597 598 /// Iterator that enumerates the sub-registers of a Reg and the associated 599 /// sub-register indices. 600 class MCSubRegIndexIterator { 601 MCSubRegIterator SRIter; 602 const uint16_t *SRIndex; 603 604 public: 605 /// Constructs an iterator that traverses subregisters and their 606 /// associated subregister indices. 607 MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI) 608 : SRIter(Reg, MCRI) { 609 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; 610 } 611 612 /// Returns current sub-register. 613 MCRegister getSubReg() const { 614 return *SRIter; 615 } 616 617 /// Returns sub-register index of the current sub-register. 618 unsigned getSubRegIndex() const { 619 return *SRIndex; 620 } 621 622 /// Returns true if this iterator is not yet at the end. 623 bool isValid() const { return SRIter.isValid(); } 624 625 /// Moves to the next position. 626 void operator++() { 627 ++SRIter; 628 ++SRIndex; 629 } 630 }; 631 632 /// MCSuperRegIterator enumerates all super-registers of Reg. 633 /// If IncludeSelf is set, Reg itself is included in the list. 634 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator { 635 public: 636 MCSuperRegIterator() = default; 637 638 MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, 639 bool IncludeSelf = false) { 640 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs); 641 // Initially, the iterator points to Reg itself. 642 if (!IncludeSelf) 643 ++*this; 644 } 645 }; 646 647 // Definition for isSuperRegister. Put it down here since it needs the 648 // iterator defined above in addition to the MCRegisterInfo class itself. 649 inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{ 650 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I) 651 if (*I == RegB) 652 return true; 653 return false; 654 } 655 656 //===----------------------------------------------------------------------===// 657 // Register Units 658 //===----------------------------------------------------------------------===// 659 660 // Register units are used to compute register aliasing. Every register has at 661 // least one register unit, but it can have more. Two registers overlap if and 662 // only if they have a common register unit. 663 // 664 // A target with a complicated sub-register structure will typically have many 665 // fewer register units than actual registers. MCRI::getNumRegUnits() returns 666 // the number of register units in the target. 667 668 // MCRegUnitIterator enumerates a list of register units for Reg. The list is 669 // in ascending numerical order. 670 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator { 671 public: 672 /// MCRegUnitIterator - Create an iterator that traverses the register units 673 /// in Reg. 674 MCRegUnitIterator() = default; 675 676 MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) { 677 assert(Reg && "Null register has no regunits"); 678 // Decode the RegUnits MCRegisterDesc field. 679 unsigned RU = MCRI->get(Reg).RegUnits; 680 unsigned Scale = RU & 15; 681 unsigned Offset = RU >> 4; 682 683 // Initialize the iterator to Reg * Scale, and the List pointer to 684 // DiffLists + Offset. 685 init(Reg * Scale, MCRI->DiffLists + Offset); 686 687 // That may not be a valid unit, we need to advance by one to get the real 688 // unit number. The first differential can be 0 which would normally 689 // terminate the list, but since we know every register has at least one 690 // unit, we can allow a 0 differential here. 691 advance(); 692 } 693 }; 694 695 /// MCRegUnitMaskIterator enumerates a list of register units and their 696 /// associated lane masks for Reg. The register units are in ascending 697 /// numerical order. 698 class MCRegUnitMaskIterator { 699 MCRegUnitIterator RUIter; 700 const LaneBitmask *MaskListIter; 701 702 public: 703 MCRegUnitMaskIterator() = default; 704 705 /// Constructs an iterator that traverses the register units and their 706 /// associated LaneMasks in Reg. 707 MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI) 708 : RUIter(Reg, MCRI) { 709 uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks; 710 MaskListIter = &MCRI->RegUnitMaskSequences[Idx]; 711 } 712 713 /// Returns a (RegUnit, LaneMask) pair. 714 std::pair<unsigned,LaneBitmask> operator*() const { 715 return std::make_pair(*RUIter, *MaskListIter); 716 } 717 718 /// Returns true if this iterator is not yet at the end. 719 bool isValid() const { return RUIter.isValid(); } 720 721 /// Moves to the next position. 722 void operator++() { 723 ++MaskListIter; 724 ++RUIter; 725 } 726 }; 727 728 // Each register unit has one or two root registers. The complete set of 729 // registers containing a register unit is the union of the roots and their 730 // super-registers. All registers aliasing Unit can be visited like this: 731 // 732 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { 733 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI) 734 // visit(*SI); 735 // } 736 737 /// MCRegUnitRootIterator enumerates the root registers of a register unit. 738 class MCRegUnitRootIterator { 739 uint16_t Reg0 = 0; 740 uint16_t Reg1 = 0; 741 742 public: 743 MCRegUnitRootIterator() = default; 744 745 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { 746 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); 747 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; 748 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; 749 } 750 751 /// Dereference to get the current root register. 752 unsigned operator*() const { 753 return Reg0; 754 } 755 756 /// Check if the iterator is at the end of the list. 757 bool isValid() const { 758 return Reg0; 759 } 760 761 /// Preincrement to move to the next root register. 762 void operator++() { 763 assert(isValid() && "Cannot move off the end of the list."); 764 Reg0 = Reg1; 765 Reg1 = 0; 766 } 767 }; 768 769 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is 770 /// set, Reg itself is included in the list. This iterator does not guarantee 771 /// any ordering or that entries are unique. 772 class MCRegAliasIterator { 773 private: 774 MCRegister Reg; 775 const MCRegisterInfo *MCRI; 776 bool IncludeSelf; 777 778 MCRegUnitIterator RI; 779 MCRegUnitRootIterator RRI; 780 MCSuperRegIterator SI; 781 782 public: 783 MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI, 784 bool IncludeSelf) 785 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) { 786 // Initialize the iterators. 787 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) { 788 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) { 789 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) { 790 if (!(!IncludeSelf && Reg == *SI)) 791 return; 792 } 793 } 794 } 795 } 796 797 bool isValid() const { return RI.isValid(); } 798 799 MCRegister operator*() const { 800 assert(SI.isValid() && "Cannot dereference an invalid iterator."); 801 return *SI; 802 } 803 804 void advance() { 805 // Assuming SI is valid. 806 ++SI; 807 if (SI.isValid()) return; 808 809 ++RRI; 810 if (RRI.isValid()) { 811 SI = MCSuperRegIterator(*RRI, MCRI, true); 812 return; 813 } 814 815 ++RI; 816 if (RI.isValid()) { 817 RRI = MCRegUnitRootIterator(*RI, MCRI); 818 SI = MCSuperRegIterator(*RRI, MCRI, true); 819 } 820 } 821 822 void operator++() { 823 assert(isValid() && "Cannot move off the end of the list."); 824 do advance(); 825 while (!IncludeSelf && isValid() && *SI == Reg); 826 } 827 }; 828 829 } // end namespace llvm 830 831 #endif // LLVM_MC_MCREGISTERINFO_H 832