10b57cec5SDimitry Andric //===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file defines the classes used to describe a subtarget's machine model 100b57cec5SDimitry Andric // for scheduling and other instruction cost heuristics. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_MC_MCSCHEDULE_H 150b57cec5SDimitry Andric #define LLVM_MC_MCSCHEDULE_H 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric #include "llvm/ADT/ArrayRef.h" 180b57cec5SDimitry Andric #include "llvm/ADT/Optional.h" 190b57cec5SDimitry Andric #include "llvm/Config/llvm-config.h" 200b57cec5SDimitry Andric #include "llvm/Support/DataTypes.h" 210b57cec5SDimitry Andric #include <cassert> 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric namespace llvm { 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric struct InstrItinerary; 260b57cec5SDimitry Andric class MCSubtargetInfo; 270b57cec5SDimitry Andric class MCInstrInfo; 280b57cec5SDimitry Andric class MCInst; 290b57cec5SDimitry Andric class InstrItineraryData; 300b57cec5SDimitry Andric 310b57cec5SDimitry Andric /// Define a kind of processor resource that will be modeled by the scheduler. 320b57cec5SDimitry Andric struct MCProcResourceDesc { 330b57cec5SDimitry Andric const char *Name; 340b57cec5SDimitry Andric unsigned NumUnits; // Number of resource of this kind 350b57cec5SDimitry Andric unsigned SuperIdx; // Index of the resources kind that contains this kind. 360b57cec5SDimitry Andric 370b57cec5SDimitry Andric // Number of resources that may be buffered. 380b57cec5SDimitry Andric // 390b57cec5SDimitry Andric // Buffered resources (BufferSize != 0) may be consumed at some indeterminate 400b57cec5SDimitry Andric // cycle after dispatch. This should be used for out-of-order cpus when 410b57cec5SDimitry Andric // instructions that use this resource can be buffered in a reservaton 420b57cec5SDimitry Andric // station. 430b57cec5SDimitry Andric // 440b57cec5SDimitry Andric // Unbuffered resources (BufferSize == 0) always consume their resource some 450b57cec5SDimitry Andric // fixed number of cycles after dispatch. If a resource is unbuffered, then 460b57cec5SDimitry Andric // the scheduler will avoid scheduling instructions with conflicting resources 470b57cec5SDimitry Andric // in the same cycle. This is for in-order cpus, or the in-order portion of 480b57cec5SDimitry Andric // an out-of-order cpus. 490b57cec5SDimitry Andric int BufferSize; 500b57cec5SDimitry Andric 510b57cec5SDimitry Andric // If the resource has sub-units, a pointer to the first element of an array 520b57cec5SDimitry Andric // of `NumUnits` elements containing the ProcResourceIdx of the sub units. 530b57cec5SDimitry Andric // nullptr if the resource does not have sub-units. 540b57cec5SDimitry Andric const unsigned *SubUnitsIdxBegin; 550b57cec5SDimitry Andric 560b57cec5SDimitry Andric bool operator==(const MCProcResourceDesc &Other) const { 570b57cec5SDimitry Andric return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx 580b57cec5SDimitry Andric && BufferSize == Other.BufferSize; 590b57cec5SDimitry Andric } 600b57cec5SDimitry Andric }; 610b57cec5SDimitry Andric 620b57cec5SDimitry Andric /// Identify one of the processor resource kinds consumed by a particular 630b57cec5SDimitry Andric /// scheduling class for the specified number of cycles. 640b57cec5SDimitry Andric struct MCWriteProcResEntry { 650b57cec5SDimitry Andric uint16_t ProcResourceIdx; 660b57cec5SDimitry Andric uint16_t Cycles; 670b57cec5SDimitry Andric 680b57cec5SDimitry Andric bool operator==(const MCWriteProcResEntry &Other) const { 690b57cec5SDimitry Andric return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles; 700b57cec5SDimitry Andric } 710b57cec5SDimitry Andric }; 720b57cec5SDimitry Andric 730b57cec5SDimitry Andric /// Specify the latency in cpu cycles for a particular scheduling class and def 740b57cec5SDimitry Andric /// index. -1 indicates an invalid latency. Heuristics would typically consider 750b57cec5SDimitry Andric /// an instruction with invalid latency to have infinite latency. Also identify 760b57cec5SDimitry Andric /// the WriteResources of this def. When the operand expands to a sequence of 770b57cec5SDimitry Andric /// writes, this ID is the last write in the sequence. 780b57cec5SDimitry Andric struct MCWriteLatencyEntry { 790b57cec5SDimitry Andric int16_t Cycles; 800b57cec5SDimitry Andric uint16_t WriteResourceID; 810b57cec5SDimitry Andric 820b57cec5SDimitry Andric bool operator==(const MCWriteLatencyEntry &Other) const { 830b57cec5SDimitry Andric return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID; 840b57cec5SDimitry Andric } 850b57cec5SDimitry Andric }; 860b57cec5SDimitry Andric 870b57cec5SDimitry Andric /// Specify the number of cycles allowed after instruction issue before a 880b57cec5SDimitry Andric /// particular use operand reads its registers. This effectively reduces the 890b57cec5SDimitry Andric /// write's latency. Here we allow negative cycles for corner cases where 900b57cec5SDimitry Andric /// latency increases. This rule only applies when the entry's WriteResource 910b57cec5SDimitry Andric /// matches the write's WriteResource. 920b57cec5SDimitry Andric /// 930b57cec5SDimitry Andric /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by 940b57cec5SDimitry Andric /// WriteResourceIdx. 950b57cec5SDimitry Andric struct MCReadAdvanceEntry { 960b57cec5SDimitry Andric unsigned UseIdx; 970b57cec5SDimitry Andric unsigned WriteResourceID; 980b57cec5SDimitry Andric int Cycles; 990b57cec5SDimitry Andric 1000b57cec5SDimitry Andric bool operator==(const MCReadAdvanceEntry &Other) const { 1010b57cec5SDimitry Andric return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID 1020b57cec5SDimitry Andric && Cycles == Other.Cycles; 1030b57cec5SDimitry Andric } 1040b57cec5SDimitry Andric }; 1050b57cec5SDimitry Andric 1060b57cec5SDimitry Andric /// Summarize the scheduling resources required for an instruction of a 1070b57cec5SDimitry Andric /// particular scheduling class. 1080b57cec5SDimitry Andric /// 1090b57cec5SDimitry Andric /// Defined as an aggregate struct for creating tables with initializer lists. 1100b57cec5SDimitry Andric struct MCSchedClassDesc { 1110b57cec5SDimitry Andric static const unsigned short InvalidNumMicroOps = (1U << 14) - 1; 1120b57cec5SDimitry Andric static const unsigned short VariantNumMicroOps = InvalidNumMicroOps - 1; 1130b57cec5SDimitry Andric 1140b57cec5SDimitry Andric #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 1150b57cec5SDimitry Andric const char* Name; 1160b57cec5SDimitry Andric #endif 1170b57cec5SDimitry Andric uint16_t NumMicroOps : 14; 1180b57cec5SDimitry Andric bool BeginGroup : 1; 1190b57cec5SDimitry Andric bool EndGroup : 1; 1200b57cec5SDimitry Andric uint16_t WriteProcResIdx; // First index into WriteProcResTable. 1210b57cec5SDimitry Andric uint16_t NumWriteProcResEntries; 1220b57cec5SDimitry Andric uint16_t WriteLatencyIdx; // First index into WriteLatencyTable. 1230b57cec5SDimitry Andric uint16_t NumWriteLatencyEntries; 1240b57cec5SDimitry Andric uint16_t ReadAdvanceIdx; // First index into ReadAdvanceTable. 1250b57cec5SDimitry Andric uint16_t NumReadAdvanceEntries; 1260b57cec5SDimitry Andric 1270b57cec5SDimitry Andric bool isValid() const { 1280b57cec5SDimitry Andric return NumMicroOps != InvalidNumMicroOps; 1290b57cec5SDimitry Andric } 1300b57cec5SDimitry Andric bool isVariant() const { 1310b57cec5SDimitry Andric return NumMicroOps == VariantNumMicroOps; 1320b57cec5SDimitry Andric } 1330b57cec5SDimitry Andric }; 1340b57cec5SDimitry Andric 1350b57cec5SDimitry Andric /// Specify the cost of a register definition in terms of number of physical 1360b57cec5SDimitry Andric /// register allocated at register renaming stage. For example, AMD Jaguar. 1370b57cec5SDimitry Andric /// natively supports 128-bit data types, and operations on 256-bit registers 1380b57cec5SDimitry Andric /// (i.e. YMM registers) are internally split into two COPs (complex operations) 1390b57cec5SDimitry Andric /// and each COP updates a physical register. Basically, on Jaguar, a YMM 1400b57cec5SDimitry Andric /// register write effectively consumes two physical registers. That means, 1410b57cec5SDimitry Andric /// the cost of a YMM write in the BtVer2 model is 2. 1420b57cec5SDimitry Andric struct MCRegisterCostEntry { 1430b57cec5SDimitry Andric unsigned RegisterClassID; 1440b57cec5SDimitry Andric unsigned Cost; 1450b57cec5SDimitry Andric bool AllowMoveElimination; 1460b57cec5SDimitry Andric }; 1470b57cec5SDimitry Andric 1480b57cec5SDimitry Andric /// A register file descriptor. 1490b57cec5SDimitry Andric /// 1500b57cec5SDimitry Andric /// This struct allows to describe processor register files. In particular, it 1510b57cec5SDimitry Andric /// helps describing the size of the register file, as well as the cost of 1520b57cec5SDimitry Andric /// allocating a register file at register renaming stage. 1530b57cec5SDimitry Andric /// FIXME: this struct can be extended to provide information about the number 1540b57cec5SDimitry Andric /// of read/write ports to the register file. A value of zero for field 1550b57cec5SDimitry Andric /// 'NumPhysRegs' means: this register file has an unbounded number of physical 1560b57cec5SDimitry Andric /// registers. 1570b57cec5SDimitry Andric struct MCRegisterFileDesc { 1580b57cec5SDimitry Andric const char *Name; 1590b57cec5SDimitry Andric uint16_t NumPhysRegs; 1600b57cec5SDimitry Andric uint16_t NumRegisterCostEntries; 1610b57cec5SDimitry Andric // Index of the first cost entry in MCExtraProcessorInfo::RegisterCostTable. 1620b57cec5SDimitry Andric uint16_t RegisterCostEntryIdx; 1630b57cec5SDimitry Andric // A value of zero means: there is no limit in the number of moves that can be 1640b57cec5SDimitry Andric // eliminated every cycle. 1650b57cec5SDimitry Andric uint16_t MaxMovesEliminatedPerCycle; 1660b57cec5SDimitry Andric // Ture if this register file only knows how to optimize register moves from 1670b57cec5SDimitry Andric // known zero registers. 1680b57cec5SDimitry Andric bool AllowZeroMoveEliminationOnly; 1690b57cec5SDimitry Andric }; 1700b57cec5SDimitry Andric 1710b57cec5SDimitry Andric /// Provide extra details about the machine processor. 1720b57cec5SDimitry Andric /// 1730b57cec5SDimitry Andric /// This is a collection of "optional" processor information that is not 1740b57cec5SDimitry Andric /// normally used by the LLVM machine schedulers, but that can be consumed by 1750b57cec5SDimitry Andric /// external tools like llvm-mca to improve the quality of the peformance 1760b57cec5SDimitry Andric /// analysis. 1770b57cec5SDimitry Andric struct MCExtraProcessorInfo { 1780b57cec5SDimitry Andric // Actual size of the reorder buffer in hardware. 1790b57cec5SDimitry Andric unsigned ReorderBufferSize; 1800b57cec5SDimitry Andric // Number of instructions retired per cycle. 1810b57cec5SDimitry Andric unsigned MaxRetirePerCycle; 1820b57cec5SDimitry Andric const MCRegisterFileDesc *RegisterFiles; 1830b57cec5SDimitry Andric unsigned NumRegisterFiles; 1840b57cec5SDimitry Andric const MCRegisterCostEntry *RegisterCostTable; 1850b57cec5SDimitry Andric unsigned NumRegisterCostEntries; 1860b57cec5SDimitry Andric unsigned LoadQueueID; 1870b57cec5SDimitry Andric unsigned StoreQueueID; 1880b57cec5SDimitry Andric }; 1890b57cec5SDimitry Andric 1900b57cec5SDimitry Andric /// Machine model for scheduling, bundling, and heuristics. 1910b57cec5SDimitry Andric /// 1920b57cec5SDimitry Andric /// The machine model directly provides basic information about the 1930b57cec5SDimitry Andric /// microarchitecture to the scheduler in the form of properties. It also 1940b57cec5SDimitry Andric /// optionally refers to scheduler resource tables and itinerary 1950b57cec5SDimitry Andric /// tables. Scheduler resource tables model the latency and cost for each 1960b57cec5SDimitry Andric /// instruction type. Itinerary tables are an independent mechanism that 1970b57cec5SDimitry Andric /// provides a detailed reservation table describing each cycle of instruction 1980b57cec5SDimitry Andric /// execution. Subtargets may define any or all of the above categories of data 1990b57cec5SDimitry Andric /// depending on the type of CPU and selected scheduler. 2000b57cec5SDimitry Andric /// 2010b57cec5SDimitry Andric /// The machine independent properties defined here are used by the scheduler as 2020b57cec5SDimitry Andric /// an abstract machine model. A real micro-architecture has a number of 2030b57cec5SDimitry Andric /// buffers, queues, and stages. Declaring that a given machine-independent 2040b57cec5SDimitry Andric /// abstract property corresponds to a specific physical property across all 2050b57cec5SDimitry Andric /// subtargets can't be done. Nonetheless, the abstract model is 2060b57cec5SDimitry Andric /// useful. Futhermore, subtargets typically extend this model with processor 2070b57cec5SDimitry Andric /// specific resources to model any hardware features that can be exploited by 2080b57cec5SDimitry Andric /// sceduling heuristics and aren't sufficiently represented in the abstract. 2090b57cec5SDimitry Andric /// 2100b57cec5SDimitry Andric /// The abstract pipeline is built around the notion of an "issue point". This 2110b57cec5SDimitry Andric /// is merely a reference point for counting machine cycles. The physical 2120b57cec5SDimitry Andric /// machine will have pipeline stages that delay execution. The scheduler does 2130b57cec5SDimitry Andric /// not model those delays because they are irrelevant as long as they are 2140b57cec5SDimitry Andric /// consistent. Inaccuracies arise when instructions have different execution 2150b57cec5SDimitry Andric /// delays relative to each other, in addition to their intrinsic latency. Those 2160b57cec5SDimitry Andric /// special cases can be handled by TableGen constructs such as, ReadAdvance, 2170b57cec5SDimitry Andric /// which reduces latency when reading data, and ResourceCycles, which consumes 2180b57cec5SDimitry Andric /// a processor resource when writing data for a number of abstract 2190b57cec5SDimitry Andric /// cycles. 2200b57cec5SDimitry Andric /// 2210b57cec5SDimitry Andric /// TODO: One tool currently missing is the ability to add a delay to 2220b57cec5SDimitry Andric /// ResourceCycles. That would be easy to add and would likely cover all cases 2230b57cec5SDimitry Andric /// currently handled by the legacy itinerary tables. 2240b57cec5SDimitry Andric /// 2250b57cec5SDimitry Andric /// A note on out-of-order execution and, more generally, instruction 2260b57cec5SDimitry Andric /// buffers. Part of the CPU pipeline is always in-order. The issue point, which 2270b57cec5SDimitry Andric /// is the point of reference for counting cycles, only makes sense as an 2280b57cec5SDimitry Andric /// in-order part of the pipeline. Other parts of the pipeline are sometimes 2290b57cec5SDimitry Andric /// falling behind and sometimes catching up. It's only interesting to model 2300b57cec5SDimitry Andric /// those other, decoupled parts of the pipeline if they may be predictably 2310b57cec5SDimitry Andric /// resource constrained in a way that the scheduler can exploit. 2320b57cec5SDimitry Andric /// 2330b57cec5SDimitry Andric /// The LLVM machine model distinguishes between in-order constraints and 2340b57cec5SDimitry Andric /// out-of-order constraints so that the target's scheduling strategy can apply 2350b57cec5SDimitry Andric /// appropriate heuristics. For a well-balanced CPU pipeline, out-of-order 2360b57cec5SDimitry Andric /// resources would not typically be treated as a hard scheduling 2370b57cec5SDimitry Andric /// constraint. For example, in the GenericScheduler, a delay caused by limited 2380b57cec5SDimitry Andric /// out-of-order resources is not directly reflected in the number of cycles 2390b57cec5SDimitry Andric /// that the scheduler sees between issuing an instruction and its dependent 2400b57cec5SDimitry Andric /// instructions. In other words, out-of-order resources don't directly increase 2410b57cec5SDimitry Andric /// the latency between pairs of instructions. However, they can still be used 2420b57cec5SDimitry Andric /// to detect potential bottlenecks across a sequence of instructions and bias 2430b57cec5SDimitry Andric /// the scheduling heuristics appropriately. 2440b57cec5SDimitry Andric struct MCSchedModel { 2450b57cec5SDimitry Andric // IssueWidth is the maximum number of instructions that may be scheduled in 2460b57cec5SDimitry Andric // the same per-cycle group. This is meant to be a hard in-order constraint 2470b57cec5SDimitry Andric // (a.k.a. "hazard"). In the GenericScheduler strategy, no more than 2480b57cec5SDimitry Andric // IssueWidth micro-ops can ever be scheduled in a particular cycle. 2490b57cec5SDimitry Andric // 2500b57cec5SDimitry Andric // In practice, IssueWidth is useful to model any bottleneck between the 2510b57cec5SDimitry Andric // decoder (after micro-op expansion) and the out-of-order reservation 2520b57cec5SDimitry Andric // stations or the decoder bandwidth itself. If the total number of 2530b57cec5SDimitry Andric // reservation stations is also a bottleneck, or if any other pipeline stage 2540b57cec5SDimitry Andric // has a bandwidth limitation, then that can be naturally modeled by adding an 2550b57cec5SDimitry Andric // out-of-order processor resource. 2560b57cec5SDimitry Andric unsigned IssueWidth; 2570b57cec5SDimitry Andric static const unsigned DefaultIssueWidth = 1; 2580b57cec5SDimitry Andric 2590b57cec5SDimitry Andric // MicroOpBufferSize is the number of micro-ops that the processor may buffer 2600b57cec5SDimitry Andric // for out-of-order execution. 2610b57cec5SDimitry Andric // 2620b57cec5SDimitry Andric // "0" means operations that are not ready in this cycle are not considered 2630b57cec5SDimitry Andric // for scheduling (they go in the pending queue). Latency is paramount. This 2640b57cec5SDimitry Andric // may be more efficient if many instructions are pending in a schedule. 2650b57cec5SDimitry Andric // 2660b57cec5SDimitry Andric // "1" means all instructions are considered for scheduling regardless of 2670b57cec5SDimitry Andric // whether they are ready in this cycle. Latency still causes issue stalls, 2680b57cec5SDimitry Andric // but we balance those stalls against other heuristics. 2690b57cec5SDimitry Andric // 2700b57cec5SDimitry Andric // "> 1" means the processor is out-of-order. This is a machine independent 2710b57cec5SDimitry Andric // estimate of highly machine specific characteristics such as the register 2720b57cec5SDimitry Andric // renaming pool and reorder buffer. 2730b57cec5SDimitry Andric unsigned MicroOpBufferSize; 2740b57cec5SDimitry Andric static const unsigned DefaultMicroOpBufferSize = 0; 2750b57cec5SDimitry Andric 2760b57cec5SDimitry Andric // LoopMicroOpBufferSize is the number of micro-ops that the processor may 2770b57cec5SDimitry Andric // buffer for optimized loop execution. More generally, this represents the 2780b57cec5SDimitry Andric // optimal number of micro-ops in a loop body. A loop may be partially 2790b57cec5SDimitry Andric // unrolled to bring the count of micro-ops in the loop body closer to this 2800b57cec5SDimitry Andric // number. 2810b57cec5SDimitry Andric unsigned LoopMicroOpBufferSize; 2820b57cec5SDimitry Andric static const unsigned DefaultLoopMicroOpBufferSize = 0; 2830b57cec5SDimitry Andric 2840b57cec5SDimitry Andric // LoadLatency is the expected latency of load instructions. 2850b57cec5SDimitry Andric unsigned LoadLatency; 2860b57cec5SDimitry Andric static const unsigned DefaultLoadLatency = 4; 2870b57cec5SDimitry Andric 2880b57cec5SDimitry Andric // HighLatency is the expected latency of "very high latency" operations. 2890b57cec5SDimitry Andric // See TargetInstrInfo::isHighLatencyDef(). 2900b57cec5SDimitry Andric // By default, this is set to an arbitrarily high number of cycles 2910b57cec5SDimitry Andric // likely to have some impact on scheduling heuristics. 2920b57cec5SDimitry Andric unsigned HighLatency; 2930b57cec5SDimitry Andric static const unsigned DefaultHighLatency = 10; 2940b57cec5SDimitry Andric 2950b57cec5SDimitry Andric // MispredictPenalty is the typical number of extra cycles the processor 2960b57cec5SDimitry Andric // takes to recover from a branch misprediction. 2970b57cec5SDimitry Andric unsigned MispredictPenalty; 2980b57cec5SDimitry Andric static const unsigned DefaultMispredictPenalty = 10; 2990b57cec5SDimitry Andric 3000b57cec5SDimitry Andric bool PostRAScheduler; // default value is false 3010b57cec5SDimitry Andric 3020b57cec5SDimitry Andric bool CompleteModel; 3030b57cec5SDimitry Andric 3040b57cec5SDimitry Andric unsigned ProcID; 3050b57cec5SDimitry Andric const MCProcResourceDesc *ProcResourceTable; 3060b57cec5SDimitry Andric const MCSchedClassDesc *SchedClassTable; 3070b57cec5SDimitry Andric unsigned NumProcResourceKinds; 3080b57cec5SDimitry Andric unsigned NumSchedClasses; 3090b57cec5SDimitry Andric // Instruction itinerary tables used by InstrItineraryData. 3100b57cec5SDimitry Andric friend class InstrItineraryData; 3110b57cec5SDimitry Andric const InstrItinerary *InstrItineraries; 3120b57cec5SDimitry Andric 3130b57cec5SDimitry Andric const MCExtraProcessorInfo *ExtraProcessorInfo; 3140b57cec5SDimitry Andric 3150b57cec5SDimitry Andric bool hasExtraProcessorInfo() const { return ExtraProcessorInfo; } 3160b57cec5SDimitry Andric 3170b57cec5SDimitry Andric unsigned getProcessorID() const { return ProcID; } 3180b57cec5SDimitry Andric 3190b57cec5SDimitry Andric /// Does this machine model include instruction-level scheduling. 3200b57cec5SDimitry Andric bool hasInstrSchedModel() const { return SchedClassTable; } 3210b57cec5SDimitry Andric 3220b57cec5SDimitry Andric const MCExtraProcessorInfo &getExtraProcessorInfo() const { 3230b57cec5SDimitry Andric assert(hasExtraProcessorInfo() && 3240b57cec5SDimitry Andric "No extra information available for this model"); 3250b57cec5SDimitry Andric return *ExtraProcessorInfo; 3260b57cec5SDimitry Andric } 3270b57cec5SDimitry Andric 3280b57cec5SDimitry Andric /// Return true if this machine model data for all instructions with a 3290b57cec5SDimitry Andric /// scheduling class (itinerary class or SchedRW list). 3300b57cec5SDimitry Andric bool isComplete() const { return CompleteModel; } 3310b57cec5SDimitry Andric 3320b57cec5SDimitry Andric /// Return true if machine supports out of order execution. 3330b57cec5SDimitry Andric bool isOutOfOrder() const { return MicroOpBufferSize > 1; } 3340b57cec5SDimitry Andric 3350b57cec5SDimitry Andric unsigned getNumProcResourceKinds() const { 3360b57cec5SDimitry Andric return NumProcResourceKinds; 3370b57cec5SDimitry Andric } 3380b57cec5SDimitry Andric 3390b57cec5SDimitry Andric const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const { 3400b57cec5SDimitry Andric assert(hasInstrSchedModel() && "No scheduling machine model"); 3410b57cec5SDimitry Andric 3420b57cec5SDimitry Andric assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx"); 3430b57cec5SDimitry Andric return &ProcResourceTable[ProcResourceIdx]; 3440b57cec5SDimitry Andric } 3450b57cec5SDimitry Andric 3460b57cec5SDimitry Andric const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { 3470b57cec5SDimitry Andric assert(hasInstrSchedModel() && "No scheduling machine model"); 3480b57cec5SDimitry Andric 3490b57cec5SDimitry Andric assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx"); 3500b57cec5SDimitry Andric return &SchedClassTable[SchedClassIdx]; 3510b57cec5SDimitry Andric } 3520b57cec5SDimitry Andric 3530b57cec5SDimitry Andric /// Returns the latency value for the scheduling class. 3540b57cec5SDimitry Andric static int computeInstrLatency(const MCSubtargetInfo &STI, 3550b57cec5SDimitry Andric const MCSchedClassDesc &SCDesc); 3560b57cec5SDimitry Andric 3570b57cec5SDimitry Andric int computeInstrLatency(const MCSubtargetInfo &STI, unsigned SClass) const; 3580b57cec5SDimitry Andric int computeInstrLatency(const MCSubtargetInfo &STI, const MCInstrInfo &MCII, 3590b57cec5SDimitry Andric const MCInst &Inst) const; 3600b57cec5SDimitry Andric 3610b57cec5SDimitry Andric // Returns the reciprocal throughput information from a MCSchedClassDesc. 3620b57cec5SDimitry Andric static double 3630b57cec5SDimitry Andric getReciprocalThroughput(const MCSubtargetInfo &STI, 3640b57cec5SDimitry Andric const MCSchedClassDesc &SCDesc); 3650b57cec5SDimitry Andric 3660b57cec5SDimitry Andric static double 3670b57cec5SDimitry Andric getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID); 3680b57cec5SDimitry Andric 3690b57cec5SDimitry Andric double 3700b57cec5SDimitry Andric getReciprocalThroughput(const MCSubtargetInfo &STI, const MCInstrInfo &MCII, 3710b57cec5SDimitry Andric const MCInst &Inst) const; 3720b57cec5SDimitry Andric 3730b57cec5SDimitry Andric /// Returns the maximum forwarding delay for register reads dependent on 3740b57cec5SDimitry Andric /// writes of scheduling class WriteResourceIdx. 3750b57cec5SDimitry Andric static unsigned getForwardingDelayCycles(ArrayRef<MCReadAdvanceEntry> Entries, 3760b57cec5SDimitry Andric unsigned WriteResourceIdx = 0); 3770b57cec5SDimitry Andric 3780b57cec5SDimitry Andric /// Returns the default initialized model. 3790b57cec5SDimitry Andric static const MCSchedModel &GetDefaultSchedModel() { return Default; } 3800b57cec5SDimitry Andric static const MCSchedModel Default; 3810b57cec5SDimitry Andric }; 3820b57cec5SDimitry Andric 3830b57cec5SDimitry Andric } // namespace llvm 3840b57cec5SDimitry Andric 3850b57cec5SDimitry Andric #endif 386