1 //===---------------------- RetireStage.h -----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file defines the retire stage of a default instruction pipeline.
11 /// The RetireStage represents the process logic that interacts with the
12 /// simulated RetireControlUnit hardware.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_MCA_STAGES_RETIRESTAGE_H
17 #define LLVM_MCA_STAGES_RETIRESTAGE_H
18 
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/MCA/HardwareUnits/LSUnit.h"
21 #include "llvm/MCA/HardwareUnits/RegisterFile.h"
22 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
23 #include "llvm/MCA/Stages/Stage.h"
24 
25 namespace llvm {
26 namespace mca {
27 
28 class RetireStage final : public Stage {
29   // Owner will go away when we move listeners/eventing to the stages.
30   RetireControlUnit &RCU;
31   RegisterFile &PRF;
32   LSUnitBase &LSU;
33 
34   RetireStage(const RetireStage &Other) = delete;
35   RetireStage &operator=(const RetireStage &Other) = delete;
36 
37 public:
38   RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS)
39       : RCU(R), PRF(F), LSU(LS) {}
40 
41   bool hasWorkToComplete() const override { return !RCU.isEmpty(); }
42   Error cycleStart() override;
43   Error cycleEnd() override;
44   Error execute(InstRef &IR) override;
45   void notifyInstructionRetired(const InstRef &IR) const;
46 };
47 
48 } // namespace mca
49 } // namespace llvm
50 
51 #endif // LLVM_MCA_STAGES_RETIRESTAGE_H
52