1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// SUBREG_TO_REG - Assert the value of bits in a super register. 60/// The result of this instruction is the value of the second operand inserted 61/// into the subregister specified by the third operand. All other bits are 62/// assumed to be equal to the bits in the immediate integer constant in the 63/// first operand. This instruction just communicates information; No code 64/// should be generated. 65/// This is typically used after an instruction where the write to a subregister 66/// implicitly cleared the bits in the super registers. 67HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70/// register-to-register copy into a specific register class. This is only 71/// used between instruction selection and MachineInstr creation, before 72/// virtual registers have been created for all the instructions, and it's 73/// only needed in cases where the register classes implied by the 74/// instructions are insufficient. It is emitted as a COPY MachineInstr. 75 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic 81/// list of locations 82HANDLE_TARGET_OPCODE(DBG_VALUE_LIST) 83 84/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction 85/// that defines the value, rather than a virtual register. 86HANDLE_TARGET_OPCODE(DBG_INSTR_REF) 87 88/// DBG_PHI - remainder of a PHI, identifies a program point where values 89/// merge under control flow. 90HANDLE_TARGET_OPCODE(DBG_PHI) 91 92/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 93HANDLE_TARGET_OPCODE(DBG_LABEL) 94 95/// REG_SEQUENCE - This variadic instruction is used to form a register that 96/// represents a consecutive sequence of sub-registers. It's used as a 97/// register coalescing / allocation aid and must be eliminated before code 98/// emission. 99// In SDNode form, the first operand encodes the register class created by 100// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 101// pair. Once it has been lowered to a MachineInstr, the regclass operand 102// is no longer present. 103/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 104/// After register coalescing references of v1024 should be replace with 105/// v1027:3, v1025 with v1027:4, etc. 106 HANDLE_TARGET_OPCODE(REG_SEQUENCE) 107 108/// COPY - Target-independent register copy. This instruction can also be 109/// used to copy between subregisters of virtual registers. 110 HANDLE_TARGET_OPCODE(COPY) 111 112/// BUNDLE - This instruction represents an instruction bundle. Instructions 113/// which immediately follow a BUNDLE instruction which are marked with 114/// 'InsideBundle' flag are inside the bundle. 115HANDLE_TARGET_OPCODE(BUNDLE) 116 117/// Lifetime markers. 118HANDLE_TARGET_OPCODE(LIFETIME_START) 119HANDLE_TARGET_OPCODE(LIFETIME_END) 120 121/// Pseudo probe 122HANDLE_TARGET_OPCODE(PSEUDO_PROBE) 123 124/// Arithmetic fence. 125HANDLE_TARGET_OPCODE(ARITH_FENCE) 126 127/// A Stackmap instruction captures the location of live variables at its 128/// position in the instruction stream. It is followed by a shadow of bytes 129/// that must lie within the function and not contain another stackmap. 130HANDLE_TARGET_OPCODE(STACKMAP) 131 132/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 133HANDLE_TARGET_OPCODE(FENTRY_CALL) 134 135/// Patchable call instruction - this instruction represents a call to a 136/// constant address, followed by a series of NOPs. It is intended to 137/// support optimizations for dynamic languages (such as javascript) that 138/// rewrite calls to runtimes with more efficient code sequences. 139/// This also implies a stack map. 140HANDLE_TARGET_OPCODE(PATCHPOINT) 141 142/// This pseudo-instruction loads the stack guard value. Targets which need 143/// to prevent the stack guard value or address from being spilled to the 144/// stack should override TargetLowering::emitLoadStackGuardNode and 145/// additionally expand this pseudo after register allocation. 146HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 147 148/// These are used to support call sites that must have the stack adjusted 149/// before the call (e.g. to initialize an argument passed by value). 150/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. 151HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) 152HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) 153 154/// Call instruction with associated vm state for deoptimization and list 155/// of live pointers for relocation by the garbage collector. It is 156/// intended to support garbage collection with fully precise relocating 157/// collectors and deoptimizations in either the callee or caller. 158HANDLE_TARGET_OPCODE(STATEPOINT) 159 160/// Instruction that records the offset of a local stack allocation passed to 161/// llvm.localescape. It has two arguments: the symbol for the label and the 162/// frame index of the local stack allocation. 163HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 164 165/// Wraps a machine instruction which can fault, bundled with associated 166/// information on how to handle such a fault. 167/// For example loading instruction that may page fault, bundled with associated 168/// information on how to handle such a page fault. It is intended to support 169/// "zero cost" null checks in managed languages by allowing LLVM to fold 170/// comparisons into existing memory operations. 171HANDLE_TARGET_OPCODE(FAULTING_OP) 172 173/// Wraps a machine instruction to add patchability constraints. An 174/// instruction wrapped in PATCHABLE_OP has to either have a minimum 175/// size or be preceded with a nop of that size. The first operand is 176/// an immediate denoting the minimum size of the instruction, the 177/// second operand is an immediate denoting the opcode of the original 178/// instruction. The rest of the operands are the operands of the 179/// original instruction. 180HANDLE_TARGET_OPCODE(PATCHABLE_OP) 181 182/// This is a marker instruction which gets translated into a nop sled, useful 183/// for inserting instrumentation instructions at runtime. 184HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 185 186/// Wraps a return instruction and its operands to enable adding nop sleds 187/// either before or after the return. The nop sleds are useful for inserting 188/// instrumentation instructions at runtime. 189/// The patch here replaces the return instruction. 190HANDLE_TARGET_OPCODE(PATCHABLE_RET) 191 192/// This is a marker instruction which gets translated into a nop sled, useful 193/// for inserting instrumentation instructions at runtime. 194/// The patch here prepends the return instruction. 195/// The same thing as in x86_64 is not possible for ARM because it has multiple 196/// return instructions. Furthermore, CPU allows parametrized and even 197/// conditional return instructions. In the current ARM implementation we are 198/// making use of the fact that currently LLVM doesn't seem to generate 199/// conditional return instructions. 200/// On ARM, the same instruction can be used for popping multiple registers 201/// from the stack and returning (it just pops pc register too), and LLVM 202/// generates it sometimes. So we can't insert the sled between this stack 203/// adjustment and the return without splitting the original instruction into 2 204/// instructions. So on ARM, rather than jumping into the exit trampoline, we 205/// call it, it does the tracing, preserves the stack and returns. 206HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 207 208/// Wraps a tail call instruction and its operands to enable adding nop sleds 209/// either before or after the tail exit. We use this as a disambiguation from 210/// PATCHABLE_RET which specifically only works for return instructions. 211HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 212 213/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 214/// be patched to insert instrumentation instructions. 215HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 216 217/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 218/// can be patched to insert instrumentation instructions. 219HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 220 221HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 222 223/// The following generic opcodes are not supposed to appear after ISel. 224/// This is something we might want to relax, but for now, this is convenient 225/// to produce diagnostics. 226 227/// Instructions which should not exist past instruction selection, but do not 228/// generate code. These instructions only act as optimization hints. 229HANDLE_TARGET_OPCODE(G_ASSERT_SEXT) 230HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT) 231HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START, 232 G_ASSERT_SEXT) 233HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END, 234 G_ASSERT_ZEXT) 235 236/// Generic ADD instruction. This is an integer add. 237HANDLE_TARGET_OPCODE(G_ADD) 238HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 239 240/// Generic SUB instruction. This is an integer sub. 241HANDLE_TARGET_OPCODE(G_SUB) 242 243// Generic multiply instruction. 244HANDLE_TARGET_OPCODE(G_MUL) 245 246// Generic signed division instruction. 247HANDLE_TARGET_OPCODE(G_SDIV) 248 249// Generic unsigned division instruction. 250HANDLE_TARGET_OPCODE(G_UDIV) 251 252// Generic signed remainder instruction. 253HANDLE_TARGET_OPCODE(G_SREM) 254 255// Generic unsigned remainder instruction. 256HANDLE_TARGET_OPCODE(G_UREM) 257 258// Generic signed divrem instruction. 259HANDLE_TARGET_OPCODE(G_SDIVREM) 260 261// Generic unsigned divrem instruction. 262HANDLE_TARGET_OPCODE(G_UDIVREM) 263 264/// Generic bitwise and instruction. 265HANDLE_TARGET_OPCODE(G_AND) 266 267/// Generic bitwise or instruction. 268HANDLE_TARGET_OPCODE(G_OR) 269 270/// Generic bitwise exclusive-or instruction. 271HANDLE_TARGET_OPCODE(G_XOR) 272 273 274HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 275 276/// Generic PHI instruction with types. 277HANDLE_TARGET_OPCODE(G_PHI) 278 279/// Generic instruction to materialize the address of an alloca or other 280/// stack-based object. 281HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 282 283/// Generic reference to global value. 284HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 285 286/// Generic instruction to extract blocks of bits from the register given 287/// (typically a sub-register COPY after instruction selection). 288HANDLE_TARGET_OPCODE(G_EXTRACT) 289 290HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 291 292/// Generic instruction to insert blocks of bits from the registers given into 293/// the source. 294HANDLE_TARGET_OPCODE(G_INSERT) 295 296/// Generic instruction to paste a variable number of components together into a 297/// larger register. 298HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 299 300/// Generic instruction to create a vector value from a number of scalar 301/// components. 302HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 303 304/// Generic instruction to create a vector value from a number of scalar 305/// components, which have types larger than the result vector elt type. 306HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 307 308/// Generic instruction to create a vector by concatenating multiple vectors. 309HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 310 311/// Generic pointer to int conversion. 312HANDLE_TARGET_OPCODE(G_PTRTOINT) 313 314/// Generic int to pointer conversion. 315HANDLE_TARGET_OPCODE(G_INTTOPTR) 316 317/// Generic bitcast. The source and destination types must be different, or a 318/// COPY is the relevant instruction. 319HANDLE_TARGET_OPCODE(G_BITCAST) 320 321/// Generic freeze. 322HANDLE_TARGET_OPCODE(G_FREEZE) 323 324/// INTRINSIC trunc intrinsic. 325HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 326 327/// INTRINSIC round intrinsic. 328HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 329 330/// INTRINSIC round to integer intrinsic. 331HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT) 332 333/// INTRINSIC roundeven intrinsic. 334HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN) 335 336/// INTRINSIC readcyclecounter 337HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) 338 339/// Generic load (including anyext load) 340HANDLE_TARGET_OPCODE(G_LOAD) 341 342/// Generic signext load 343HANDLE_TARGET_OPCODE(G_SEXTLOAD) 344 345/// Generic zeroext load 346HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 347 348/// Generic indexed load (including anyext load) 349HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) 350 351/// Generic indexed signext load 352HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) 353 354/// Generic indexed zeroext load 355HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) 356 357/// Generic store. 358HANDLE_TARGET_OPCODE(G_STORE) 359 360/// Generic indexed store. 361HANDLE_TARGET_OPCODE(G_INDEXED_STORE) 362 363/// Generic atomic cmpxchg with internal success check. 364HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 365 366/// Generic atomic cmpxchg. 367HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 368 369/// Generic atomicrmw. 370HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 371HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 372HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 373HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 374HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 375HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 376HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 377HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 378HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 379HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 380HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 381HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) 382HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) 383 384// Generic atomic fence 385HANDLE_TARGET_OPCODE(G_FENCE) 386 387/// Generic conditional branch instruction. 388HANDLE_TARGET_OPCODE(G_BRCOND) 389 390/// Generic indirect branch instruction. 391HANDLE_TARGET_OPCODE(G_BRINDIRECT) 392 393/// Generic intrinsic use (without side effects). 394HANDLE_TARGET_OPCODE(G_INTRINSIC) 395 396/// Generic intrinsic use (with side effects). 397HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 398 399/// Generic extension allowing rubbish in high bits. 400HANDLE_TARGET_OPCODE(G_ANYEXT) 401 402/// Generic instruction to discard the high bits of a register. This differs 403/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 404/// each element individually, G_EXTRACT will typically discard the high 405/// elements of the vector. 406HANDLE_TARGET_OPCODE(G_TRUNC) 407 408/// Generic integer constant. 409HANDLE_TARGET_OPCODE(G_CONSTANT) 410 411/// Generic floating constant. 412HANDLE_TARGET_OPCODE(G_FCONSTANT) 413 414/// Generic va_start instruction. Stores to its one pointer operand. 415HANDLE_TARGET_OPCODE(G_VASTART) 416 417/// Generic va_start instruction. Stores to its one pointer operand. 418HANDLE_TARGET_OPCODE(G_VAARG) 419 420// Generic sign extend 421HANDLE_TARGET_OPCODE(G_SEXT) 422HANDLE_TARGET_OPCODE(G_SEXT_INREG) 423 424// Generic zero extend 425HANDLE_TARGET_OPCODE(G_ZEXT) 426 427// Generic left-shift 428HANDLE_TARGET_OPCODE(G_SHL) 429 430// Generic logical right-shift 431HANDLE_TARGET_OPCODE(G_LSHR) 432 433// Generic arithmetic right-shift 434HANDLE_TARGET_OPCODE(G_ASHR) 435 436// Generic funnel left shift 437HANDLE_TARGET_OPCODE(G_FSHL) 438 439// Generic funnel right shift 440HANDLE_TARGET_OPCODE(G_FSHR) 441 442// Generic right rotate 443HANDLE_TARGET_OPCODE(G_ROTR) 444 445// Generic left rotate 446HANDLE_TARGET_OPCODE(G_ROTL) 447 448/// Generic integer-base comparison, also applicable to vectors of integers. 449HANDLE_TARGET_OPCODE(G_ICMP) 450 451/// Generic floating-point comparison, also applicable to vectors. 452HANDLE_TARGET_OPCODE(G_FCMP) 453 454/// Generic select. 455HANDLE_TARGET_OPCODE(G_SELECT) 456 457/// Generic unsigned add instruction, consuming the normal operands and 458/// producing the result and a carry flag. 459HANDLE_TARGET_OPCODE(G_UADDO) 460 461/// Generic unsigned add instruction, consuming the normal operands plus a carry 462/// flag, and similarly producing the result and a carry flag. 463HANDLE_TARGET_OPCODE(G_UADDE) 464 465/// Generic unsigned sub instruction, consuming the normal operands and 466/// producing the result and a carry flag. 467HANDLE_TARGET_OPCODE(G_USUBO) 468 469/// Generic unsigned subtract instruction, consuming the normal operands plus a 470/// carry flag, and similarly producing the result and a carry flag. 471HANDLE_TARGET_OPCODE(G_USUBE) 472 473/// Generic signed add instruction, producing the result and a signed overflow 474/// flag. 475HANDLE_TARGET_OPCODE(G_SADDO) 476 477/// Generic signed add instruction, consuming the normal operands plus a carry 478/// flag, and similarly producing the result and a carry flag. 479HANDLE_TARGET_OPCODE(G_SADDE) 480 481/// Generic signed subtract instruction, producing the result and a signed 482/// overflow flag. 483HANDLE_TARGET_OPCODE(G_SSUBO) 484 485/// Generic signed sub instruction, consuming the normal operands plus a carry 486/// flag, and similarly producing the result and a carry flag. 487HANDLE_TARGET_OPCODE(G_SSUBE) 488 489/// Generic unsigned multiply instruction, producing the result and a signed 490/// overflow flag. 491HANDLE_TARGET_OPCODE(G_UMULO) 492 493/// Generic signed multiply instruction, producing the result and a signed 494/// overflow flag. 495HANDLE_TARGET_OPCODE(G_SMULO) 496 497// Multiply two numbers at twice the incoming bit width (unsigned) and return 498// the high half of the result. 499HANDLE_TARGET_OPCODE(G_UMULH) 500 501// Multiply two numbers at twice the incoming bit width (signed) and return 502// the high half of the result. 503HANDLE_TARGET_OPCODE(G_SMULH) 504 505/// Generic saturating unsigned addition. 506HANDLE_TARGET_OPCODE(G_UADDSAT) 507 508/// Generic saturating signed addition. 509HANDLE_TARGET_OPCODE(G_SADDSAT) 510 511/// Generic saturating unsigned subtraction. 512HANDLE_TARGET_OPCODE(G_USUBSAT) 513 514/// Generic saturating signed subtraction. 515HANDLE_TARGET_OPCODE(G_SSUBSAT) 516 517/// Generic saturating unsigned left shift. 518HANDLE_TARGET_OPCODE(G_USHLSAT) 519 520/// Generic saturating signed left shift. 521HANDLE_TARGET_OPCODE(G_SSHLSAT) 522 523// Perform signed fixed point multiplication 524HANDLE_TARGET_OPCODE(G_SMULFIX) 525 526// Perform unsigned fixed point multiplication 527HANDLE_TARGET_OPCODE(G_UMULFIX) 528 529// Perform signed, saturating fixed point multiplication 530HANDLE_TARGET_OPCODE(G_SMULFIXSAT) 531 532// Perform unsigned, saturating fixed point multiplication 533HANDLE_TARGET_OPCODE(G_UMULFIXSAT) 534 535// Perform signed fixed point division 536HANDLE_TARGET_OPCODE(G_SDIVFIX) 537 538// Perform unsigned fixed point division 539HANDLE_TARGET_OPCODE(G_UDIVFIX) 540 541// Perform signed, saturating fixed point division 542HANDLE_TARGET_OPCODE(G_SDIVFIXSAT) 543 544// Perform unsigned, saturating fixed point division 545HANDLE_TARGET_OPCODE(G_UDIVFIXSAT) 546 547/// Generic FP addition. 548HANDLE_TARGET_OPCODE(G_FADD) 549 550/// Generic FP subtraction. 551HANDLE_TARGET_OPCODE(G_FSUB) 552 553/// Generic FP multiplication. 554HANDLE_TARGET_OPCODE(G_FMUL) 555 556/// Generic FMA multiplication. Behaves like llvm fma intrinsic 557HANDLE_TARGET_OPCODE(G_FMA) 558 559/// Generic FP multiply and add. Behaves as separate fmul and fadd. 560HANDLE_TARGET_OPCODE(G_FMAD) 561 562/// Generic FP division. 563HANDLE_TARGET_OPCODE(G_FDIV) 564 565/// Generic FP remainder. 566HANDLE_TARGET_OPCODE(G_FREM) 567 568/// Generic FP exponentiation. 569HANDLE_TARGET_OPCODE(G_FPOW) 570 571/// Generic FP exponentiation, with an integer exponent. 572HANDLE_TARGET_OPCODE(G_FPOWI) 573 574/// Generic base-e exponential of a value. 575HANDLE_TARGET_OPCODE(G_FEXP) 576 577/// Generic base-2 exponential of a value. 578HANDLE_TARGET_OPCODE(G_FEXP2) 579 580/// Floating point base-e logarithm of a value. 581HANDLE_TARGET_OPCODE(G_FLOG) 582 583/// Floating point base-2 logarithm of a value. 584HANDLE_TARGET_OPCODE(G_FLOG2) 585 586/// Floating point base-10 logarithm of a value. 587HANDLE_TARGET_OPCODE(G_FLOG10) 588 589/// Generic FP negation. 590HANDLE_TARGET_OPCODE(G_FNEG) 591 592/// Generic FP extension. 593HANDLE_TARGET_OPCODE(G_FPEXT) 594 595/// Generic float to signed-int conversion 596HANDLE_TARGET_OPCODE(G_FPTRUNC) 597 598/// Generic float to signed-int conversion 599HANDLE_TARGET_OPCODE(G_FPTOSI) 600 601/// Generic float to unsigned-int conversion 602HANDLE_TARGET_OPCODE(G_FPTOUI) 603 604/// Generic signed-int to float conversion 605HANDLE_TARGET_OPCODE(G_SITOFP) 606 607/// Generic unsigned-int to float conversion 608HANDLE_TARGET_OPCODE(G_UITOFP) 609 610/// Generic FP absolute value. 611HANDLE_TARGET_OPCODE(G_FABS) 612 613/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 614/// not require that X and Y have the same type, just that they are both 615/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 616/// f64) is allowed. 617HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 618 619/// Generic FP canonicalize value. 620HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 621 622/// FP min/max matching libm's fmin/fmax 623HANDLE_TARGET_OPCODE(G_FMINNUM) 624HANDLE_TARGET_OPCODE(G_FMAXNUM) 625 626/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 627HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 628HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 629 630/// FP min/max matching IEEE-754 2018 draft semantics. 631HANDLE_TARGET_OPCODE(G_FMINIMUM) 632HANDLE_TARGET_OPCODE(G_FMAXIMUM) 633 634/// Generic pointer offset 635HANDLE_TARGET_OPCODE(G_PTR_ADD) 636 637/// Clear the specified bits in a pointer. 638HANDLE_TARGET_OPCODE(G_PTRMASK) 639 640/// Generic signed integer minimum. 641HANDLE_TARGET_OPCODE(G_SMIN) 642 643/// Generic signed integer maximum. 644HANDLE_TARGET_OPCODE(G_SMAX) 645 646/// Generic unsigned integer maximum. 647HANDLE_TARGET_OPCODE(G_UMIN) 648 649/// Generic unsigned integer maximum. 650HANDLE_TARGET_OPCODE(G_UMAX) 651 652/// Generic integer absolute value. 653HANDLE_TARGET_OPCODE(G_ABS) 654 655/// Generic BRANCH instruction. This is an unconditional branch. 656HANDLE_TARGET_OPCODE(G_BR) 657 658/// Generic branch to jump table entry. 659HANDLE_TARGET_OPCODE(G_BRJT) 660 661/// Generic insertelement. 662HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 663 664/// Generic extractelement. 665HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 666 667/// Generic shufflevector. 668HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 669 670/// Generic count trailing zeroes. 671HANDLE_TARGET_OPCODE(G_CTTZ) 672 673/// Same as above, undefined for zero inputs. 674HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 675 676/// Generic count leading zeroes. 677HANDLE_TARGET_OPCODE(G_CTLZ) 678 679/// Same as above, undefined for zero inputs. 680HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 681 682/// Generic count bits. 683HANDLE_TARGET_OPCODE(G_CTPOP) 684 685/// Generic byte swap. 686HANDLE_TARGET_OPCODE(G_BSWAP) 687 688/// Generic bit reverse. 689HANDLE_TARGET_OPCODE(G_BITREVERSE) 690 691/// Floating point ceil. 692HANDLE_TARGET_OPCODE(G_FCEIL) 693 694/// Floating point cosine. 695HANDLE_TARGET_OPCODE(G_FCOS) 696 697/// Floating point sine. 698HANDLE_TARGET_OPCODE(G_FSIN) 699 700/// Floating point square root. 701HANDLE_TARGET_OPCODE(G_FSQRT) 702 703/// Floating point floor. 704HANDLE_TARGET_OPCODE(G_FFLOOR) 705 706/// Floating point round to next integer. 707HANDLE_TARGET_OPCODE(G_FRINT) 708 709/// Floating point round to nearest integer. 710HANDLE_TARGET_OPCODE(G_FNEARBYINT) 711 712/// Generic AddressSpaceCast. 713HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 714 715/// Generic block address 716HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 717 718/// Generic jump table address 719HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 720 721/// Generic dynamic stack allocation. 722HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) 723 724/// Strict floating point instructions. 725HANDLE_TARGET_OPCODE(G_STRICT_FADD) 726HANDLE_TARGET_OPCODE(G_STRICT_FSUB) 727HANDLE_TARGET_OPCODE(G_STRICT_FMUL) 728HANDLE_TARGET_OPCODE(G_STRICT_FDIV) 729HANDLE_TARGET_OPCODE(G_STRICT_FREM) 730HANDLE_TARGET_OPCODE(G_STRICT_FMA) 731HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) 732 733/// read_register intrinsic 734HANDLE_TARGET_OPCODE(G_READ_REGISTER) 735 736/// write_register intrinsic 737HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) 738 739/// llvm.memcpy intrinsic 740HANDLE_TARGET_OPCODE(G_MEMCPY) 741 742/// llvm.memcpy.inline intrinsic 743HANDLE_TARGET_OPCODE(G_MEMCPY_INLINE) 744 745/// llvm.memmove intrinsic 746HANDLE_TARGET_OPCODE(G_MEMMOVE) 747 748/// llvm.memset intrinsic 749HANDLE_TARGET_OPCODE(G_MEMSET) 750HANDLE_TARGET_OPCODE(G_BZERO) 751 752/// Vector reductions 753HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD) 754HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL) 755HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD) 756HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL) 757HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX) 758HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN) 759HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD) 760HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL) 761HANDLE_TARGET_OPCODE(G_VECREDUCE_AND) 762HANDLE_TARGET_OPCODE(G_VECREDUCE_OR) 763HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR) 764HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX) 765HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN) 766HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX) 767HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN) 768 769HANDLE_TARGET_OPCODE(G_SBFX) 770HANDLE_TARGET_OPCODE(G_UBFX) 771 772/// Marker for the end of the generic opcode. 773/// This is used to check if an opcode is in the range of the 774/// generic opcodes. 775HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_UBFX) 776 777/// BUILTIN_OP_END - This must be the last enum value in this list. 778/// The target-specific post-isel opcode values start here. 779HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 780