1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// SUBREG_TO_REG - Assert the value of bits in a super register. 60/// The result of this instruction is the value of the second operand inserted 61/// into the subregister specified by the third operand. All other bits are 62/// assumed to be equal to the bits in the immediate integer constant in the 63/// first operand. This instruction just communicates information; No code 64/// should be generated. 65/// This is typically used after an instruction where the write to a subregister 66/// implicitly cleared the bits in the super registers. 67HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70/// register-to-register copy into a specific register class. This is only 71/// used between instruction selection and MachineInstr creation, before 72/// virtual registers have been created for all the instructions, and it's 73/// only needed in cases where the register classes implied by the 74/// instructions are insufficient. It is emitted as a COPY MachineInstr. 75 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic 81/// list of locations 82HANDLE_TARGET_OPCODE(DBG_VALUE_LIST) 83 84/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction 85/// that defines the value, rather than a virtual register. 86HANDLE_TARGET_OPCODE(DBG_INSTR_REF) 87 88/// DBG_PHI - remainder of a PHI, identifies a program point where values 89/// merge under control flow. 90HANDLE_TARGET_OPCODE(DBG_PHI) 91 92/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 93HANDLE_TARGET_OPCODE(DBG_LABEL) 94 95/// REG_SEQUENCE - This variadic instruction is used to form a register that 96/// represents a consecutive sequence of sub-registers. It's used as a 97/// register coalescing / allocation aid and must be eliminated before code 98/// emission. 99// In SDNode form, the first operand encodes the register class created by 100// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 101// pair. Once it has been lowered to a MachineInstr, the regclass operand 102// is no longer present. 103/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 104/// After register coalescing references of v1024 should be replace with 105/// v1027:3, v1025 with v1027:4, etc. 106 HANDLE_TARGET_OPCODE(REG_SEQUENCE) 107 108/// COPY - Target-independent register copy. This instruction can also be 109/// used to copy between subregisters of virtual registers. 110 HANDLE_TARGET_OPCODE(COPY) 111 112/// BUNDLE - This instruction represents an instruction bundle. Instructions 113/// which immediately follow a BUNDLE instruction which are marked with 114/// 'InsideBundle' flag are inside the bundle. 115HANDLE_TARGET_OPCODE(BUNDLE) 116 117/// Lifetime markers. 118HANDLE_TARGET_OPCODE(LIFETIME_START) 119HANDLE_TARGET_OPCODE(LIFETIME_END) 120 121/// Pseudo probe 122HANDLE_TARGET_OPCODE(PSEUDO_PROBE) 123 124/// Arithmetic fence. 125HANDLE_TARGET_OPCODE(ARITH_FENCE) 126 127/// A Stackmap instruction captures the location of live variables at its 128/// position in the instruction stream. It is followed by a shadow of bytes 129/// that must lie within the function and not contain another stackmap. 130HANDLE_TARGET_OPCODE(STACKMAP) 131 132/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 133HANDLE_TARGET_OPCODE(FENTRY_CALL) 134 135/// Patchable call instruction - this instruction represents a call to a 136/// constant address, followed by a series of NOPs. It is intended to 137/// support optimizations for dynamic languages (such as javascript) that 138/// rewrite calls to runtimes with more efficient code sequences. 139/// This also implies a stack map. 140HANDLE_TARGET_OPCODE(PATCHPOINT) 141 142/// This pseudo-instruction loads the stack guard value. Targets which need 143/// to prevent the stack guard value or address from being spilled to the 144/// stack should override TargetLowering::emitLoadStackGuardNode and 145/// additionally expand this pseudo after register allocation. 146HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 147 148/// These are used to support call sites that must have the stack adjusted 149/// before the call (e.g. to initialize an argument passed by value). 150/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. 151HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) 152HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) 153 154/// Call instruction with associated vm state for deoptimization and list 155/// of live pointers for relocation by the garbage collector. It is 156/// intended to support garbage collection with fully precise relocating 157/// collectors and deoptimizations in either the callee or caller. 158HANDLE_TARGET_OPCODE(STATEPOINT) 159 160/// Instruction that records the offset of a local stack allocation passed to 161/// llvm.localescape. It has two arguments: the symbol for the label and the 162/// frame index of the local stack allocation. 163HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 164 165/// Wraps a machine instruction which can fault, bundled with associated 166/// information on how to handle such a fault. 167/// For example loading instruction that may page fault, bundled with associated 168/// information on how to handle such a page fault. It is intended to support 169/// "zero cost" null checks in managed languages by allowing LLVM to fold 170/// comparisons into existing memory operations. 171HANDLE_TARGET_OPCODE(FAULTING_OP) 172 173/// Wraps a machine instruction to add patchability constraints. An 174/// instruction wrapped in PATCHABLE_OP has to either have a minimum 175/// size or be preceded with a nop of that size. The first operand is 176/// an immediate denoting the minimum size of the instruction, the 177/// second operand is an immediate denoting the opcode of the original 178/// instruction. The rest of the operands are the operands of the 179/// original instruction. 180HANDLE_TARGET_OPCODE(PATCHABLE_OP) 181 182/// This is a marker instruction which gets translated into a nop sled, useful 183/// for inserting instrumentation instructions at runtime. 184HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 185 186/// Wraps a return instruction and its operands to enable adding nop sleds 187/// either before or after the return. The nop sleds are useful for inserting 188/// instrumentation instructions at runtime. 189/// The patch here replaces the return instruction. 190HANDLE_TARGET_OPCODE(PATCHABLE_RET) 191 192/// This is a marker instruction which gets translated into a nop sled, useful 193/// for inserting instrumentation instructions at runtime. 194/// The patch here prepends the return instruction. 195/// The same thing as in x86_64 is not possible for ARM because it has multiple 196/// return instructions. Furthermore, CPU allows parametrized and even 197/// conditional return instructions. In the current ARM implementation we are 198/// making use of the fact that currently LLVM doesn't seem to generate 199/// conditional return instructions. 200/// On ARM, the same instruction can be used for popping multiple registers 201/// from the stack and returning (it just pops pc register too), and LLVM 202/// generates it sometimes. So we can't insert the sled between this stack 203/// adjustment and the return without splitting the original instruction into 2 204/// instructions. So on ARM, rather than jumping into the exit trampoline, we 205/// call it, it does the tracing, preserves the stack and returns. 206HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 207 208/// Wraps a tail call instruction and its operands to enable adding nop sleds 209/// either before or after the tail exit. We use this as a disambiguation from 210/// PATCHABLE_RET which specifically only works for return instructions. 211HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 212 213/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 214/// be patched to insert instrumentation instructions. 215HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 216 217/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 218/// can be patched to insert instrumentation instructions. 219HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 220 221HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 222 223/// The following generic opcodes are not supposed to appear after ISel. 224/// This is something we might want to relax, but for now, this is convenient 225/// to produce diagnostics. 226 227/// Instructions which should not exist past instruction selection, but do not 228/// generate code. These instructions only act as optimization hints. 229HANDLE_TARGET_OPCODE(G_ASSERT_SEXT) 230HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT) 231HANDLE_TARGET_OPCODE(G_ASSERT_ALIGN) 232HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START, 233 G_ASSERT_SEXT) 234HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END, 235 G_ASSERT_ALIGN) 236 237/// Generic ADD instruction. This is an integer add. 238HANDLE_TARGET_OPCODE(G_ADD) 239HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 240 241/// Generic SUB instruction. This is an integer sub. 242HANDLE_TARGET_OPCODE(G_SUB) 243 244// Generic multiply instruction. 245HANDLE_TARGET_OPCODE(G_MUL) 246 247// Generic signed division instruction. 248HANDLE_TARGET_OPCODE(G_SDIV) 249 250// Generic unsigned division instruction. 251HANDLE_TARGET_OPCODE(G_UDIV) 252 253// Generic signed remainder instruction. 254HANDLE_TARGET_OPCODE(G_SREM) 255 256// Generic unsigned remainder instruction. 257HANDLE_TARGET_OPCODE(G_UREM) 258 259// Generic signed divrem instruction. 260HANDLE_TARGET_OPCODE(G_SDIVREM) 261 262// Generic unsigned divrem instruction. 263HANDLE_TARGET_OPCODE(G_UDIVREM) 264 265/// Generic bitwise and instruction. 266HANDLE_TARGET_OPCODE(G_AND) 267 268/// Generic bitwise or instruction. 269HANDLE_TARGET_OPCODE(G_OR) 270 271/// Generic bitwise exclusive-or instruction. 272HANDLE_TARGET_OPCODE(G_XOR) 273 274 275HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 276 277/// Generic PHI instruction with types. 278HANDLE_TARGET_OPCODE(G_PHI) 279 280/// Generic instruction to materialize the address of an alloca or other 281/// stack-based object. 282HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 283 284/// Generic reference to global value. 285HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 286 287/// Generic instruction to extract blocks of bits from the register given 288/// (typically a sub-register COPY after instruction selection). 289HANDLE_TARGET_OPCODE(G_EXTRACT) 290 291HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 292 293/// Generic instruction to insert blocks of bits from the registers given into 294/// the source. 295HANDLE_TARGET_OPCODE(G_INSERT) 296 297/// Generic instruction to paste a variable number of components together into a 298/// larger register. 299HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 300 301/// Generic instruction to create a vector value from a number of scalar 302/// components. 303HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 304 305/// Generic instruction to create a vector value from a number of scalar 306/// components, which have types larger than the result vector elt type. 307HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 308 309/// Generic instruction to create a vector by concatenating multiple vectors. 310HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 311 312/// Generic pointer to int conversion. 313HANDLE_TARGET_OPCODE(G_PTRTOINT) 314 315/// Generic int to pointer conversion. 316HANDLE_TARGET_OPCODE(G_INTTOPTR) 317 318/// Generic bitcast. The source and destination types must be different, or a 319/// COPY is the relevant instruction. 320HANDLE_TARGET_OPCODE(G_BITCAST) 321 322/// Generic freeze. 323HANDLE_TARGET_OPCODE(G_FREEZE) 324 325// INTRINSIC fptrunc_round intrinsic. 326HANDLE_TARGET_OPCODE(G_INTRINSIC_FPTRUNC_ROUND) 327 328/// INTRINSIC trunc intrinsic. 329HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 330 331/// INTRINSIC round intrinsic. 332HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 333 334/// INTRINSIC round to integer intrinsic. 335HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT) 336 337/// INTRINSIC roundeven intrinsic. 338HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN) 339 340/// INTRINSIC readcyclecounter 341HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) 342 343/// Generic load (including anyext load) 344HANDLE_TARGET_OPCODE(G_LOAD) 345 346/// Generic signext load 347HANDLE_TARGET_OPCODE(G_SEXTLOAD) 348 349/// Generic zeroext load 350HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 351 352/// Generic indexed load (including anyext load) 353HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) 354 355/// Generic indexed signext load 356HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) 357 358/// Generic indexed zeroext load 359HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) 360 361/// Generic store. 362HANDLE_TARGET_OPCODE(G_STORE) 363 364/// Generic indexed store. 365HANDLE_TARGET_OPCODE(G_INDEXED_STORE) 366 367/// Generic atomic cmpxchg with internal success check. 368HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 369 370/// Generic atomic cmpxchg. 371HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 372 373/// Generic atomicrmw. 374HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 375HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 376HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 377HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 378HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 379HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 380HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 381HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 382HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 383HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 384HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 385HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) 386HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) 387HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX) 388HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN) 389 390// Generic atomic fence 391HANDLE_TARGET_OPCODE(G_FENCE) 392 393/// Generic conditional branch instruction. 394HANDLE_TARGET_OPCODE(G_BRCOND) 395 396/// Generic indirect branch instruction. 397HANDLE_TARGET_OPCODE(G_BRINDIRECT) 398 399/// Generic intrinsic use (without side effects). 400HANDLE_TARGET_OPCODE(G_INTRINSIC) 401 402/// Generic intrinsic use (with side effects). 403HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 404 405/// Generic extension allowing rubbish in high bits. 406HANDLE_TARGET_OPCODE(G_ANYEXT) 407 408/// Generic instruction to discard the high bits of a register. This differs 409/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 410/// each element individually, G_EXTRACT will typically discard the high 411/// elements of the vector. 412HANDLE_TARGET_OPCODE(G_TRUNC) 413 414/// Generic integer constant. 415HANDLE_TARGET_OPCODE(G_CONSTANT) 416 417/// Generic floating constant. 418HANDLE_TARGET_OPCODE(G_FCONSTANT) 419 420/// Generic va_start instruction. Stores to its one pointer operand. 421HANDLE_TARGET_OPCODE(G_VASTART) 422 423/// Generic va_start instruction. Stores to its one pointer operand. 424HANDLE_TARGET_OPCODE(G_VAARG) 425 426// Generic sign extend 427HANDLE_TARGET_OPCODE(G_SEXT) 428HANDLE_TARGET_OPCODE(G_SEXT_INREG) 429 430// Generic zero extend 431HANDLE_TARGET_OPCODE(G_ZEXT) 432 433// Generic left-shift 434HANDLE_TARGET_OPCODE(G_SHL) 435 436// Generic logical right-shift 437HANDLE_TARGET_OPCODE(G_LSHR) 438 439// Generic arithmetic right-shift 440HANDLE_TARGET_OPCODE(G_ASHR) 441 442// Generic funnel left shift 443HANDLE_TARGET_OPCODE(G_FSHL) 444 445// Generic funnel right shift 446HANDLE_TARGET_OPCODE(G_FSHR) 447 448// Generic right rotate 449HANDLE_TARGET_OPCODE(G_ROTR) 450 451// Generic left rotate 452HANDLE_TARGET_OPCODE(G_ROTL) 453 454/// Generic integer-base comparison, also applicable to vectors of integers. 455HANDLE_TARGET_OPCODE(G_ICMP) 456 457/// Generic floating-point comparison, also applicable to vectors. 458HANDLE_TARGET_OPCODE(G_FCMP) 459 460/// Generic select. 461HANDLE_TARGET_OPCODE(G_SELECT) 462 463/// Generic unsigned add instruction, consuming the normal operands and 464/// producing the result and a carry flag. 465HANDLE_TARGET_OPCODE(G_UADDO) 466 467/// Generic unsigned add instruction, consuming the normal operands plus a carry 468/// flag, and similarly producing the result and a carry flag. 469HANDLE_TARGET_OPCODE(G_UADDE) 470 471/// Generic unsigned sub instruction, consuming the normal operands and 472/// producing the result and a carry flag. 473HANDLE_TARGET_OPCODE(G_USUBO) 474 475/// Generic unsigned subtract instruction, consuming the normal operands plus a 476/// carry flag, and similarly producing the result and a carry flag. 477HANDLE_TARGET_OPCODE(G_USUBE) 478 479/// Generic signed add instruction, producing the result and a signed overflow 480/// flag. 481HANDLE_TARGET_OPCODE(G_SADDO) 482 483/// Generic signed add instruction, consuming the normal operands plus a carry 484/// flag, and similarly producing the result and a carry flag. 485HANDLE_TARGET_OPCODE(G_SADDE) 486 487/// Generic signed subtract instruction, producing the result and a signed 488/// overflow flag. 489HANDLE_TARGET_OPCODE(G_SSUBO) 490 491/// Generic signed sub instruction, consuming the normal operands plus a carry 492/// flag, and similarly producing the result and a carry flag. 493HANDLE_TARGET_OPCODE(G_SSUBE) 494 495/// Generic unsigned multiply instruction, producing the result and a signed 496/// overflow flag. 497HANDLE_TARGET_OPCODE(G_UMULO) 498 499/// Generic signed multiply instruction, producing the result and a signed 500/// overflow flag. 501HANDLE_TARGET_OPCODE(G_SMULO) 502 503// Multiply two numbers at twice the incoming bit width (unsigned) and return 504// the high half of the result. 505HANDLE_TARGET_OPCODE(G_UMULH) 506 507// Multiply two numbers at twice the incoming bit width (signed) and return 508// the high half of the result. 509HANDLE_TARGET_OPCODE(G_SMULH) 510 511/// Generic saturating unsigned addition. 512HANDLE_TARGET_OPCODE(G_UADDSAT) 513 514/// Generic saturating signed addition. 515HANDLE_TARGET_OPCODE(G_SADDSAT) 516 517/// Generic saturating unsigned subtraction. 518HANDLE_TARGET_OPCODE(G_USUBSAT) 519 520/// Generic saturating signed subtraction. 521HANDLE_TARGET_OPCODE(G_SSUBSAT) 522 523/// Generic saturating unsigned left shift. 524HANDLE_TARGET_OPCODE(G_USHLSAT) 525 526/// Generic saturating signed left shift. 527HANDLE_TARGET_OPCODE(G_SSHLSAT) 528 529// Perform signed fixed point multiplication 530HANDLE_TARGET_OPCODE(G_SMULFIX) 531 532// Perform unsigned fixed point multiplication 533HANDLE_TARGET_OPCODE(G_UMULFIX) 534 535// Perform signed, saturating fixed point multiplication 536HANDLE_TARGET_OPCODE(G_SMULFIXSAT) 537 538// Perform unsigned, saturating fixed point multiplication 539HANDLE_TARGET_OPCODE(G_UMULFIXSAT) 540 541// Perform signed fixed point division 542HANDLE_TARGET_OPCODE(G_SDIVFIX) 543 544// Perform unsigned fixed point division 545HANDLE_TARGET_OPCODE(G_UDIVFIX) 546 547// Perform signed, saturating fixed point division 548HANDLE_TARGET_OPCODE(G_SDIVFIXSAT) 549 550// Perform unsigned, saturating fixed point division 551HANDLE_TARGET_OPCODE(G_UDIVFIXSAT) 552 553/// Generic FP addition. 554HANDLE_TARGET_OPCODE(G_FADD) 555 556/// Generic FP subtraction. 557HANDLE_TARGET_OPCODE(G_FSUB) 558 559/// Generic FP multiplication. 560HANDLE_TARGET_OPCODE(G_FMUL) 561 562/// Generic FMA multiplication. Behaves like llvm fma intrinsic 563HANDLE_TARGET_OPCODE(G_FMA) 564 565/// Generic FP multiply and add. Behaves as separate fmul and fadd. 566HANDLE_TARGET_OPCODE(G_FMAD) 567 568/// Generic FP division. 569HANDLE_TARGET_OPCODE(G_FDIV) 570 571/// Generic FP remainder. 572HANDLE_TARGET_OPCODE(G_FREM) 573 574/// Generic FP exponentiation. 575HANDLE_TARGET_OPCODE(G_FPOW) 576 577/// Generic FP exponentiation, with an integer exponent. 578HANDLE_TARGET_OPCODE(G_FPOWI) 579 580/// Generic base-e exponential of a value. 581HANDLE_TARGET_OPCODE(G_FEXP) 582 583/// Generic base-2 exponential of a value. 584HANDLE_TARGET_OPCODE(G_FEXP2) 585 586/// Floating point base-e logarithm of a value. 587HANDLE_TARGET_OPCODE(G_FLOG) 588 589/// Floating point base-2 logarithm of a value. 590HANDLE_TARGET_OPCODE(G_FLOG2) 591 592/// Floating point base-10 logarithm of a value. 593HANDLE_TARGET_OPCODE(G_FLOG10) 594 595/// Generic FP negation. 596HANDLE_TARGET_OPCODE(G_FNEG) 597 598/// Generic FP extension. 599HANDLE_TARGET_OPCODE(G_FPEXT) 600 601/// Generic float to signed-int conversion 602HANDLE_TARGET_OPCODE(G_FPTRUNC) 603 604/// Generic float to signed-int conversion 605HANDLE_TARGET_OPCODE(G_FPTOSI) 606 607/// Generic float to unsigned-int conversion 608HANDLE_TARGET_OPCODE(G_FPTOUI) 609 610/// Generic signed-int to float conversion 611HANDLE_TARGET_OPCODE(G_SITOFP) 612 613/// Generic unsigned-int to float conversion 614HANDLE_TARGET_OPCODE(G_UITOFP) 615 616/// Generic FP absolute value. 617HANDLE_TARGET_OPCODE(G_FABS) 618 619/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 620/// not require that X and Y have the same type, just that they are both 621/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 622/// f64) is allowed. 623HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 624 625/// Generic test for floating-point class. 626HANDLE_TARGET_OPCODE(G_IS_FPCLASS) 627 628/// Generic FP canonicalize value. 629HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 630 631/// FP min/max matching libm's fmin/fmax 632HANDLE_TARGET_OPCODE(G_FMINNUM) 633HANDLE_TARGET_OPCODE(G_FMAXNUM) 634 635/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 636HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 637HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 638 639/// FP min/max matching IEEE-754 2018 draft semantics. 640HANDLE_TARGET_OPCODE(G_FMINIMUM) 641HANDLE_TARGET_OPCODE(G_FMAXIMUM) 642 643/// Generic pointer offset 644HANDLE_TARGET_OPCODE(G_PTR_ADD) 645 646/// Clear the specified bits in a pointer. 647HANDLE_TARGET_OPCODE(G_PTRMASK) 648 649/// Generic signed integer minimum. 650HANDLE_TARGET_OPCODE(G_SMIN) 651 652/// Generic signed integer maximum. 653HANDLE_TARGET_OPCODE(G_SMAX) 654 655/// Generic unsigned integer maximum. 656HANDLE_TARGET_OPCODE(G_UMIN) 657 658/// Generic unsigned integer maximum. 659HANDLE_TARGET_OPCODE(G_UMAX) 660 661/// Generic integer absolute value. 662HANDLE_TARGET_OPCODE(G_ABS) 663 664HANDLE_TARGET_OPCODE(G_LROUND) 665HANDLE_TARGET_OPCODE(G_LLROUND) 666 667/// Generic BRANCH instruction. This is an unconditional branch. 668HANDLE_TARGET_OPCODE(G_BR) 669 670/// Generic branch to jump table entry. 671HANDLE_TARGET_OPCODE(G_BRJT) 672 673/// Generic insertelement. 674HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 675 676/// Generic extractelement. 677HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 678 679/// Generic shufflevector. 680HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 681 682/// Generic count trailing zeroes. 683HANDLE_TARGET_OPCODE(G_CTTZ) 684 685/// Same as above, undefined for zero inputs. 686HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 687 688/// Generic count leading zeroes. 689HANDLE_TARGET_OPCODE(G_CTLZ) 690 691/// Same as above, undefined for zero inputs. 692HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 693 694/// Generic count bits. 695HANDLE_TARGET_OPCODE(G_CTPOP) 696 697/// Generic byte swap. 698HANDLE_TARGET_OPCODE(G_BSWAP) 699 700/// Generic bit reverse. 701HANDLE_TARGET_OPCODE(G_BITREVERSE) 702 703/// Floating point ceil. 704HANDLE_TARGET_OPCODE(G_FCEIL) 705 706/// Floating point cosine. 707HANDLE_TARGET_OPCODE(G_FCOS) 708 709/// Floating point sine. 710HANDLE_TARGET_OPCODE(G_FSIN) 711 712/// Floating point square root. 713HANDLE_TARGET_OPCODE(G_FSQRT) 714 715/// Floating point floor. 716HANDLE_TARGET_OPCODE(G_FFLOOR) 717 718/// Floating point round to next integer. 719HANDLE_TARGET_OPCODE(G_FRINT) 720 721/// Floating point round to nearest integer. 722HANDLE_TARGET_OPCODE(G_FNEARBYINT) 723 724/// Generic AddressSpaceCast. 725HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 726 727/// Generic block address 728HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 729 730/// Generic jump table address 731HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 732 733/// Generic dynamic stack allocation. 734HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) 735 736/// Strict floating point instructions. 737HANDLE_TARGET_OPCODE(G_STRICT_FADD) 738HANDLE_TARGET_OPCODE(G_STRICT_FSUB) 739HANDLE_TARGET_OPCODE(G_STRICT_FMUL) 740HANDLE_TARGET_OPCODE(G_STRICT_FDIV) 741HANDLE_TARGET_OPCODE(G_STRICT_FREM) 742HANDLE_TARGET_OPCODE(G_STRICT_FMA) 743HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) 744 745/// read_register intrinsic 746HANDLE_TARGET_OPCODE(G_READ_REGISTER) 747 748/// write_register intrinsic 749HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) 750 751/// llvm.memcpy intrinsic 752HANDLE_TARGET_OPCODE(G_MEMCPY) 753 754/// llvm.memcpy.inline intrinsic 755HANDLE_TARGET_OPCODE(G_MEMCPY_INLINE) 756 757/// llvm.memmove intrinsic 758HANDLE_TARGET_OPCODE(G_MEMMOVE) 759 760/// llvm.memset intrinsic 761HANDLE_TARGET_OPCODE(G_MEMSET) 762HANDLE_TARGET_OPCODE(G_BZERO) 763 764/// Vector reductions 765HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD) 766HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL) 767HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD) 768HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL) 769HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX) 770HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN) 771HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD) 772HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL) 773HANDLE_TARGET_OPCODE(G_VECREDUCE_AND) 774HANDLE_TARGET_OPCODE(G_VECREDUCE_OR) 775HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR) 776HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX) 777HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN) 778HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX) 779HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN) 780 781HANDLE_TARGET_OPCODE(G_SBFX) 782HANDLE_TARGET_OPCODE(G_UBFX) 783 784/// Marker for the end of the generic opcode. 785/// This is used to check if an opcode is in the range of the 786/// generic opcodes. 787HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_UBFX) 788 789/// BUILTIN_OP_END - This must be the last enum value in this list. 790/// The target-specific post-isel opcode values start here. 791HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 792