1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// SUBREG_TO_REG - Assert the value of bits in a super register. 60/// The result of this instruction is the value of the second operand inserted 61/// into the subregister specified by the third operand. All other bits are 62/// assumed to be equal to the bits in the immediate integer constant in the 63/// first operand. This instruction just communicates information; No code 64/// should be generated. 65/// This is typically used after an instruction where the write to a subregister 66/// implicitly cleared the bits in the super registers. 67HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70/// register-to-register copy into a specific register class. This is only 71/// used between instruction selection and MachineInstr creation, before 72/// virtual registers have been created for all the instructions, and it's 73/// only needed in cases where the register classes implied by the 74/// instructions are insufficient. It is emitted as a COPY MachineInstr. 75 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction 81/// that defines the value, rather than a virtual register. 82HANDLE_TARGET_OPCODE(DBG_INSTR_REF) 83 84/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 85HANDLE_TARGET_OPCODE(DBG_LABEL) 86 87/// REG_SEQUENCE - This variadic instruction is used to form a register that 88/// represents a consecutive sequence of sub-registers. It's used as a 89/// register coalescing / allocation aid and must be eliminated before code 90/// emission. 91// In SDNode form, the first operand encodes the register class created by 92// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 93// pair. Once it has been lowered to a MachineInstr, the regclass operand 94// is no longer present. 95/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 96/// After register coalescing references of v1024 should be replace with 97/// v1027:3, v1025 with v1027:4, etc. 98 HANDLE_TARGET_OPCODE(REG_SEQUENCE) 99 100/// COPY - Target-independent register copy. This instruction can also be 101/// used to copy between subregisters of virtual registers. 102 HANDLE_TARGET_OPCODE(COPY) 103 104/// BUNDLE - This instruction represents an instruction bundle. Instructions 105/// which immediately follow a BUNDLE instruction which are marked with 106/// 'InsideBundle' flag are inside the bundle. 107HANDLE_TARGET_OPCODE(BUNDLE) 108 109/// Lifetime markers. 110HANDLE_TARGET_OPCODE(LIFETIME_START) 111HANDLE_TARGET_OPCODE(LIFETIME_END) 112 113/// Pseudo probe 114HANDLE_TARGET_OPCODE(PSEUDO_PROBE) 115 116/// A Stackmap instruction captures the location of live variables at its 117/// position in the instruction stream. It is followed by a shadow of bytes 118/// that must lie within the function and not contain another stackmap. 119HANDLE_TARGET_OPCODE(STACKMAP) 120 121/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 122HANDLE_TARGET_OPCODE(FENTRY_CALL) 123 124/// Patchable call instruction - this instruction represents a call to a 125/// constant address, followed by a series of NOPs. It is intended to 126/// support optimizations for dynamic languages (such as javascript) that 127/// rewrite calls to runtimes with more efficient code sequences. 128/// This also implies a stack map. 129HANDLE_TARGET_OPCODE(PATCHPOINT) 130 131/// This pseudo-instruction loads the stack guard value. Targets which need 132/// to prevent the stack guard value or address from being spilled to the 133/// stack should override TargetLowering::emitLoadStackGuardNode and 134/// additionally expand this pseudo after register allocation. 135HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 136 137/// These are used to support call sites that must have the stack adjusted 138/// before the call (e.g. to initialize an argument passed by value). 139/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. 140HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) 141HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) 142 143/// Call instruction with associated vm state for deoptimization and list 144/// of live pointers for relocation by the garbage collector. It is 145/// intended to support garbage collection with fully precise relocating 146/// collectors and deoptimizations in either the callee or caller. 147HANDLE_TARGET_OPCODE(STATEPOINT) 148 149/// Instruction that records the offset of a local stack allocation passed to 150/// llvm.localescape. It has two arguments: the symbol for the label and the 151/// frame index of the local stack allocation. 152HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 153 154/// Wraps a machine instruction which can fault, bundled with associated 155/// information on how to handle such a fault. 156/// For example loading instruction that may page fault, bundled with associated 157/// information on how to handle such a page fault. It is intended to support 158/// "zero cost" null checks in managed languages by allowing LLVM to fold 159/// comparisons into existing memory operations. 160HANDLE_TARGET_OPCODE(FAULTING_OP) 161 162/// Wraps a machine instruction to add patchability constraints. An 163/// instruction wrapped in PATCHABLE_OP has to either have a minimum 164/// size or be preceded with a nop of that size. The first operand is 165/// an immediate denoting the minimum size of the instruction, the 166/// second operand is an immediate denoting the opcode of the original 167/// instruction. The rest of the operands are the operands of the 168/// original instruction. 169HANDLE_TARGET_OPCODE(PATCHABLE_OP) 170 171/// This is a marker instruction which gets translated into a nop sled, useful 172/// for inserting instrumentation instructions at runtime. 173HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 174 175/// Wraps a return instruction and its operands to enable adding nop sleds 176/// either before or after the return. The nop sleds are useful for inserting 177/// instrumentation instructions at runtime. 178/// The patch here replaces the return instruction. 179HANDLE_TARGET_OPCODE(PATCHABLE_RET) 180 181/// This is a marker instruction which gets translated into a nop sled, useful 182/// for inserting instrumentation instructions at runtime. 183/// The patch here prepends the return instruction. 184/// The same thing as in x86_64 is not possible for ARM because it has multiple 185/// return instructions. Furthermore, CPU allows parametrized and even 186/// conditional return instructions. In the current ARM implementation we are 187/// making use of the fact that currently LLVM doesn't seem to generate 188/// conditional return instructions. 189/// On ARM, the same instruction can be used for popping multiple registers 190/// from the stack and returning (it just pops pc register too), and LLVM 191/// generates it sometimes. So we can't insert the sled between this stack 192/// adjustment and the return without splitting the original instruction into 2 193/// instructions. So on ARM, rather than jumping into the exit trampoline, we 194/// call it, it does the tracing, preserves the stack and returns. 195HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 196 197/// Wraps a tail call instruction and its operands to enable adding nop sleds 198/// either before or after the tail exit. We use this as a disambiguation from 199/// PATCHABLE_RET which specifically only works for return instructions. 200HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 201 202/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 203/// be patched to insert instrumentation instructions. 204HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 205 206/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 207/// can be patched to insert instrumentation instructions. 208HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 209 210HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 211 212/// The following generic opcodes are not supposed to appear after ISel. 213/// This is something we might want to relax, but for now, this is convenient 214/// to produce diagnostics. 215 216/// Generic ADD instruction. This is an integer add. 217HANDLE_TARGET_OPCODE(G_ADD) 218HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 219 220/// Generic SUB instruction. This is an integer sub. 221HANDLE_TARGET_OPCODE(G_SUB) 222 223// Generic multiply instruction. 224HANDLE_TARGET_OPCODE(G_MUL) 225 226// Generic signed division instruction. 227HANDLE_TARGET_OPCODE(G_SDIV) 228 229// Generic unsigned division instruction. 230HANDLE_TARGET_OPCODE(G_UDIV) 231 232// Generic signed remainder instruction. 233HANDLE_TARGET_OPCODE(G_SREM) 234 235// Generic unsigned remainder instruction. 236HANDLE_TARGET_OPCODE(G_UREM) 237 238/// Generic bitwise and instruction. 239HANDLE_TARGET_OPCODE(G_AND) 240 241/// Generic bitwise or instruction. 242HANDLE_TARGET_OPCODE(G_OR) 243 244/// Generic bitwise exclusive-or instruction. 245HANDLE_TARGET_OPCODE(G_XOR) 246 247 248HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 249 250/// Generic PHI instruction with types. 251HANDLE_TARGET_OPCODE(G_PHI) 252 253/// Generic instruction to materialize the address of an alloca or other 254/// stack-based object. 255HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 256 257/// Generic reference to global value. 258HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 259 260/// Generic instruction to extract blocks of bits from the register given 261/// (typically a sub-register COPY after instruction selection). 262HANDLE_TARGET_OPCODE(G_EXTRACT) 263 264HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 265 266/// Generic instruction to insert blocks of bits from the registers given into 267/// the source. 268HANDLE_TARGET_OPCODE(G_INSERT) 269 270/// Generic instruction to paste a variable number of components together into a 271/// larger register. 272HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 273 274/// Generic instruction to create a vector value from a number of scalar 275/// components. 276HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 277 278/// Generic instruction to create a vector value from a number of scalar 279/// components, which have types larger than the result vector elt type. 280HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 281 282/// Generic instruction to create a vector by concatenating multiple vectors. 283HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 284 285/// Generic pointer to int conversion. 286HANDLE_TARGET_OPCODE(G_PTRTOINT) 287 288/// Generic int to pointer conversion. 289HANDLE_TARGET_OPCODE(G_INTTOPTR) 290 291/// Generic bitcast. The source and destination types must be different, or a 292/// COPY is the relevant instruction. 293HANDLE_TARGET_OPCODE(G_BITCAST) 294 295/// Generic freeze. 296HANDLE_TARGET_OPCODE(G_FREEZE) 297 298/// INTRINSIC trunc intrinsic. 299HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 300 301/// INTRINSIC round intrinsic. 302HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 303 304/// INTRINSIC round to integer intrinsic. 305HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT) 306 307/// INTRINSIC roundeven intrinsic. 308HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN) 309 310/// INTRINSIC readcyclecounter 311HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) 312 313/// Generic load (including anyext load) 314HANDLE_TARGET_OPCODE(G_LOAD) 315 316/// Generic signext load 317HANDLE_TARGET_OPCODE(G_SEXTLOAD) 318 319/// Generic zeroext load 320HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 321 322/// Generic indexed load (including anyext load) 323HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) 324 325/// Generic indexed signext load 326HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) 327 328/// Generic indexed zeroext load 329HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) 330 331/// Generic store. 332HANDLE_TARGET_OPCODE(G_STORE) 333 334/// Generic indexed store. 335HANDLE_TARGET_OPCODE(G_INDEXED_STORE) 336 337/// Generic atomic cmpxchg with internal success check. 338HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 339 340/// Generic atomic cmpxchg. 341HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 342 343/// Generic atomicrmw. 344HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 345HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 346HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 347HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 348HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 349HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 350HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 351HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 352HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 353HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 354HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 355HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) 356HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) 357 358// Generic atomic fence 359HANDLE_TARGET_OPCODE(G_FENCE) 360 361/// Generic conditional branch instruction. 362HANDLE_TARGET_OPCODE(G_BRCOND) 363 364/// Generic indirect branch instruction. 365HANDLE_TARGET_OPCODE(G_BRINDIRECT) 366 367/// Generic intrinsic use (without side effects). 368HANDLE_TARGET_OPCODE(G_INTRINSIC) 369 370/// Generic intrinsic use (with side effects). 371HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 372 373/// Generic extension allowing rubbish in high bits. 374HANDLE_TARGET_OPCODE(G_ANYEXT) 375 376/// Generic instruction to discard the high bits of a register. This differs 377/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 378/// each element individually, G_EXTRACT will typically discard the high 379/// elements of the vector. 380HANDLE_TARGET_OPCODE(G_TRUNC) 381 382/// Generic integer constant. 383HANDLE_TARGET_OPCODE(G_CONSTANT) 384 385/// Generic floating constant. 386HANDLE_TARGET_OPCODE(G_FCONSTANT) 387 388/// Generic va_start instruction. Stores to its one pointer operand. 389HANDLE_TARGET_OPCODE(G_VASTART) 390 391/// Generic va_start instruction. Stores to its one pointer operand. 392HANDLE_TARGET_OPCODE(G_VAARG) 393 394// Generic sign extend 395HANDLE_TARGET_OPCODE(G_SEXT) 396HANDLE_TARGET_OPCODE(G_SEXT_INREG) 397 398// Generic zero extend 399HANDLE_TARGET_OPCODE(G_ZEXT) 400 401// Generic left-shift 402HANDLE_TARGET_OPCODE(G_SHL) 403 404// Generic logical right-shift 405HANDLE_TARGET_OPCODE(G_LSHR) 406 407// Generic arithmetic right-shift 408HANDLE_TARGET_OPCODE(G_ASHR) 409 410// Generic funnel left shift 411HANDLE_TARGET_OPCODE(G_FSHL) 412 413// Generic funnel right shift 414HANDLE_TARGET_OPCODE(G_FSHR) 415 416/// Generic integer-base comparison, also applicable to vectors of integers. 417HANDLE_TARGET_OPCODE(G_ICMP) 418 419/// Generic floating-point comparison, also applicable to vectors. 420HANDLE_TARGET_OPCODE(G_FCMP) 421 422/// Generic select. 423HANDLE_TARGET_OPCODE(G_SELECT) 424 425/// Generic unsigned add instruction, consuming the normal operands and 426/// producing the result and a carry flag. 427HANDLE_TARGET_OPCODE(G_UADDO) 428 429/// Generic unsigned add instruction, consuming the normal operands plus a carry 430/// flag, and similarly producing the result and a carry flag. 431HANDLE_TARGET_OPCODE(G_UADDE) 432 433/// Generic unsigned sub instruction, consuming the normal operands and 434/// producing the result and a carry flag. 435HANDLE_TARGET_OPCODE(G_USUBO) 436 437/// Generic unsigned subtract instruction, consuming the normal operands plus a 438/// carry flag, and similarly producing the result and a carry flag. 439HANDLE_TARGET_OPCODE(G_USUBE) 440 441/// Generic signed add instruction, producing the result and a signed overflow 442/// flag. 443HANDLE_TARGET_OPCODE(G_SADDO) 444 445/// Generic signed add instruction, consuming the normal operands plus a carry 446/// flag, and similarly producing the result and a carry flag. 447HANDLE_TARGET_OPCODE(G_SADDE) 448 449/// Generic signed subtract instruction, producing the result and a signed 450/// overflow flag. 451HANDLE_TARGET_OPCODE(G_SSUBO) 452 453/// Generic signed sub instruction, consuming the normal operands plus a carry 454/// flag, and similarly producing the result and a carry flag. 455HANDLE_TARGET_OPCODE(G_SSUBE) 456 457/// Generic unsigned multiply instruction, producing the result and a signed 458/// overflow flag. 459HANDLE_TARGET_OPCODE(G_UMULO) 460 461/// Generic signed multiply instruction, producing the result and a signed 462/// overflow flag. 463HANDLE_TARGET_OPCODE(G_SMULO) 464 465// Multiply two numbers at twice the incoming bit width (unsigned) and return 466// the high half of the result. 467HANDLE_TARGET_OPCODE(G_UMULH) 468 469// Multiply two numbers at twice the incoming bit width (signed) and return 470// the high half of the result. 471HANDLE_TARGET_OPCODE(G_SMULH) 472 473/// Generic saturating unsigned addition. 474HANDLE_TARGET_OPCODE(G_UADDSAT) 475 476/// Generic saturating signed addition. 477HANDLE_TARGET_OPCODE(G_SADDSAT) 478 479/// Generic saturating unsigned subtraction. 480HANDLE_TARGET_OPCODE(G_USUBSAT) 481 482/// Generic saturating signed subtraction. 483HANDLE_TARGET_OPCODE(G_SSUBSAT) 484 485/// Generic saturating unsigned left shift. 486HANDLE_TARGET_OPCODE(G_USHLSAT) 487 488/// Generic saturating signed left shift. 489HANDLE_TARGET_OPCODE(G_SSHLSAT) 490 491// Perform signed fixed point multiplication 492HANDLE_TARGET_OPCODE(G_SMULFIX) 493 494// Perform unsigned fixed point multiplication 495HANDLE_TARGET_OPCODE(G_UMULFIX) 496 497// Perform signed, saturating fixed point multiplication 498HANDLE_TARGET_OPCODE(G_SMULFIXSAT) 499 500// Perform unsigned, saturating fixed point multiplication 501HANDLE_TARGET_OPCODE(G_UMULFIXSAT) 502 503// Perform signed fixed point division 504HANDLE_TARGET_OPCODE(G_SDIVFIX) 505 506// Perform unsigned fixed point division 507HANDLE_TARGET_OPCODE(G_UDIVFIX) 508 509// Perform signed, saturating fixed point division 510HANDLE_TARGET_OPCODE(G_SDIVFIXSAT) 511 512// Perform unsigned, saturating fixed point division 513HANDLE_TARGET_OPCODE(G_UDIVFIXSAT) 514 515/// Generic FP addition. 516HANDLE_TARGET_OPCODE(G_FADD) 517 518/// Generic FP subtraction. 519HANDLE_TARGET_OPCODE(G_FSUB) 520 521/// Generic FP multiplication. 522HANDLE_TARGET_OPCODE(G_FMUL) 523 524/// Generic FMA multiplication. Behaves like llvm fma intrinsic 525HANDLE_TARGET_OPCODE(G_FMA) 526 527/// Generic FP multiply and add. Behaves as separate fmul and fadd. 528HANDLE_TARGET_OPCODE(G_FMAD) 529 530/// Generic FP division. 531HANDLE_TARGET_OPCODE(G_FDIV) 532 533/// Generic FP remainder. 534HANDLE_TARGET_OPCODE(G_FREM) 535 536/// Generic FP exponentiation. 537HANDLE_TARGET_OPCODE(G_FPOW) 538 539/// Generic FP exponentiation, with an integer exponent. 540HANDLE_TARGET_OPCODE(G_FPOWI) 541 542/// Generic base-e exponential of a value. 543HANDLE_TARGET_OPCODE(G_FEXP) 544 545/// Generic base-2 exponential of a value. 546HANDLE_TARGET_OPCODE(G_FEXP2) 547 548/// Floating point base-e logarithm of a value. 549HANDLE_TARGET_OPCODE(G_FLOG) 550 551/// Floating point base-2 logarithm of a value. 552HANDLE_TARGET_OPCODE(G_FLOG2) 553 554/// Floating point base-10 logarithm of a value. 555HANDLE_TARGET_OPCODE(G_FLOG10) 556 557/// Generic FP negation. 558HANDLE_TARGET_OPCODE(G_FNEG) 559 560/// Generic FP extension. 561HANDLE_TARGET_OPCODE(G_FPEXT) 562 563/// Generic float to signed-int conversion 564HANDLE_TARGET_OPCODE(G_FPTRUNC) 565 566/// Generic float to signed-int conversion 567HANDLE_TARGET_OPCODE(G_FPTOSI) 568 569/// Generic float to unsigned-int conversion 570HANDLE_TARGET_OPCODE(G_FPTOUI) 571 572/// Generic signed-int to float conversion 573HANDLE_TARGET_OPCODE(G_SITOFP) 574 575/// Generic unsigned-int to float conversion 576HANDLE_TARGET_OPCODE(G_UITOFP) 577 578/// Generic FP absolute value. 579HANDLE_TARGET_OPCODE(G_FABS) 580 581/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 582/// not require that X and Y have the same type, just that they are both 583/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 584/// f64) is allowed. 585HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 586 587/// Generic FP canonicalize value. 588HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 589 590/// FP min/max matching libm's fmin/fmax 591HANDLE_TARGET_OPCODE(G_FMINNUM) 592HANDLE_TARGET_OPCODE(G_FMAXNUM) 593 594/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 595HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 596HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 597 598/// FP min/max matching IEEE-754 2018 draft semantics. 599HANDLE_TARGET_OPCODE(G_FMINIMUM) 600HANDLE_TARGET_OPCODE(G_FMAXIMUM) 601 602/// Generic pointer offset 603HANDLE_TARGET_OPCODE(G_PTR_ADD) 604 605/// Clear the specified bits in a pointer. 606HANDLE_TARGET_OPCODE(G_PTRMASK) 607 608/// Generic signed integer minimum. 609HANDLE_TARGET_OPCODE(G_SMIN) 610 611/// Generic signed integer maximum. 612HANDLE_TARGET_OPCODE(G_SMAX) 613 614/// Generic unsigned integer maximum. 615HANDLE_TARGET_OPCODE(G_UMIN) 616 617/// Generic unsigned integer maximum. 618HANDLE_TARGET_OPCODE(G_UMAX) 619 620/// Generic integer absolute value. 621HANDLE_TARGET_OPCODE(G_ABS) 622 623/// Generic BRANCH instruction. This is an unconditional branch. 624HANDLE_TARGET_OPCODE(G_BR) 625 626/// Generic branch to jump table entry. 627HANDLE_TARGET_OPCODE(G_BRJT) 628 629/// Generic insertelement. 630HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 631 632/// Generic extractelement. 633HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 634 635/// Generic shufflevector. 636HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 637 638/// Generic count trailing zeroes. 639HANDLE_TARGET_OPCODE(G_CTTZ) 640 641/// Same as above, undefined for zero inputs. 642HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 643 644/// Generic count leading zeroes. 645HANDLE_TARGET_OPCODE(G_CTLZ) 646 647/// Same as above, undefined for zero inputs. 648HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 649 650/// Generic count bits. 651HANDLE_TARGET_OPCODE(G_CTPOP) 652 653/// Generic byte swap. 654HANDLE_TARGET_OPCODE(G_BSWAP) 655 656/// Generic bit reverse. 657HANDLE_TARGET_OPCODE(G_BITREVERSE) 658 659/// Floating point ceil. 660HANDLE_TARGET_OPCODE(G_FCEIL) 661 662/// Floating point cosine. 663HANDLE_TARGET_OPCODE(G_FCOS) 664 665/// Floating point sine. 666HANDLE_TARGET_OPCODE(G_FSIN) 667 668/// Floating point square root. 669HANDLE_TARGET_OPCODE(G_FSQRT) 670 671/// Floating point floor. 672HANDLE_TARGET_OPCODE(G_FFLOOR) 673 674/// Floating point round to next integer. 675HANDLE_TARGET_OPCODE(G_FRINT) 676 677/// Floating point round to nearest integer. 678HANDLE_TARGET_OPCODE(G_FNEARBYINT) 679 680/// Generic AddressSpaceCast. 681HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 682 683/// Generic block address 684HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 685 686/// Generic jump table address 687HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 688 689/// Generic dynamic stack allocation. 690HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) 691 692/// Strict floating point instructions. 693HANDLE_TARGET_OPCODE(G_STRICT_FADD) 694HANDLE_TARGET_OPCODE(G_STRICT_FSUB) 695HANDLE_TARGET_OPCODE(G_STRICT_FMUL) 696HANDLE_TARGET_OPCODE(G_STRICT_FDIV) 697HANDLE_TARGET_OPCODE(G_STRICT_FREM) 698HANDLE_TARGET_OPCODE(G_STRICT_FMA) 699HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) 700 701/// read_register intrinsic 702HANDLE_TARGET_OPCODE(G_READ_REGISTER) 703 704/// write_register intrinsic 705HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) 706 707/// llvm.memcpy intrinsic 708HANDLE_TARGET_OPCODE(G_MEMCPY) 709 710/// llvm.memmove intrinsic 711HANDLE_TARGET_OPCODE(G_MEMMOVE) 712 713/// llvm.memset intrinsic 714HANDLE_TARGET_OPCODE(G_MEMSET) 715 716/// Vector reductions 717HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD) 718HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL) 719HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD) 720HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL) 721HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX) 722HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN) 723HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD) 724HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL) 725HANDLE_TARGET_OPCODE(G_VECREDUCE_AND) 726HANDLE_TARGET_OPCODE(G_VECREDUCE_OR) 727HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR) 728HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX) 729HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN) 730HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX) 731HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN) 732 733/// Marker for the end of the generic opcode. 734/// This is used to check if an opcode is in the range of the 735/// generic opcodes. 736HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_VECREDUCE_UMIN) 737 738/// BUILTIN_OP_END - This must be the last enum value in this list. 739/// The target-specific post-isel opcode values start here. 740HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 741