1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target-independent interfaces which should be 10// implemented by each target which is using a TableGen based code generator. 11// 12//===----------------------------------------------------------------------===// 13 14// Include all information about LLVM intrinsics. 15include "llvm/IR/Intrinsics.td" 16 17//===----------------------------------------------------------------------===// 18// Register file description - These classes are used to fill in the target 19// description classes. 20 21class HwMode<string FS> { 22 // A string representing subtarget features that turn on this HW mode. 23 // For example, "+feat1,-feat2" will indicate that the mode is active 24 // when "feat1" is enabled and "feat2" is disabled at the same time. 25 // Any other features are not checked. 26 // When multiple modes are used, they should be mutually exclusive, 27 // otherwise the results are unpredictable. 28 string Features = FS; 29} 30 31// A special mode recognized by tablegen. This mode is considered active 32// when no other mode is active. For targets that do not use specific hw 33// modes, this is the only mode. 34def DefaultMode : HwMode<"">; 35 36// A class used to associate objects with HW modes. It is only intended to 37// be used as a base class, where the derived class should contain a member 38// "Objects", which is a list of the same length as the list of modes. 39// The n-th element on the Objects list will be associated with the n-th 40// element on the Modes list. 41class HwModeSelect<list<HwMode> Ms> { 42 list<HwMode> Modes = Ms; 43} 44 45// A common class that implements a counterpart of ValueType, which is 46// dependent on a HW mode. This class inherits from ValueType itself, 47// which makes it possible to use objects of this class where ValueType 48// objects could be used. This is specifically applicable to selection 49// patterns. 50class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts> 51 : HwModeSelect<Ms>, ValueType<0, 0> { 52 // The length of this list must be the same as the length of Ms. 53 list<ValueType> Objects = Ts; 54} 55 56// A class representing the register size, spill size and spill alignment 57// in bits of a register. 58class RegInfo<int RS, int SS, int SA> { 59 int RegSize = RS; // Register size in bits. 60 int SpillSize = SS; // Spill slot size in bits. 61 int SpillAlignment = SA; // Spill slot alignment in bits. 62} 63 64// The register size/alignment information, parameterized by a HW mode. 65class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []> 66 : HwModeSelect<Ms> { 67 // The length of this list must be the same as the length of Ms. 68 list<RegInfo> Objects = Ts; 69} 70 71// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 72class SubRegIndex<int size, int offset = 0> { 73 string Namespace = ""; 74 75 // Size - Size (in bits) of the sub-registers represented by this index. 76 int Size = size; 77 78 // Offset - Offset of the first bit that is part of this sub-register index. 79 // Set it to -1 if the same index is used to represent sub-registers that can 80 // be at different offsets (for example when using an index to access an 81 // element in a register tuple). 82 int Offset = offset; 83 84 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 85 // This indicates that this SubRegIndex is the result of composing A and B. 86 // See ComposedSubRegIndex. 87 list<SubRegIndex> ComposedOf = []; 88 89 // CoveringSubRegIndices - A list of two or more sub-register indexes that 90 // cover this sub-register. 91 // 92 // This field should normally be left blank as TableGen can infer it. 93 // 94 // TableGen automatically detects sub-registers that straddle the registers 95 // in the SubRegs field of a Register definition. For example: 96 // 97 // Q0 = dsub_0 -> D0, dsub_1 -> D1 98 // Q1 = dsub_0 -> D2, dsub_1 -> D3 99 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 100 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 101 // 102 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given 103 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 104 // CoveringSubRegIndices = [dsub_1, dsub_2]. 105 list<SubRegIndex> CoveringSubRegIndices = []; 106} 107 108// ComposedSubRegIndex - A sub-register that is the result of composing A and B. 109// Offset is set to the sum of A and B's Offsets. Size is set to B's Size. 110class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> 111 : SubRegIndex<B.Size, !cond(!eq(A.Offset, -1): -1, 112 !eq(B.Offset, -1): -1, 113 true: !add(A.Offset, B.Offset))> { 114 // See SubRegIndex. 115 let ComposedOf = [A, B]; 116} 117 118// RegAltNameIndex - The alternate name set to use for register operands of 119// this register class when printing. 120class RegAltNameIndex { 121 string Namespace = ""; 122 123 // A set to be used if the name for a register is not defined in this set. 124 // This allows creating name sets with only a few alternative names. 125 RegAltNameIndex FallbackRegAltNameIndex = ?; 126} 127def NoRegAltName : RegAltNameIndex; 128 129// Register - You should define one instance of this class for each register 130// in the target machine. String n will become the "name" of the register. 131class Register<string n, list<string> altNames = []> { 132 string Namespace = ""; 133 string AsmName = n; 134 list<string> AltNames = altNames; 135 136 // Aliases - A list of registers that this register overlaps with. A read or 137 // modification of this register can potentially read or modify the aliased 138 // registers. 139 list<Register> Aliases = []; 140 141 // SubRegs - A list of registers that are parts of this register. Note these 142 // are "immediate" sub-registers and the registers within the list do not 143 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 144 // not [AX, AH, AL]. 145 list<Register> SubRegs = []; 146 147 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 148 // to address it. Sub-sub-register indices are automatically inherited from 149 // SubRegs. 150 list<SubRegIndex> SubRegIndices = []; 151 152 // RegAltNameIndices - The alternate name indices which are valid for this 153 // register. 154 list<RegAltNameIndex> RegAltNameIndices = []; 155 156 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 157 // These values can be determined by locating the <target>.h file in the 158 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 159 // order of these names correspond to the enumeration used by gcc. A value of 160 // -1 indicates that the gcc number is undefined and -2 that register number 161 // is invalid for this mode/flavour. 162 list<int> DwarfNumbers = []; 163 164 // CostPerUse - Additional cost of instructions using this register compared 165 // to other registers in its class. The register allocator will try to 166 // minimize the number of instructions using a register with a CostPerUse. 167 // This is used by the ARC target, by the ARM Thumb and x86-64 targets, where 168 // some registers require larger instruction encodings, by the RISC-V target, 169 // where some registers preclude using some C instructions. By making it a 170 // list, targets can have multiple cost models associated with each register 171 // and can choose one specific cost model per Machine Function by overriding 172 // TargetRegisterInfo::getRegisterCostTableIndex. Every target register will 173 // finally have an equal number of cost values which is the max of costPerUse 174 // values specified. Any mismatch in the cost values for a register will be 175 // filled with zeros. Restricted the cost type to uint8_t in the 176 // generated table. It will considerably reduce the table size. 177 list<int> CostPerUse = [0]; 178 179 // CoveredBySubRegs - When this bit is set, the value of this register is 180 // completely determined by the value of its sub-registers. For example, the 181 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 182 // covered by its sub-register AX. 183 bit CoveredBySubRegs = false; 184 185 // HWEncoding - The target specific hardware encoding for this register. 186 bits<16> HWEncoding = 0; 187 188 bit isArtificial = false; 189 190 // isConstant - This register always holds a constant value (e.g. the zero 191 // register in architectures such as MIPS) 192 bit isConstant = false; 193} 194 195// RegisterWithSubRegs - This can be used to define instances of Register which 196// need to specify sub-registers. 197// List "subregs" specifies which registers are sub-registers to this one. This 198// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 199// This allows the code generator to be careful not to put two values with 200// overlapping live ranges into registers which alias. 201class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 202 let SubRegs = subregs; 203} 204 205// DAGOperand - An empty base class that unifies RegisterClass's and other forms 206// of Operand's that are legal as type qualifiers in DAG patterns. This should 207// only ever be used for defining multiclasses that are polymorphic over both 208// RegisterClass's and other Operand's. 209class DAGOperand { 210 string OperandNamespace = "MCOI"; 211 string DecoderMethod = ""; 212} 213 214// RegisterClass - Now that all of the registers are defined, and aliases 215// between registers are defined, specify which registers belong to which 216// register classes. This also defines the default allocation order of 217// registers by register allocators. 218// 219class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 220 dag regList, RegAltNameIndex idx = NoRegAltName> 221 : DAGOperand { 222 string Namespace = namespace; 223 224 // The register size/alignment information, parameterized by a HW mode. 225 RegInfoByHwMode RegInfos; 226 227 // RegType - Specify the list ValueType of the registers in this register 228 // class. Note that all registers in a register class must have the same 229 // ValueTypes. This is a list because some targets permit storing different 230 // types in same register, for example vector values with 128-bit total size, 231 // but different count/size of items, like SSE on x86. 232 // 233 list<ValueType> RegTypes = regTypes; 234 235 // Size - Specify the spill size in bits of the registers. A default value of 236 // zero lets tablegen pick an appropriate size. 237 int Size = 0; 238 239 // Alignment - Specify the alignment required of the registers when they are 240 // stored or loaded to memory. 241 // 242 int Alignment = alignment; 243 244 // CopyCost - This value is used to specify the cost of copying a value 245 // between two registers in this register class. The default value is one 246 // meaning it takes a single instruction to perform the copying. A negative 247 // value means copying is extremely expensive or impossible. 248 int CopyCost = 1; 249 250 // MemberList - Specify which registers are in this class. If the 251 // allocation_order_* method are not specified, this also defines the order of 252 // allocation used by the register allocator. 253 // 254 dag MemberList = regList; 255 256 // AltNameIndex - The alternate register name to use when printing operands 257 // of this register class. Every register in the register class must have 258 // a valid alternate name for the given index. 259 RegAltNameIndex altNameIndex = idx; 260 261 // isAllocatable - Specify that the register class can be used for virtual 262 // registers and register allocation. Some register classes are only used to 263 // model instruction operand constraints, and should have isAllocatable = 0. 264 bit isAllocatable = true; 265 266 // AltOrders - List of alternative allocation orders. The default order is 267 // MemberList itself, and that is good enough for most targets since the 268 // register allocators automatically remove reserved registers and move 269 // callee-saved registers to the end. 270 list<dag> AltOrders = []; 271 272 // AltOrderSelect - The body of a function that selects the allocation order 273 // to use in a given machine function. The code will be inserted in a 274 // function like this: 275 // 276 // static inline unsigned f(const MachineFunction &MF) { ... } 277 // 278 // The function should return 0 to select the default order defined by 279 // MemberList, 1 to select the first AltOrders entry and so on. 280 code AltOrderSelect = [{}]; 281 282 // Specify allocation priority for register allocators using a greedy 283 // heuristic. Classes with higher priority values are assigned first. This is 284 // useful as it is sometimes beneficial to assign registers to highly 285 // constrained classes first. The value has to be in the range [0,31]. 286 int AllocationPriority = 0; 287 288 // Force register class to use greedy's global heuristic for all 289 // registers in this class. This should more aggressively try to 290 // avoid spilling in pathological cases. 291 bit GlobalPriority = false; 292 293 // Generate register pressure set for this register class and any class 294 // synthesized from it. Set to 0 to inhibit unneeded pressure sets. 295 bit GeneratePressureSet = true; 296 297 // Weight override for register pressure calculation. This is the value 298 // TargetRegisterClass::getRegClassWeight() will return. The weight is in 299 // units of pressure for this register class. If unset tablegen will 300 // calculate a weight based on a number of register units in this register 301 // class registers. The weight is per register. 302 int Weight = ?; 303 304 // The diagnostic type to present when referencing this operand in a match 305 // failure error message. If this is empty, the default Match_InvalidOperand 306 // diagnostic type will be used. If this is "<name>", a Match_<name> enum 307 // value will be generated and used for this operand type. The target 308 // assembly parser is responsible for converting this into a user-facing 309 // diagnostic message. 310 string DiagnosticType = ""; 311 312 // A diagnostic message to emit when an invalid value is provided for this 313 // register class when it is being used an an assembly operand. If this is 314 // non-empty, an anonymous diagnostic type enum value will be generated, and 315 // the assembly matcher will provide a function to map from diagnostic types 316 // to message strings. 317 string DiagnosticString = ""; 318 319 // Target-specific flags. This becomes the TSFlags field in TargetRegisterClass. 320 bits<8> TSFlags = 0; 321 322 // If set then consider this register class to be the base class for registers in 323 // its MemberList. The base class for registers present in multiple base register 324 // classes will be resolved in the order defined by this value, with lower values 325 // taking precedence over higher ones. Ties are resolved by enumeration order. 326 int BaseClassOrder = ?; 327} 328 329// The memberList in a RegisterClass is a dag of set operations. TableGen 330// evaluates these set operations and expand them into register lists. These 331// are the most common operation, see test/TableGen/SetTheory.td for more 332// examples of what is possible: 333// 334// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 335// register class, or a sub-expression. This is also the way to simply list 336// registers. 337// 338// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 339// 340// (and GPR, CSR) - Set intersection. All registers from the first set that are 341// also in the second set. 342// 343// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 344// numbered registers. Takes an optional 4th operand which is a stride to use 345// when generating the sequence. 346// 347// (shl GPR, 4) - Remove the first N elements. 348// 349// (trunc GPR, 4) - Truncate after the first N elements. 350// 351// (rotl GPR, 1) - Rotate N places to the left. 352// 353// (rotr GPR, 1) - Rotate N places to the right. 354// 355// (decimate GPR, 2) - Pick every N'th element, starting with the first. 356// 357// (interleave A, B, ...) - Interleave the elements from each argument list. 358// 359// All of these operators work on ordered sets, not lists. That means 360// duplicates are removed from sub-expressions. 361 362// Set operators. The rest is defined in TargetSelectionDAG.td. 363def sequence; 364def decimate; 365def interleave; 366 367// RegisterTuples - Automatically generate super-registers by forming tuples of 368// sub-registers. This is useful for modeling register sequence constraints 369// with pseudo-registers that are larger than the architectural registers. 370// 371// The sub-register lists are zipped together: 372// 373// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 374// 375// Generates the same registers as: 376// 377// let SubRegIndices = [sube, subo] in { 378// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 379// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 380// } 381// 382// The generated pseudo-registers inherit super-classes and fields from their 383// first sub-register. Most fields from the Register class are inferred, and 384// the AsmName and Dwarf numbers are cleared. 385// 386// RegisterTuples instances can be used in other set operations to form 387// register classes and so on. This is the only way of using the generated 388// registers. 389// 390// RegNames may be specified to supply asm names for the generated tuples. 391// If used must have the same size as the list of produced registers. 392class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs, 393 list<string> RegNames = []> { 394 // SubRegs - N lists of registers to be zipped up. Super-registers are 395 // synthesized from the first element of each SubRegs list, the second 396 // element and so on. 397 list<dag> SubRegs = Regs; 398 399 // SubRegIndices - N SubRegIndex instances. This provides the names of the 400 // sub-registers in the synthesized super-registers. 401 list<SubRegIndex> SubRegIndices = Indices; 402 403 // List of asm names for the generated tuple registers. 404 list<string> RegAsmNames = RegNames; 405} 406 407// RegisterCategory - This class is a list of RegisterClasses that belong to a 408// general cateogry --- e.g. "general purpose" or "fixed" registers. This is 409// useful for identifying registers in a generic way instead of having 410// information about a specific target's registers. 411class RegisterCategory<list<RegisterClass> classes> { 412 // Classes - A list of register classes that fall within the category. 413 list<RegisterClass> Classes = classes; 414} 415 416//===----------------------------------------------------------------------===// 417// DwarfRegNum - This class provides a mapping of the llvm register enumeration 418// to the register numbering used by gcc and gdb. These values are used by a 419// debug information writer to describe where values may be located during 420// execution. 421class DwarfRegNum<list<int> Numbers> { 422 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 423 // These values can be determined by locating the <target>.h file in the 424 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 425 // order of these names correspond to the enumeration used by gcc. A value of 426 // -1 indicates that the gcc number is undefined and -2 that register number 427 // is invalid for this mode/flavour. 428 list<int> DwarfNumbers = Numbers; 429} 430 431// DwarfRegAlias - This class declares that a given register uses the same dwarf 432// numbers as another one. This is useful for making it clear that the two 433// registers do have the same number. It also lets us build a mapping 434// from dwarf register number to llvm register. 435class DwarfRegAlias<Register reg> { 436 Register DwarfAlias = reg; 437} 438 439//===----------------------------------------------------------------------===// 440// Pull in the common support for MCPredicate (portable scheduling predicates). 441// 442include "llvm/Target/TargetInstrPredicate.td" 443 444//===----------------------------------------------------------------------===// 445// Pull in the common support for scheduling 446// 447include "llvm/Target/TargetSchedule.td" 448 449class Predicate; // Forward def 450 451class InstructionEncoding { 452 // Size of encoded instruction. 453 int Size; 454 455 // The "namespace" in which this instruction exists, on targets like ARM 456 // which multiple ISA namespaces exist. 457 string DecoderNamespace = ""; 458 459 // List of predicates which will be turned into isel matching code. 460 list<Predicate> Predicates = []; 461 462 string DecoderMethod = ""; 463 464 // Is the instruction decoder method able to completely determine if the 465 // given instruction is valid or not. If the TableGen definition of the 466 // instruction specifies bitpattern A??B where A and B are static bits, the 467 // hasCompleteDecoder flag says whether the decoder method fully handles the 468 // ?? space, i.e. if it is a final arbiter for the instruction validity. 469 // If not then the decoder attempts to continue decoding when the decoder 470 // method fails. 471 // 472 // This allows to handle situations where the encoding is not fully 473 // orthogonal. Example: 474 // * InstA with bitpattern 0b0000????, 475 // * InstB with bitpattern 0b000000?? but the associated decoder method 476 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11. 477 // 478 // The decoder tries to decode a bitpattern that matches both InstA and 479 // InstB bitpatterns first as InstB (because it is the most specific 480 // encoding). In the default case (hasCompleteDecoder = 1), when 481 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting 482 // hasCompleteDecoder = 0 in InstB, the decoder is informed that 483 // DecodeInstB() is not able to determine if all possible values of ?? are 484 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to 485 // decode the bitpattern as InstA too. 486 bit hasCompleteDecoder = true; 487} 488 489// Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies 490// an EncodingByHwMode, its Inst and Size members are ignored and Ts are used 491// to encode and decode based on HwMode. 492class EncodingByHwMode<list<HwMode> Ms = [], list<InstructionEncoding> Ts = []> 493 : HwModeSelect<Ms> { 494 // The length of this list must be the same as the length of Ms. 495 list<InstructionEncoding> Objects = Ts; 496} 497 498//===----------------------------------------------------------------------===// 499// Instruction set description - These classes correspond to the C++ classes in 500// the Target/TargetInstrInfo.h file. 501// 502class Instruction : InstructionEncoding { 503 string Namespace = ""; 504 505 dag OutOperandList; // An dag containing the MI def operand list. 506 dag InOperandList; // An dag containing the MI use operand list. 507 string AsmString = ""; // The .s format to print the instruction with. 508 509 // Allows specifying a canonical InstructionEncoding by HwMode. If non-empty, 510 // the Inst member of this Instruction is ignored. 511 EncodingByHwMode EncodingInfos; 512 513 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 514 // otherwise, uninitialized. 515 list<dag> Pattern; 516 517 // The follow state will eventually be inferred automatically from the 518 // instruction pattern. 519 520 list<Register> Uses = []; // Default to using no non-operand registers 521 list<Register> Defs = []; // Default to modifying no non-operand registers 522 523 // Predicates - List of predicates which will be turned into isel matching 524 // code. 525 list<Predicate> Predicates = []; 526 527 // Size - Size of encoded instruction, or zero if the size cannot be determined 528 // from the opcode. 529 int Size = 0; 530 531 // Code size, for instruction selection. 532 // FIXME: What does this actually mean? 533 int CodeSize = 0; 534 535 // Added complexity passed onto matching pattern. 536 int AddedComplexity = 0; 537 538 // Indicates if this is a pre-isel opcode that should be 539 // legalized/regbankselected/selected. 540 bit isPreISelOpcode = false; 541 542 // These bits capture information about the high-level semantics of the 543 // instruction. 544 bit isReturn = false; // Is this instruction a return instruction? 545 bit isBranch = false; // Is this instruction a branch instruction? 546 bit isEHScopeReturn = false; // Does this instruction end an EH scope? 547 bit isIndirectBranch = false; // Is this instruction an indirect branch? 548 bit isCompare = false; // Is this instruction a comparison instruction? 549 bit isMoveImm = false; // Is this instruction a move immediate instruction? 550 bit isMoveReg = false; // Is this instruction a move register instruction? 551 bit isBitcast = false; // Is this instruction a bitcast instruction? 552 bit isSelect = false; // Is this instruction a select instruction? 553 bit isBarrier = false; // Can control flow fall through this instruction? 554 bit isCall = false; // Is this instruction a call instruction? 555 bit isAdd = false; // Is this instruction an add instruction? 556 bit isTrap = false; // Is this instruction a trap instruction? 557 bit canFoldAsLoad = false; // Can this be folded as a simple memory operand? 558 bit mayLoad = ?; // Is it possible for this inst to read memory? 559 bit mayStore = ?; // Is it possible for this inst to write memory? 560 bit mayRaiseFPException = false; // Can this raise a floating-point exception? 561 bit isConvertibleToThreeAddress = false; // Can this 2-addr instruction promote? 562 bit isCommutable = false; // Is this 3 operand instruction commutable? 563 bit isTerminator = false; // Is this part of the terminator for a basic block? 564 bit isReMaterializable = false; // Is this instruction re-materializable? 565 bit isPredicable = false; // 1 means this instruction is predicable 566 // even if it does not have any operand 567 // tablegen can identify as a predicate 568 bit isUnpredicable = false; // 1 means this instruction is not predicable 569 // even if it _does_ have a predicate operand 570 bit hasDelaySlot = false; // Does this instruction have an delay slot? 571 bit usesCustomInserter = false; // Pseudo instr needing special help. 572 bit hasPostISelHook = false; // To be *adjusted* after isel by target hook. 573 bit hasCtrlDep = false; // Does this instruction r/w ctrl-flow chains? 574 bit isNotDuplicable = false; // Is it unsafe to duplicate this instruction? 575 bit isConvergent = false; // Is this instruction convergent? 576 bit isAuthenticated = false; // Does this instruction authenticate a pointer? 577 bit isAsCheapAsAMove = false; // As cheap (or cheaper) than a move instruction. 578 bit hasExtraSrcRegAllocReq = false; // Sources have special regalloc requirement? 579 bit hasExtraDefRegAllocReq = false; // Defs have special regalloc requirement? 580 bit isRegSequence = false; // Is this instruction a kind of reg sequence? 581 // If so, make sure to override 582 // TargetInstrInfo::getRegSequenceLikeInputs. 583 bit isPseudo = false; // Is this instruction a pseudo-instruction? 584 // If so, won't have encoding information for 585 // the [MC]CodeEmitter stuff. 586 bit isMeta = false; // Is this instruction a meta-instruction? 587 // If so, won't produce any output in the form of 588 // executable instructions 589 bit isExtractSubreg = false; // Is this instruction a kind of extract subreg? 590 // If so, make sure to override 591 // TargetInstrInfo::getExtractSubregLikeInputs. 592 bit isInsertSubreg = false; // Is this instruction a kind of insert subreg? 593 // If so, make sure to override 594 // TargetInstrInfo::getInsertSubregLikeInputs. 595 bit variadicOpsAreDefs = false; // Are variadic operands definitions? 596 597 // Does the instruction have side effects that are not captured by any 598 // operands of the instruction or other flags? 599 bit hasSideEffects = ?; 600 601 // Is this instruction a "real" instruction (with a distinct machine 602 // encoding), or is it a pseudo instruction used for codegen modeling 603 // purposes. 604 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 605 // instructions can (and often do) still have encoding information 606 // associated with them. Once we've migrated all of them over to true 607 // pseudo-instructions that are lowered to real instructions prior to 608 // the printer/emitter, we can remove this attribute and just use isPseudo. 609 // 610 // The intended use is: 611 // isPseudo: Does not have encoding information and should be expanded, 612 // at the latest, during lowering to MCInst. 613 // 614 // isCodeGenOnly: Does have encoding information and can go through to the 615 // CodeEmitter unchanged, but duplicates a canonical instruction 616 // definition's encoding and should be ignored when constructing the 617 // assembler match tables. 618 bit isCodeGenOnly = false; 619 620 // Is this instruction a pseudo instruction for use by the assembler parser. 621 bit isAsmParserOnly = false; 622 623 // This instruction is not expected to be queried for scheduling latencies 624 // and therefore needs no scheduling information even for a complete 625 // scheduling model. 626 bit hasNoSchedulingInfo = false; 627 628 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 629 630 // Scheduling information from TargetSchedule.td. 631 list<SchedReadWrite> SchedRW; 632 633 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 634 635 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 636 /// be encoded into the output machineinstr. 637 string DisableEncoding = ""; 638 639 string PostEncoderMethod = ""; 640 641 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 642 bits<64> TSFlags = 0; 643 644 ///@name Assembler Parser Support 645 ///@{ 646 647 string AsmMatchConverter = ""; 648 649 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 650 /// two-operand matcher inst-alias for a three operand instruction. 651 /// For example, the arm instruction "add r3, r3, r5" can be written 652 /// as "add r3, r5". The constraint is of the same form as a tied-operand 653 /// constraint. For example, "$Rn = $Rd". 654 string TwoOperandAliasConstraint = ""; 655 656 /// Assembler variant name to use for this instruction. If specified then 657 /// instruction will be presented only in MatchTable for this variant. If 658 /// not specified then assembler variants will be determined based on 659 /// AsmString 660 string AsmVariantName = ""; 661 662 ///@} 663 664 /// UseNamedOperandTable - If set, the operand indices of this instruction 665 /// can be queried via the getNamedOperandIdx() function which is generated 666 /// by TableGen. 667 bit UseNamedOperandTable = false; 668 669 /// Should generate helper functions that help you to map a logical operand's 670 /// index to the underlying MIOperand's index. 671 /// In most architectures logical operand indicies are equal to 672 /// MIOperand indicies, but for some CISC architectures, a logical operand 673 /// might be consist of multiple MIOperand (e.g. a logical operand that 674 /// uses complex address mode). 675 bit UseLogicalOperandMappings = false; 676 677 /// Should FastISel ignore this instruction. For certain ISAs, they have 678 /// instructions which map to the same ISD Opcode, value type operands and 679 /// instruction selection predicates. FastISel cannot handle such cases, but 680 /// SelectionDAG can. 681 bit FastISelShouldIgnore = false; 682 683 /// HasPositionOrder: Indicate tablegen to sort the instructions by record 684 /// ID, so that instruction that is defined earlier can be sorted earlier 685 /// in the assembly matching table. 686 bit HasPositionOrder = false; 687} 688 689/// Defines a Pat match between compressed and uncompressed instruction. 690/// The relationship and helper function generation are handled by 691/// CompressInstEmitter backend. 692class CompressPat<dag input, dag output, list<Predicate> predicates = []> { 693 /// Uncompressed instruction description. 694 dag Input = input; 695 /// Compressed instruction description. 696 dag Output = output; 697 /// Predicates that must be true for this to match. 698 list<Predicate> Predicates = predicates; 699 /// Duplicate match when tied operand is just different. 700 bit isCompressOnly = false; 701} 702 703/// Defines an additional encoding that disassembles to the given instruction 704/// Like Instruction, the Inst and SoftFail fields are omitted to allow targets 705// to specify their size. 706class AdditionalEncoding<Instruction I> : InstructionEncoding { 707 Instruction AliasOf = I; 708} 709 710/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 711/// Which instruction it expands to and how the operands map from the 712/// pseudo. 713class PseudoInstExpansion<dag Result> { 714 dag ResultInst = Result; // The instruction to generate. 715 bit isPseudo = true; 716} 717 718/// Predicates - These are extra conditionals which are turned into instruction 719/// selector matching code. Currently each predicate is just a string. 720class Predicate<string cond> { 721 string CondString = cond; 722 723 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 724 /// matcher, this is true. Targets should set this by inheriting their 725 /// feature from the AssemblerPredicate class in addition to Predicate. 726 bit AssemblerMatcherPredicate = false; 727 728 /// AssemblerCondDag - Set of subtarget features being tested used 729 /// as alternative condition string used for assembler matcher. Must be used 730 /// with (all_of) to indicate that all features must be present, or (any_of) 731 /// to indicate that at least one must be. The required lack of presence of 732 /// a feature can be tested using a (not) node including the feature. 733 /// e.g. "(all_of ModeThumb)" is translated to "(Bits & ModeThumb) != 0". 734 /// "(all_of (not ModeThumb))" is translated to 735 /// "(Bits & ModeThumb) == 0". 736 /// "(all_of ModeThumb, FeatureThumb2)" is translated to 737 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 738 /// "(any_of ModeTumb, FeatureThumb2)" is translated to 739 /// "(Bits & ModeThumb) != 0 || (Bits & FeatureThumb2) != 0". 740 /// all_of and any_of cannot be combined in a single dag, instead multiple 741 /// predicates can be placed onto Instruction definitions. 742 dag AssemblerCondDag; 743 744 /// PredicateName - User-level name to use for the predicate. Mainly for use 745 /// in diagnostics such as missing feature errors in the asm matcher. 746 string PredicateName = ""; 747 748 /// Setting this to '1' indicates that the predicate must be recomputed on 749 /// every function change. Most predicates can leave this at '0'. 750 /// 751 /// Ignored by SelectionDAG, it always recomputes the predicate on every use. 752 bit RecomputePerFunction = false; 753} 754 755/// NoHonorSignDependentRounding - This predicate is true if support for 756/// sign-dependent-rounding is not enabled. 757def NoHonorSignDependentRounding 758 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 759 760class Requires<list<Predicate> preds> { 761 list<Predicate> Predicates = preds; 762} 763 764/// ops definition - This is just a simple marker used to identify the operand 765/// list for an instruction. outs and ins are identical both syntactically and 766/// semantically; they are used to define def operands and use operands to 767/// improve readability. This should be used like this: 768/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 769def ops; 770def outs; 771def ins; 772 773/// variable_ops definition - Mark this instruction as taking a variable number 774/// of operands. 775def variable_ops; 776 777/// variable-length instruction encoding utilities. 778/// The `ascend` operator should be used like this: 779/// (ascend 0b0010, 0b1101) 780/// Which represent a seqence of encoding fragments placing from LSB to MSB. 781/// Thus, in this case the final encoding will be 0b1101_0010. 782/// The arguments for `ascend` can either be `bits` or another DAG. 783def ascend; 784/// In addition, we can use `descend` to describe an encoding that places 785/// its arguments (i.e. encoding fragments) from MSB to LSB. For instance: 786/// (descend 0b0010, 0b1101) 787/// This results in an encoding of 0b0010_1101. 788def descend; 789/// The `operand` operator should be used like this: 790/// (operand "$src", 4) 791/// Which represents a 4-bit encoding for an instruction operand named `$src`. 792def operand; 793/// Similar to `operand`, we can reference only part of the operand's encoding: 794/// (slice "$src", 6, 8) 795/// (slice "$src", 8, 6) 796/// Both DAG represent bit 6 to 8 (total of 3 bits) in the encoding of operand 797/// `$src`. 798def slice; 799/// You can use `encoder` or `decoder` to specify a custom encoder or decoder 800/// function for a specific `operand` or `slice` directive. For example: 801/// (operand "$src", 4, (encoder "encodeMyImm")) 802/// (slice "$src", 8, 6, (encoder "encodeMyReg")) 803/// (operand "$src", 4, (encoder "encodeMyImm"), (decoder "decodeMyImm")) 804/// The ordering of `encoder` and `decoder` in the same `operand` or `slice` 805/// doesn't matter. 806/// Note that currently we cannot assign different decoders in the same 807/// (instruction) operand. 808def encoder; 809def decoder; 810 811/// PointerLikeRegClass - Values that are designed to have pointer width are 812/// derived from this. TableGen treats the register class as having a symbolic 813/// type that it doesn't know, and resolves the actual regclass to use by using 814/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 815class PointerLikeRegClass<int Kind> { 816 int RegClassKind = Kind; 817} 818 819 820/// ptr_rc definition - Mark this operand as being a pointer value whose 821/// register class is resolved dynamically via a callback to TargetInstrInfo. 822/// FIXME: We should probably change this to a class which contain a list of 823/// flags. But currently we have but one flag. 824def ptr_rc : PointerLikeRegClass<0>; 825 826/// unknown definition - Mark this operand as being of unknown type, causing 827/// it to be resolved by inference in the context it is used. 828class unknown_class; 829def unknown : unknown_class; 830 831/// AsmOperandClass - Representation for the kinds of operands which the target 832/// specific parser can create and the assembly matcher may need to distinguish. 833/// 834/// Operand classes are used to define the order in which instructions are 835/// matched, to ensure that the instruction which gets matched for any 836/// particular list of operands is deterministic. 837/// 838/// The target specific parser must be able to classify a parsed operand into a 839/// unique class which does not partially overlap with any other classes. It can 840/// match a subset of some other class, in which case the super class field 841/// should be defined. 842class AsmOperandClass { 843 /// The name to use for this class, which should be usable as an enum value. 844 string Name = ?; 845 846 /// The super classes of this operand. 847 list<AsmOperandClass> SuperClasses = []; 848 849 /// The name of the method on the target specific operand to call to test 850 /// whether the operand is an instance of this class. If not set, this will 851 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 852 /// signature should be: 853 /// bool isFoo() const; 854 string PredicateMethod = ?; 855 856 /// The name of the method on the target specific operand to call to add the 857 /// target specific operand to an MCInst. If not set, this will default to 858 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 859 /// signature should be: 860 /// void addFooOperands(MCInst &Inst, unsigned N) const; 861 string RenderMethod = ?; 862 863 /// The name of the method on the target specific operand to call to custom 864 /// handle the operand parsing. This is useful when the operands do not relate 865 /// to immediates or registers and are very instruction specific (as flags to 866 /// set in a processor register, coprocessor number, ...). 867 string ParserMethod = ?; 868 869 // The diagnostic type to present when referencing this operand in a 870 // match failure error message. By default, use a generic "invalid operand" 871 // diagnostic. The target AsmParser maps these codes to text. 872 string DiagnosticType = ""; 873 874 /// A diagnostic message to emit when an invalid value is provided for this 875 /// operand. 876 string DiagnosticString = ""; 877 878 /// Set to 1 if this operand is optional and not always required. Typically, 879 /// the AsmParser will emit an error when it finishes parsing an 880 /// instruction if it hasn't matched all the operands yet. However, this 881 /// error will be suppressed if all of the remaining unmatched operands are 882 /// marked as IsOptional. 883 /// 884 /// Optional arguments must be at the end of the operand list. 885 bit IsOptional = false; 886 887 /// The name of the method on the target specific asm parser that returns the 888 /// default operand for this optional operand. This method is only used if 889 /// IsOptional == 1. If not set, this will default to "defaultFooOperands", 890 /// where Foo is the AsmOperandClass name. The method signature should be: 891 /// std::unique_ptr<MCParsedAsmOperand> defaultFooOperands() const; 892 string DefaultMethod = ?; 893} 894 895def ImmAsmOperand : AsmOperandClass { 896 let Name = "Imm"; 897} 898 899/// Operand Types - These provide the built-in operand types that may be used 900/// by a target. Targets can optionally provide their own operand types as 901/// needed, though this should not be needed for RISC targets. 902class Operand<ValueType ty> : DAGOperand { 903 ValueType Type = ty; 904 string PrintMethod = "printOperand"; 905 string EncoderMethod = ""; 906 bit hasCompleteDecoder = true; 907 string OperandType = "OPERAND_UNKNOWN"; 908 dag MIOperandInfo = (ops); 909 910 // MCOperandPredicate - Optionally, a code fragment operating on 911 // const MCOperand &MCOp, and returning a bool, to indicate if 912 // the value of MCOp is valid for the specific subclass of Operand 913 code MCOperandPredicate; 914 915 // ParserMatchClass - The "match class" that operands of this type fit 916 // in. Match classes are used to define the order in which instructions are 917 // match, to ensure that which instructions gets matched is deterministic. 918 // 919 // The target specific parser must be able to classify an parsed operand into 920 // a unique class, which does not partially overlap with any other classes. It 921 // can match a subset of some other class, in which case the AsmOperandClass 922 // should declare the other operand as one of its super classes. 923 AsmOperandClass ParserMatchClass = ImmAsmOperand; 924} 925 926class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> 927 : DAGOperand { 928 // RegClass - The register class of the operand. 929 RegisterClass RegClass = regclass; 930 // PrintMethod - The target method to call to print register operands of 931 // this type. The method normally will just use an alt-name index to look 932 // up the name to print. Default to the generic printOperand(). 933 string PrintMethod = pm; 934 935 // EncoderMethod - The target method name to call to encode this register 936 // operand. 937 string EncoderMethod = ""; 938 939 // ParserMatchClass - The "match class" that operands of this type fit 940 // in. Match classes are used to define the order in which instructions are 941 // match, to ensure that which instructions gets matched is deterministic. 942 // 943 // The target specific parser must be able to classify an parsed operand into 944 // a unique class, which does not partially overlap with any other classes. It 945 // can match a subset of some other class, in which case the AsmOperandClass 946 // should declare the other operand as one of its super classes. 947 AsmOperandClass ParserMatchClass; 948 949 string OperandType = "OPERAND_REGISTER"; 950 951 // When referenced in the result of a CodeGen pattern, GlobalISel will 952 // normally copy the matched operand to the result. When this is set, it will 953 // emit a special copy that will replace zero-immediates with the specified 954 // zero-register. 955 Register GIZeroRegister = ?; 956} 957 958let OperandType = "OPERAND_IMMEDIATE" in { 959def i1imm : Operand<i1>; 960def i8imm : Operand<i8>; 961def i16imm : Operand<i16>; 962def i32imm : Operand<i32>; 963def i64imm : Operand<i64>; 964 965def f32imm : Operand<f32>; 966def f64imm : Operand<f64>; 967} 968 969// Register operands for generic instructions don't have an MVT, but do have 970// constraints linking the operands (e.g. all operands of a G_ADD must 971// have the same LLT). 972class TypedOperand<string Ty> : Operand<untyped> { 973 let OperandType = Ty; 974 bit IsPointer = false; 975 bit IsImmediate = false; 976} 977 978def type0 : TypedOperand<"OPERAND_GENERIC_0">; 979def type1 : TypedOperand<"OPERAND_GENERIC_1">; 980def type2 : TypedOperand<"OPERAND_GENERIC_2">; 981def type3 : TypedOperand<"OPERAND_GENERIC_3">; 982def type4 : TypedOperand<"OPERAND_GENERIC_4">; 983def type5 : TypedOperand<"OPERAND_GENERIC_5">; 984 985let IsPointer = true in { 986 def ptype0 : TypedOperand<"OPERAND_GENERIC_0">; 987 def ptype1 : TypedOperand<"OPERAND_GENERIC_1">; 988 def ptype2 : TypedOperand<"OPERAND_GENERIC_2">; 989 def ptype3 : TypedOperand<"OPERAND_GENERIC_3">; 990 def ptype4 : TypedOperand<"OPERAND_GENERIC_4">; 991 def ptype5 : TypedOperand<"OPERAND_GENERIC_5">; 992} 993 994// untyped_imm is for operands where isImm() will be true. It currently has no 995// special behaviour and is only used for clarity. 996def untyped_imm_0 : TypedOperand<"OPERAND_GENERIC_IMM_0"> { 997 let IsImmediate = true; 998} 999 1000/// zero_reg definition - Special node to stand for the zero register. 1001/// 1002def zero_reg; 1003 1004/// undef_tied_input - Special node to indicate an input register tied 1005/// to an output which defaults to IMPLICIT_DEF. 1006def undef_tied_input; 1007 1008/// All operands which the MC layer classifies as predicates should inherit from 1009/// this class in some manner. This is already handled for the most commonly 1010/// used PredicateOperand, but may be useful in other circumstances. 1011class PredicateOp; 1012 1013/// OperandWithDefaultOps - This Operand class can be used as the parent class 1014/// for an Operand that needs to be initialized with a default value if 1015/// no value is supplied in a pattern. This class can be used to simplify the 1016/// pattern definitions for instructions that have target specific flags 1017/// encoded as immediate operands. 1018class OperandWithDefaultOps<ValueType ty, dag defaultops> 1019 : Operand<ty> { 1020 dag DefaultOps = defaultops; 1021} 1022 1023/// PredicateOperand - This can be used to define a predicate operand for an 1024/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 1025/// AlwaysVal specifies the value of this predicate when set to "always 1026/// execute". 1027class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 1028 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp { 1029 let MIOperandInfo = OpTypes; 1030} 1031 1032/// OptionalDefOperand - This is used to define a optional definition operand 1033/// for an instruction. DefaultOps is the register the operand represents if 1034/// none is supplied, e.g. zero_reg. 1035class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 1036 : OperandWithDefaultOps<ty, defaultops> { 1037 let MIOperandInfo = OpTypes; 1038} 1039 1040 1041// InstrInfo - This class should only be instantiated once to provide parameters 1042// which are global to the target machine. 1043// 1044class InstrInfo { 1045 // Target can specify its instructions in either big or little-endian formats. 1046 // For instance, while both Sparc and PowerPC are big-endian platforms, the 1047 // Sparc manual specifies its instructions in the format [31..0] (big), while 1048 // PowerPC specifies them using the format [0..31] (little). 1049 bit isLittleEndianEncoding = false; 1050 1051 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset 1052 // by default, and TableGen will infer their value from the instruction 1053 // pattern when possible. 1054 // 1055 // Normally, TableGen will issue an error if it can't infer the value of a 1056 // property that hasn't been set explicitly. When guessInstructionProperties 1057 // is set, it will guess a safe value instead. 1058 // 1059 // This option is a temporary migration help. It will go away. 1060 bit guessInstructionProperties = true; 1061 1062 // TableGen's instruction encoder generator has support for matching operands 1063 // to bit-field variables both by name and by position. Support for matching 1064 // by position is DEPRECATED, and WILL BE REMOVED. Positional matching is 1065 // confusing to use, and makes it very easy to accidentally write buggy 1066 // instruction definitions. 1067 // 1068 // In previous versions of LLVM, the ability to match operands by position was 1069 // enabled unconditionally. It is now controllable by this option -- and 1070 // disabled by default. The previous behavior can be restored by setting this 1071 // option to true. 1072 // 1073 // This option is temporary, and will go away once all in-tree targets have 1074 // migrated. 1075 // 1076 // TODO: clean up and remove these options. 1077 bit useDeprecatedPositionallyEncodedOperands = false; 1078 1079 // If positional encoding rules are used for the encoder generator, they may 1080 // also need to be used by the decoder generator -- if so, enable this 1081 // variable. 1082 // 1083 // This option is a no-op unless useDeprecatedPositionallyEncodedOperands is 1084 // true. 1085 // 1086 // This option is temporary, and will go away once all in-tree targets have 1087 // migrated. 1088 bit decodePositionallyEncodedOperands = false; 1089 1090 // When set, this indicates that there will be no overlap between those 1091 // operands that are matched by ordering (positional operands) and those 1092 // matched by name. 1093 // 1094 // This is a no-op unless useDeprecatedPositionallyEncodedOperands is true 1095 // (though it does modify the "would've used positional operand XXX" error.) 1096 // 1097 // This option is temporary, and will go away once all in-tree targets have 1098 // migrated. 1099 bit noNamedPositionallyEncodedOperands = false; 1100} 1101 1102// Standard Pseudo Instructions. 1103// This list must match TargetOpcodes.def. 1104// Only these instructions are allowed in the TargetOpcode namespace. 1105// Ensure mayLoad and mayStore have a default value, so as not to break 1106// targets that set guessInstructionProperties=0. Any local definition of 1107// mayLoad/mayStore takes precedence over these default values. 1108class StandardPseudoInstruction : Instruction { 1109 let mayLoad = false; 1110 let mayStore = false; 1111 let isCodeGenOnly = true; 1112 let isPseudo = true; 1113 let hasNoSchedulingInfo = true; 1114 let Namespace = "TargetOpcode"; 1115} 1116def PHI : StandardPseudoInstruction { 1117 let OutOperandList = (outs unknown:$dst); 1118 let InOperandList = (ins variable_ops); 1119 let AsmString = "PHINODE"; 1120 let hasSideEffects = false; 1121} 1122def INLINEASM : StandardPseudoInstruction { 1123 let OutOperandList = (outs); 1124 let InOperandList = (ins variable_ops); 1125 let AsmString = ""; 1126 let hasSideEffects = false; // Note side effect is encoded in an operand. 1127} 1128def INLINEASM_BR : StandardPseudoInstruction { 1129 let OutOperandList = (outs); 1130 let InOperandList = (ins variable_ops); 1131 let AsmString = ""; 1132 // Unlike INLINEASM, this is always treated as having side-effects. 1133 let hasSideEffects = true; 1134 // Despite potentially branching, this instruction is intentionally _not_ 1135 // marked as a terminator or a branch. 1136} 1137def CFI_INSTRUCTION : StandardPseudoInstruction { 1138 let OutOperandList = (outs); 1139 let InOperandList = (ins i32imm:$id); 1140 let AsmString = ""; 1141 let hasCtrlDep = true; 1142 let hasSideEffects = false; 1143 let isNotDuplicable = true; 1144 let isMeta = true; 1145} 1146def EH_LABEL : StandardPseudoInstruction { 1147 let OutOperandList = (outs); 1148 let InOperandList = (ins i32imm:$id); 1149 let AsmString = ""; 1150 let hasCtrlDep = true; 1151 let hasSideEffects = false; 1152 let isNotDuplicable = true; 1153 let isMeta = true; 1154} 1155def GC_LABEL : StandardPseudoInstruction { 1156 let OutOperandList = (outs); 1157 let InOperandList = (ins i32imm:$id); 1158 let AsmString = ""; 1159 let hasCtrlDep = true; 1160 let hasSideEffects = false; 1161 let isNotDuplicable = true; 1162 let isMeta = true; 1163} 1164def ANNOTATION_LABEL : StandardPseudoInstruction { 1165 let OutOperandList = (outs); 1166 let InOperandList = (ins i32imm:$id); 1167 let AsmString = ""; 1168 let hasCtrlDep = true; 1169 let hasSideEffects = false; 1170 let isNotDuplicable = true; 1171} 1172def KILL : StandardPseudoInstruction { 1173 let OutOperandList = (outs); 1174 let InOperandList = (ins variable_ops); 1175 let AsmString = ""; 1176 let hasSideEffects = false; 1177 let isMeta = true; 1178} 1179def EXTRACT_SUBREG : StandardPseudoInstruction { 1180 let OutOperandList = (outs unknown:$dst); 1181 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 1182 let AsmString = ""; 1183 let hasSideEffects = false; 1184} 1185def INSERT_SUBREG : StandardPseudoInstruction { 1186 let OutOperandList = (outs unknown:$dst); 1187 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 1188 let AsmString = ""; 1189 let hasSideEffects = false; 1190 let Constraints = "$supersrc = $dst"; 1191} 1192def IMPLICIT_DEF : StandardPseudoInstruction { 1193 let OutOperandList = (outs unknown:$dst); 1194 let InOperandList = (ins); 1195 let AsmString = ""; 1196 let hasSideEffects = false; 1197 let isReMaterializable = true; 1198 let isAsCheapAsAMove = true; 1199 let isMeta = true; 1200} 1201def SUBREG_TO_REG : StandardPseudoInstruction { 1202 let OutOperandList = (outs unknown:$dst); 1203 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 1204 let AsmString = ""; 1205 let hasSideEffects = false; 1206} 1207def COPY_TO_REGCLASS : StandardPseudoInstruction { 1208 let OutOperandList = (outs unknown:$dst); 1209 let InOperandList = (ins unknown:$src, i32imm:$regclass); 1210 let AsmString = ""; 1211 let hasSideEffects = false; 1212 let isAsCheapAsAMove = true; 1213} 1214def DBG_VALUE : StandardPseudoInstruction { 1215 let OutOperandList = (outs); 1216 let InOperandList = (ins variable_ops); 1217 let AsmString = "DBG_VALUE"; 1218 let hasSideEffects = false; 1219 let isMeta = true; 1220} 1221def DBG_VALUE_LIST : StandardPseudoInstruction { 1222 let OutOperandList = (outs); 1223 let InOperandList = (ins variable_ops); 1224 let AsmString = "DBG_VALUE_LIST"; 1225 let hasSideEffects = 0; 1226 let isMeta = true; 1227} 1228def DBG_INSTR_REF : StandardPseudoInstruction { 1229 let OutOperandList = (outs); 1230 let InOperandList = (ins variable_ops); 1231 let AsmString = "DBG_INSTR_REF"; 1232 let hasSideEffects = false; 1233 let isMeta = true; 1234} 1235def DBG_PHI : StandardPseudoInstruction { 1236 let OutOperandList = (outs); 1237 let InOperandList = (ins variable_ops); 1238 let AsmString = "DBG_PHI"; 1239 let hasSideEffects = 0; 1240 let isMeta = true; 1241} 1242def DBG_LABEL : StandardPseudoInstruction { 1243 let OutOperandList = (outs); 1244 let InOperandList = (ins unknown:$label); 1245 let AsmString = "DBG_LABEL"; 1246 let hasSideEffects = false; 1247 let isMeta = true; 1248} 1249def REG_SEQUENCE : StandardPseudoInstruction { 1250 let OutOperandList = (outs unknown:$dst); 1251 let InOperandList = (ins unknown:$supersrc, variable_ops); 1252 let AsmString = ""; 1253 let hasSideEffects = false; 1254 let isAsCheapAsAMove = true; 1255} 1256def COPY : StandardPseudoInstruction { 1257 let OutOperandList = (outs unknown:$dst); 1258 let InOperandList = (ins unknown:$src); 1259 let AsmString = ""; 1260 let hasSideEffects = false; 1261 let isAsCheapAsAMove = true; 1262 let hasNoSchedulingInfo = false; 1263} 1264def BUNDLE : StandardPseudoInstruction { 1265 let OutOperandList = (outs); 1266 let InOperandList = (ins variable_ops); 1267 let AsmString = "BUNDLE"; 1268 let hasSideEffects = false; 1269} 1270def LIFETIME_START : StandardPseudoInstruction { 1271 let OutOperandList = (outs); 1272 let InOperandList = (ins i32imm:$id); 1273 let AsmString = "LIFETIME_START"; 1274 let hasSideEffects = false; 1275 let isMeta = true; 1276} 1277def LIFETIME_END : StandardPseudoInstruction { 1278 let OutOperandList = (outs); 1279 let InOperandList = (ins i32imm:$id); 1280 let AsmString = "LIFETIME_END"; 1281 let hasSideEffects = false; 1282 let isMeta = true; 1283} 1284def PSEUDO_PROBE : StandardPseudoInstruction { 1285 let OutOperandList = (outs); 1286 let InOperandList = (ins i64imm:$guid, i64imm:$index, i8imm:$type, i32imm:$attr); 1287 let AsmString = "PSEUDO_PROBE"; 1288 let hasSideEffects = 1; 1289 let isMeta = true; 1290} 1291def ARITH_FENCE : StandardPseudoInstruction { 1292 let OutOperandList = (outs unknown:$dst); 1293 let InOperandList = (ins unknown:$src); 1294 let AsmString = ""; 1295 let hasSideEffects = false; 1296 let Constraints = "$src = $dst"; 1297 let isMeta = true; 1298} 1299 1300def STACKMAP : StandardPseudoInstruction { 1301 let OutOperandList = (outs); 1302 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops); 1303 let hasSideEffects = true; 1304 let isCall = true; 1305 let mayLoad = true; 1306 let usesCustomInserter = true; 1307} 1308def PATCHPOINT : StandardPseudoInstruction { 1309 let OutOperandList = (outs unknown:$dst); 1310 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee, 1311 i32imm:$nargs, i32imm:$cc, variable_ops); 1312 let hasSideEffects = true; 1313 let isCall = true; 1314 let mayLoad = true; 1315 let usesCustomInserter = true; 1316} 1317def STATEPOINT : StandardPseudoInstruction { 1318 let OutOperandList = (outs variable_ops); 1319 let InOperandList = (ins variable_ops); 1320 let usesCustomInserter = true; 1321 let mayLoad = true; 1322 let mayStore = true; 1323 let hasSideEffects = true; 1324 let isCall = true; 1325} 1326def LOAD_STACK_GUARD : StandardPseudoInstruction { 1327 let OutOperandList = (outs ptr_rc:$dst); 1328 let InOperandList = (ins); 1329 let mayLoad = true; 1330 bit isReMaterializable = true; 1331 let hasSideEffects = false; 1332 bit isPseudo = true; 1333} 1334def PREALLOCATED_SETUP : StandardPseudoInstruction { 1335 let OutOperandList = (outs); 1336 let InOperandList = (ins i32imm:$a); 1337 let usesCustomInserter = true; 1338 let hasSideEffects = true; 1339} 1340def PREALLOCATED_ARG : StandardPseudoInstruction { 1341 let OutOperandList = (outs ptr_rc:$loc); 1342 let InOperandList = (ins i32imm:$a, i32imm:$b); 1343 let usesCustomInserter = true; 1344 let hasSideEffects = true; 1345} 1346def LOCAL_ESCAPE : StandardPseudoInstruction { 1347 // This instruction is really just a label. It has to be part of the chain so 1348 // that it doesn't get dropped from the DAG, but it produces nothing and has 1349 // no side effects. 1350 let OutOperandList = (outs); 1351 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id); 1352 let hasSideEffects = false; 1353 let hasCtrlDep = true; 1354} 1355def FAULTING_OP : StandardPseudoInstruction { 1356 let OutOperandList = (outs unknown:$dst); 1357 let InOperandList = (ins variable_ops); 1358 let usesCustomInserter = true; 1359 let hasSideEffects = true; 1360 let mayLoad = true; 1361 let mayStore = true; 1362 let isTerminator = true; 1363 let isBranch = true; 1364} 1365def PATCHABLE_OP : StandardPseudoInstruction { 1366 let OutOperandList = (outs); 1367 let InOperandList = (ins variable_ops); 1368 let usesCustomInserter = true; 1369 let mayLoad = true; 1370 let mayStore = true; 1371 let hasSideEffects = true; 1372} 1373def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction { 1374 let OutOperandList = (outs); 1375 let InOperandList = (ins); 1376 let AsmString = "# XRay Function Enter."; 1377 let usesCustomInserter = true; 1378 let hasSideEffects = true; 1379} 1380def PATCHABLE_RET : StandardPseudoInstruction { 1381 let OutOperandList = (outs); 1382 let InOperandList = (ins variable_ops); 1383 let AsmString = "# XRay Function Patchable RET."; 1384 let usesCustomInserter = true; 1385 let hasSideEffects = true; 1386 let isTerminator = true; 1387 let isReturn = true; 1388} 1389def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction { 1390 let OutOperandList = (outs); 1391 let InOperandList = (ins); 1392 let AsmString = "# XRay Function Exit."; 1393 let usesCustomInserter = true; 1394 let hasSideEffects = true; 1395 let isReturn = false; // Original return instruction will follow 1396} 1397def PATCHABLE_TAIL_CALL : StandardPseudoInstruction { 1398 let OutOperandList = (outs); 1399 let InOperandList = (ins variable_ops); 1400 let AsmString = "# XRay Tail Call Exit."; 1401 let usesCustomInserter = true; 1402 let hasSideEffects = true; 1403 let isReturn = true; 1404} 1405def PATCHABLE_EVENT_CALL : StandardPseudoInstruction { 1406 let OutOperandList = (outs); 1407 let InOperandList = (ins ptr_rc:$event, unknown:$size); 1408 let AsmString = "# XRay Custom Event Log."; 1409 let usesCustomInserter = true; 1410 let isCall = true; 1411 let mayLoad = true; 1412 let mayStore = true; 1413 let hasSideEffects = true; 1414} 1415def PATCHABLE_TYPED_EVENT_CALL : StandardPseudoInstruction { 1416 let OutOperandList = (outs); 1417 let InOperandList = (ins unknown:$type, ptr_rc:$event, unknown:$size); 1418 let AsmString = "# XRay Typed Event Log."; 1419 let usesCustomInserter = true; 1420 let isCall = true; 1421 let mayLoad = true; 1422 let mayStore = true; 1423 let hasSideEffects = true; 1424} 1425def FENTRY_CALL : StandardPseudoInstruction { 1426 let OutOperandList = (outs); 1427 let InOperandList = (ins); 1428 let AsmString = "# FEntry call"; 1429 let usesCustomInserter = true; 1430 let isCall = true; 1431 let mayLoad = true; 1432 let mayStore = true; 1433 let hasSideEffects = true; 1434} 1435def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction { 1436 let OutOperandList = (outs); 1437 let InOperandList = (ins variable_ops); 1438 let AsmString = ""; 1439 let hasSideEffects = true; 1440} 1441def MEMBARRIER : StandardPseudoInstruction { 1442 let OutOperandList = (outs); 1443 let InOperandList = (ins); 1444 let AsmString = ""; 1445 let hasSideEffects = true; 1446 let Size = 0; 1447 let isMeta = true; 1448} 1449 1450// Generic opcodes used in GlobalISel. 1451include "llvm/Target/GenericOpcodes.td" 1452 1453//===----------------------------------------------------------------------===// 1454// AsmParser - This class can be implemented by targets that wish to implement 1455// .s file parsing. 1456// 1457// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 1458// syntax on X86 for example). 1459// 1460class AsmParser { 1461 // AsmParserClassName - This specifies the suffix to use for the asmparser 1462 // class. Generated AsmParser classes are always prefixed with the target 1463 // name. 1464 string AsmParserClassName = "AsmParser"; 1465 1466 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 1467 // function of the AsmParser class to call on every matched instruction. 1468 // This can be used to perform target specific instruction post-processing. 1469 string AsmParserInstCleanup = ""; 1470 1471 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand 1472 // written register name matcher 1473 bit ShouldEmitMatchRegisterName = true; 1474 1475 // Set to true if the target needs a generated 'alternative register name' 1476 // matcher. 1477 // 1478 // This generates a function which can be used to lookup registers from 1479 // their aliases. This function will fail when called on targets where 1480 // several registers share the same alias (i.e. not a 1:1 mapping). 1481 bit ShouldEmitMatchRegisterAltName = false; 1482 1483 // Set to true if MatchRegisterName and MatchRegisterAltName functions 1484 // should be generated even if there are duplicate register names. The 1485 // target is responsible for coercing aliased registers as necessary 1486 // (e.g. in validateTargetOperandClass), and there are no guarantees about 1487 // which numeric register identifier will be returned in the case of 1488 // multiple matches. 1489 bit AllowDuplicateRegisterNames = false; 1490 1491 // HasMnemonicFirst - Set to false if target instructions don't always 1492 // start with a mnemonic as the first token. 1493 bit HasMnemonicFirst = true; 1494 1495 // ReportMultipleNearMisses - 1496 // When 0, the assembly matcher reports an error for one encoding or operand 1497 // that did not match the parsed instruction. 1498 // When 1, the assembly matcher returns a list of encodings that were close 1499 // to matching the parsed instruction, so to allow more detailed error 1500 // messages. 1501 bit ReportMultipleNearMisses = false; 1502 1503 // OperandParserMethod - If non-empty, this is the name of a custom 1504 // member function of the AsmParser class to call for every instruction 1505 // operand to be parsed. 1506 string OperandParserMethod = ""; 1507 1508 // CallCustomParserForAllOperands - Set to true if the custom parser 1509 // method shall be called for all operands as opposed to only those 1510 // that have their own specified custom parsers. 1511 bit CallCustomParserForAllOperands = false; 1512} 1513def DefaultAsmParser : AsmParser; 1514 1515//===----------------------------------------------------------------------===// 1516// AsmParserVariant - Subtargets can have multiple different assembly parsers 1517// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 1518// implemented by targets to describe such variants. 1519// 1520class AsmParserVariant { 1521 // Variant - AsmParsers can be of multiple different variants. Variants are 1522 // used to support targets that need to parse multiple formats for the 1523 // assembly language. 1524 int Variant = 0; 1525 1526 // Name - The AsmParser variant name (e.g., AT&T vs Intel). 1527 string Name = ""; 1528 1529 // CommentDelimiter - If given, the delimiter string used to recognize 1530 // comments which are hard coded in the .td assembler strings for individual 1531 // instructions. 1532 string CommentDelimiter = ""; 1533 1534 // RegisterPrefix - If given, the token prefix which indicates a register 1535 // token. This is used by the matcher to automatically recognize hard coded 1536 // register tokens as constrained registers, instead of tokens, for the 1537 // purposes of matching. 1538 string RegisterPrefix = ""; 1539 1540 // TokenizingCharacters - Characters that are standalone tokens 1541 string TokenizingCharacters = "[]*!"; 1542 1543 // SeparatorCharacters - Characters that are not tokens 1544 string SeparatorCharacters = " \t,"; 1545 1546 // BreakCharacters - Characters that start new identifiers 1547 string BreakCharacters = ""; 1548} 1549def DefaultAsmParserVariant : AsmParserVariant; 1550 1551// Operators for combining SubtargetFeatures in AssemblerPredicates 1552def any_of; 1553def all_of; 1554 1555/// AssemblerPredicate - This is a Predicate that can be used when the assembler 1556/// matches instructions and aliases. 1557class AssemblerPredicate<dag cond, string name = ""> { 1558 bit AssemblerMatcherPredicate = true; 1559 dag AssemblerCondDag = cond; 1560 string PredicateName = name; 1561} 1562 1563/// TokenAlias - This class allows targets to define assembler token 1564/// operand aliases. That is, a token literal operand which is equivalent 1565/// to another, canonical, token literal. For example, ARM allows: 1566/// vmov.u32 s4, #0 -> vmov.i32, #0 1567/// 'u32' is a more specific designator for the 32-bit integer type specifier 1568/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 1569/// def : TokenAlias<".u32", ".i32">; 1570/// 1571/// This works by marking the match class of 'From' as a subclass of the 1572/// match class of 'To'. 1573class TokenAlias<string From, string To> { 1574 string FromToken = From; 1575 string ToToken = To; 1576} 1577 1578/// MnemonicAlias - This class allows targets to define assembler mnemonic 1579/// aliases. This should be used when all forms of one mnemonic are accepted 1580/// with a different mnemonic. For example, X86 allows: 1581/// sal %al, 1 -> shl %al, 1 1582/// sal %ax, %cl -> shl %ax, %cl 1583/// sal %eax, %cl -> shl %eax, %cl 1584/// etc. Though "sal" is accepted with many forms, all of them are directly 1585/// translated to a shl, so it can be handled with (in the case of X86, it 1586/// actually has one for each suffix as well): 1587/// def : MnemonicAlias<"sal", "shl">; 1588/// 1589/// Mnemonic aliases are mapped before any other translation in the match phase, 1590/// and do allow Requires predicates, e.g.: 1591/// 1592/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 1593/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 1594/// 1595/// Mnemonic aliases can also be constrained to specific variants, e.g.: 1596/// 1597/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 1598/// 1599/// If no variant (e.g., "att" or "intel") is specified then the alias is 1600/// applied unconditionally. 1601class MnemonicAlias<string From, string To, string VariantName = ""> { 1602 string FromMnemonic = From; 1603 string ToMnemonic = To; 1604 string AsmVariantName = VariantName; 1605 1606 // Predicates - Predicates that must be true for this remapping to happen. 1607 list<Predicate> Predicates = []; 1608} 1609 1610/// InstAlias - This defines an alternate assembly syntax that is allowed to 1611/// match an instruction that has a different (more canonical) assembly 1612/// representation. 1613class InstAlias<string Asm, dag Result, int Emit = 1, string VariantName = ""> { 1614 string AsmString = Asm; // The .s format to match the instruction with. 1615 dag ResultInst = Result; // The MCInst to generate. 1616 1617 // This determines which order the InstPrinter detects aliases for 1618 // printing. A larger value makes the alias more likely to be 1619 // emitted. The Instruction's own definition is notionally 0.5, so 0 1620 // disables printing and 1 enables it if there are no conflicting aliases. 1621 int EmitPriority = Emit; 1622 1623 // Predicates - Predicates that must be true for this to match. 1624 list<Predicate> Predicates = []; 1625 1626 // If the instruction specified in Result has defined an AsmMatchConverter 1627 // then setting this to 1 will cause the alias to use the AsmMatchConverter 1628 // function when converting the OperandVector into an MCInst instead of the 1629 // function that is generated by the dag Result. 1630 // Setting this to 0 will cause the alias to ignore the Result instruction's 1631 // defined AsmMatchConverter and instead use the function generated by the 1632 // dag Result. 1633 bit UseInstAsmMatchConverter = true; 1634 1635 // Assembler variant name to use for this alias. If not specified then 1636 // assembler variants will be determined based on AsmString 1637 string AsmVariantName = VariantName; 1638} 1639 1640//===----------------------------------------------------------------------===// 1641// AsmWriter - This class can be implemented by targets that need to customize 1642// the format of the .s file writer. 1643// 1644// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 1645// on X86 for example). 1646// 1647class AsmWriter { 1648 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 1649 // class. Generated AsmWriter classes are always prefixed with the target 1650 // name. 1651 string AsmWriterClassName = "InstPrinter"; 1652 1653 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to 1654 // the various print methods. 1655 // FIXME: Remove after all ports are updated. 1656 int PassSubtarget = 0; 1657 1658 // Variant - AsmWriters can be of multiple different variants. Variants are 1659 // used to support targets that need to emit assembly code in ways that are 1660 // mostly the same for different targets, but have minor differences in 1661 // syntax. If the asmstring contains {|} characters in them, this integer 1662 // will specify which alternative to use. For example "{x|y|z}" with Variant 1663 // == 1, will expand to "y". 1664 int Variant = 0; 1665} 1666def DefaultAsmWriter : AsmWriter; 1667 1668 1669//===----------------------------------------------------------------------===// 1670// Target - This class contains the "global" target information 1671// 1672class Target { 1673 // InstructionSet - Instruction set description for this target. 1674 InstrInfo InstructionSet; 1675 1676 // AssemblyParsers - The AsmParser instances available for this target. 1677 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 1678 1679 /// AssemblyParserVariants - The AsmParserVariant instances available for 1680 /// this target. 1681 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 1682 1683 // AssemblyWriters - The AsmWriter instances available for this target. 1684 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 1685 1686 // AllowRegisterRenaming - Controls whether this target allows 1687 // post-register-allocation renaming of registers. This is done by 1688 // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1 1689 // for all opcodes if this flag is set to 0. 1690 int AllowRegisterRenaming = 0; 1691} 1692 1693//===----------------------------------------------------------------------===// 1694// SubtargetFeature - A characteristic of the chip set. 1695// 1696class SubtargetFeature<string n, string a, string v, string d, 1697 list<SubtargetFeature> i = []> { 1698 // Name - Feature name. Used by command line (-mattr=) to determine the 1699 // appropriate target chip. 1700 // 1701 string Name = n; 1702 1703 // Attribute - Attribute to be set by feature. 1704 // 1705 string Attribute = a; 1706 1707 // Value - Value the attribute to be set to by feature. 1708 // 1709 string Value = v; 1710 1711 // Desc - Feature description. Used by command line (-mattr=) to display help 1712 // information. 1713 // 1714 string Desc = d; 1715 1716 // Implies - Features that this feature implies are present. If one of those 1717 // features isn't set, then this one shouldn't be set either. 1718 // 1719 list<SubtargetFeature> Implies = i; 1720} 1721 1722/// Specifies a Subtarget feature that this instruction is deprecated on. 1723class Deprecated<SubtargetFeature dep> { 1724 SubtargetFeature DeprecatedFeatureMask = dep; 1725} 1726 1727/// A custom predicate used to determine if an instruction is 1728/// deprecated or not. 1729class ComplexDeprecationPredicate<string dep> { 1730 string ComplexDeprecationPredicate = dep; 1731} 1732 1733//===----------------------------------------------------------------------===// 1734// Processor chip sets - These values represent each of the chip sets supported 1735// by the scheduler. Each Processor definition requires corresponding 1736// instruction itineraries. 1737// 1738class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f, 1739 list<SubtargetFeature> tunef = []> { 1740 // Name - Chip set name. Used by command line (-mcpu=) to determine the 1741 // appropriate target chip. 1742 // 1743 string Name = n; 1744 1745 // SchedModel - The machine model for scheduling and instruction cost. 1746 // 1747 SchedMachineModel SchedModel = NoSchedModel; 1748 1749 // ProcItin - The scheduling information for the target processor. 1750 // 1751 ProcessorItineraries ProcItin = pi; 1752 1753 // Features - list of 1754 list<SubtargetFeature> Features = f; 1755 1756 // TuneFeatures - list of features for tuning for this CPU. If the target 1757 // supports -mtune, this should contain the list of features used to make 1758 // microarchitectural optimization decisions for a given processor. While 1759 // Features should contain the architectural features for the processor. 1760 list<SubtargetFeature> TuneFeatures = tunef; 1761} 1762 1763// ProcessorModel allows subtargets to specify the more general 1764// SchedMachineModel instead if a ProcessorItinerary. Subtargets will 1765// gradually move to this newer form. 1766// 1767// Although this class always passes NoItineraries to the Processor 1768// class, the SchedMachineModel may still define valid Itineraries. 1769class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f, 1770 list<SubtargetFeature> tunef = []> 1771 : Processor<n, NoItineraries, f, tunef> { 1772 let SchedModel = m; 1773} 1774 1775//===----------------------------------------------------------------------===// 1776// InstrMapping - This class is used to create mapping tables to relate 1777// instructions with each other based on the values specified in RowFields, 1778// ColFields, KeyCol and ValueCols. 1779// 1780class InstrMapping { 1781 // FilterClass - Used to limit search space only to the instructions that 1782 // define the relationship modeled by this InstrMapping record. 1783 string FilterClass; 1784 1785 // RowFields - List of fields/attributes that should be same for all the 1786 // instructions in a row of the relation table. Think of this as a set of 1787 // properties shared by all the instructions related by this relationship 1788 // model and is used to categorize instructions into subgroups. For instance, 1789 // if we want to define a relation that maps 'Add' instruction to its 1790 // predicated forms, we can define RowFields like this: 1791 // 1792 // let RowFields = BaseOp 1793 // All add instruction predicated/non-predicated will have to set their BaseOp 1794 // to the same value. 1795 // 1796 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } 1797 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } 1798 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' } 1799 list<string> RowFields = []; 1800 1801 // List of fields/attributes that are same for all the instructions 1802 // in a column of the relation table. 1803 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged 1804 // based on the 'predSense' values. All the instruction in a specific 1805 // column have the same value and it is fixed for the column according 1806 // to the values set in 'ValueCols'. 1807 list<string> ColFields = []; 1808 1809 // Values for the fields/attributes listed in 'ColFields'. 1810 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction 1811 // that models this relation) should be non-predicated. 1812 // In the example above, 'Add' is the key instruction. 1813 list<string> KeyCol = []; 1814 1815 // List of values for the fields/attributes listed in 'ColFields', one for 1816 // each column in the relation table. 1817 // 1818 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the 1819 // table. First column requires all the instructions to have predSense 1820 // set to 'true' and second column requires it to be 'false'. 1821 list<list<string> > ValueCols = []; 1822} 1823 1824//===----------------------------------------------------------------------===// 1825// Pull in the common support for calling conventions. 1826// 1827include "llvm/Target/TargetCallingConv.td" 1828 1829//===----------------------------------------------------------------------===// 1830// Pull in the common support for DAG isel generation. 1831// 1832include "llvm/Target/TargetSelectionDAG.td" 1833 1834//===----------------------------------------------------------------------===// 1835// Pull in the common support for Global ISel register bank info generation. 1836// 1837include "llvm/Target/GlobalISel/RegisterBank.td" 1838 1839//===----------------------------------------------------------------------===// 1840// Pull in the common support for DAG isel generation. 1841// 1842include "llvm/Target/GlobalISel/Target.td" 1843 1844//===----------------------------------------------------------------------===// 1845// Pull in the common support for the Global ISel DAG-based selector generation. 1846// 1847include "llvm/Target/GlobalISel/SelectionDAGCompat.td" 1848 1849//===----------------------------------------------------------------------===// 1850// Pull in the common support for Pfm Counters generation. 1851// 1852include "llvm/Target/TargetPfmCounters.td" 1853