1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target-independent interfaces which should be 10// implemented by each target which is using a TableGen based code generator. 11// 12//===----------------------------------------------------------------------===// 13 14// Include all information about LLVM intrinsics. 15include "llvm/IR/Intrinsics.td" 16 17//===----------------------------------------------------------------------===// 18// Register file description - These classes are used to fill in the target 19// description classes. 20 21class HwMode<string FS> { 22 // A string representing subtarget features that turn on this HW mode. 23 // For example, "+feat1,-feat2" will indicate that the mode is active 24 // when "feat1" is enabled and "feat2" is disabled at the same time. 25 // Any other features are not checked. 26 // When multiple modes are used, they should be mutually exclusive, 27 // otherwise the results are unpredictable. 28 string Features = FS; 29} 30 31// A special mode recognized by tablegen. This mode is considered active 32// when no other mode is active. For targets that do not use specific hw 33// modes, this is the only mode. 34def DefaultMode : HwMode<"">; 35 36// A class used to associate objects with HW modes. It is only intended to 37// be used as a base class, where the derived class should contain a member 38// "Objects", which is a list of the same length as the list of modes. 39// The n-th element on the Objects list will be associated with the n-th 40// element on the Modes list. 41class HwModeSelect<list<HwMode> Ms> { 42 list<HwMode> Modes = Ms; 43} 44 45// A common class that implements a counterpart of ValueType, which is 46// dependent on a HW mode. This class inherits from ValueType itself, 47// which makes it possible to use objects of this class where ValueType 48// objects could be used. This is specifically applicable to selection 49// patterns. 50class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts> 51 : HwModeSelect<Ms>, ValueType<0, 0> { 52 // The length of this list must be the same as the length of Ms. 53 list<ValueType> Objects = Ts; 54} 55 56// A class representing the register size, spill size and spill alignment 57// in bits of a register. 58class RegInfo<int RS, int SS, int SA> { 59 int RegSize = RS; // Register size in bits. 60 int SpillSize = SS; // Spill slot size in bits. 61 int SpillAlignment = SA; // Spill slot alignment in bits. 62} 63 64// The register size/alignment information, parameterized by a HW mode. 65class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []> 66 : HwModeSelect<Ms> { 67 // The length of this list must be the same as the length of Ms. 68 list<RegInfo> Objects = Ts; 69} 70 71// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 72class SubRegIndex<int size, int offset = 0> { 73 string Namespace = ""; 74 75 // Size - Size (in bits) of the sub-registers represented by this index. 76 int Size = size; 77 78 // Offset - Offset of the first bit that is part of this sub-register index. 79 // Set it to -1 if the same index is used to represent sub-registers that can 80 // be at different offsets (for example when using an index to access an 81 // element in a register tuple). 82 int Offset = offset; 83 84 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 85 // This indicates that this SubRegIndex is the result of composing A and B. 86 // See ComposedSubRegIndex. 87 list<SubRegIndex> ComposedOf = []; 88 89 // CoveringSubRegIndices - A list of two or more sub-register indexes that 90 // cover this sub-register. 91 // 92 // This field should normally be left blank as TableGen can infer it. 93 // 94 // TableGen automatically detects sub-registers that straddle the registers 95 // in the SubRegs field of a Register definition. For example: 96 // 97 // Q0 = dsub_0 -> D0, dsub_1 -> D1 98 // Q1 = dsub_0 -> D2, dsub_1 -> D3 99 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 100 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 101 // 102 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given 103 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 104 // CoveringSubRegIndices = [dsub_1, dsub_2]. 105 list<SubRegIndex> CoveringSubRegIndices = []; 106} 107 108// ComposedSubRegIndex - A sub-register that is the result of composing A and B. 109// Offset is set to the sum of A and B's Offsets. Size is set to B's Size. 110class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> 111 : SubRegIndex<B.Size, !cond(!eq(A.Offset, -1): -1, 112 !eq(B.Offset, -1): -1, 113 true: !add(A.Offset, B.Offset))> { 114 // See SubRegIndex. 115 let ComposedOf = [A, B]; 116} 117 118// RegAltNameIndex - The alternate name set to use for register operands of 119// this register class when printing. 120class RegAltNameIndex { 121 string Namespace = ""; 122 123 // A set to be used if the name for a register is not defined in this set. 124 // This allows creating name sets with only a few alternative names. 125 RegAltNameIndex FallbackRegAltNameIndex = ?; 126} 127def NoRegAltName : RegAltNameIndex; 128 129// Register - You should define one instance of this class for each register 130// in the target machine. String n will become the "name" of the register. 131class Register<string n, list<string> altNames = []> { 132 string Namespace = ""; 133 string AsmName = n; 134 list<string> AltNames = altNames; 135 136 // Aliases - A list of registers that this register overlaps with. A read or 137 // modification of this register can potentially read or modify the aliased 138 // registers. 139 list<Register> Aliases = []; 140 141 // SubRegs - A list of registers that are parts of this register. Note these 142 // are "immediate" sub-registers and the registers within the list do not 143 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 144 // not [AX, AH, AL]. 145 list<Register> SubRegs = []; 146 147 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 148 // to address it. Sub-sub-register indices are automatically inherited from 149 // SubRegs. 150 list<SubRegIndex> SubRegIndices = []; 151 152 // RegAltNameIndices - The alternate name indices which are valid for this 153 // register. 154 list<RegAltNameIndex> RegAltNameIndices = []; 155 156 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 157 // These values can be determined by locating the <target>.h file in the 158 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 159 // order of these names correspond to the enumeration used by gcc. A value of 160 // -1 indicates that the gcc number is undefined and -2 that register number 161 // is invalid for this mode/flavour. 162 list<int> DwarfNumbers = []; 163 164 // CostPerUse - Additional cost of instructions using this register compared 165 // to other registers in its class. The register allocator will try to 166 // minimize the number of instructions using a register with a CostPerUse. 167 // This is used by the ARC target, by the ARM Thumb and x86-64 targets, where 168 // some registers require larger instruction encodings, by the RISC-V target, 169 // where some registers preclude using some C instructions. By making it a 170 // list, targets can have multiple cost models associated with each register 171 // and can choose one specific cost model per Machine Function by overriding 172 // TargetRegisterInfo::getRegisterCostTableIndex. Every target register will 173 // finally have an equal number of cost values which is the max of costPerUse 174 // values specified. Any mismatch in the cost values for a register will be 175 // filled with zeros. Restricted the cost type to uint8_t in the 176 // generated table. It will considerably reduce the table size. 177 list<int> CostPerUse = [0]; 178 179 // CoveredBySubRegs - When this bit is set, the value of this register is 180 // completely determined by the value of its sub-registers. For example, the 181 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 182 // covered by its sub-register AX. 183 bit CoveredBySubRegs = false; 184 185 // HWEncoding - The target specific hardware encoding for this register. 186 bits<16> HWEncoding = 0; 187 188 bit isArtificial = false; 189} 190 191// RegisterWithSubRegs - This can be used to define instances of Register which 192// need to specify sub-registers. 193// List "subregs" specifies which registers are sub-registers to this one. This 194// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 195// This allows the code generator to be careful not to put two values with 196// overlapping live ranges into registers which alias. 197class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 198 let SubRegs = subregs; 199} 200 201// DAGOperand - An empty base class that unifies RegisterClass's and other forms 202// of Operand's that are legal as type qualifiers in DAG patterns. This should 203// only ever be used for defining multiclasses that are polymorphic over both 204// RegisterClass's and other Operand's. 205class DAGOperand { 206 string OperandNamespace = "MCOI"; 207 string DecoderMethod = ""; 208} 209 210// RegisterClass - Now that all of the registers are defined, and aliases 211// between registers are defined, specify which registers belong to which 212// register classes. This also defines the default allocation order of 213// registers by register allocators. 214// 215class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 216 dag regList, RegAltNameIndex idx = NoRegAltName> 217 : DAGOperand { 218 string Namespace = namespace; 219 220 // The register size/alignment information, parameterized by a HW mode. 221 RegInfoByHwMode RegInfos; 222 223 // RegType - Specify the list ValueType of the registers in this register 224 // class. Note that all registers in a register class must have the same 225 // ValueTypes. This is a list because some targets permit storing different 226 // types in same register, for example vector values with 128-bit total size, 227 // but different count/size of items, like SSE on x86. 228 // 229 list<ValueType> RegTypes = regTypes; 230 231 // Size - Specify the spill size in bits of the registers. A default value of 232 // zero lets tablegen pick an appropriate size. 233 int Size = 0; 234 235 // Alignment - Specify the alignment required of the registers when they are 236 // stored or loaded to memory. 237 // 238 int Alignment = alignment; 239 240 // CopyCost - This value is used to specify the cost of copying a value 241 // between two registers in this register class. The default value is one 242 // meaning it takes a single instruction to perform the copying. A negative 243 // value means copying is extremely expensive or impossible. 244 int CopyCost = 1; 245 246 // MemberList - Specify which registers are in this class. If the 247 // allocation_order_* method are not specified, this also defines the order of 248 // allocation used by the register allocator. 249 // 250 dag MemberList = regList; 251 252 // AltNameIndex - The alternate register name to use when printing operands 253 // of this register class. Every register in the register class must have 254 // a valid alternate name for the given index. 255 RegAltNameIndex altNameIndex = idx; 256 257 // isAllocatable - Specify that the register class can be used for virtual 258 // registers and register allocation. Some register classes are only used to 259 // model instruction operand constraints, and should have isAllocatable = 0. 260 bit isAllocatable = true; 261 262 // AltOrders - List of alternative allocation orders. The default order is 263 // MemberList itself, and that is good enough for most targets since the 264 // register allocators automatically remove reserved registers and move 265 // callee-saved registers to the end. 266 list<dag> AltOrders = []; 267 268 // AltOrderSelect - The body of a function that selects the allocation order 269 // to use in a given machine function. The code will be inserted in a 270 // function like this: 271 // 272 // static inline unsigned f(const MachineFunction &MF) { ... } 273 // 274 // The function should return 0 to select the default order defined by 275 // MemberList, 1 to select the first AltOrders entry and so on. 276 code AltOrderSelect = [{}]; 277 278 // Specify allocation priority for register allocators using a greedy 279 // heuristic. Classes with higher priority values are assigned first. This is 280 // useful as it is sometimes beneficial to assign registers to highly 281 // constrained classes first. The value has to be in the range [0,63]. 282 // Values >= 32 should be used with care since they may overlap with other 283 // fields in the allocator's priority heuristics. 284 int AllocationPriority = 0; 285 286 // Generate register pressure set for this register class and any class 287 // synthesized from it. Set to 0 to inhibit unneeded pressure sets. 288 bit GeneratePressureSet = true; 289 290 // Weight override for register pressure calculation. This is the value 291 // TargetRegisterClass::getRegClassWeight() will return. The weight is in 292 // units of pressure for this register class. If unset tablegen will 293 // calculate a weight based on a number of register units in this register 294 // class registers. The weight is per register. 295 int Weight = ?; 296 297 // The diagnostic type to present when referencing this operand in a match 298 // failure error message. If this is empty, the default Match_InvalidOperand 299 // diagnostic type will be used. If this is "<name>", a Match_<name> enum 300 // value will be generated and used for this operand type. The target 301 // assembly parser is responsible for converting this into a user-facing 302 // diagnostic message. 303 string DiagnosticType = ""; 304 305 // A diagnostic message to emit when an invalid value is provided for this 306 // register class when it is being used an an assembly operand. If this is 307 // non-empty, an anonymous diagnostic type enum value will be generated, and 308 // the assembly matcher will provide a function to map from diagnostic types 309 // to message strings. 310 string DiagnosticString = ""; 311 312 // Target-specific flags. This becomes the TSFlags field in TargetRegisterClass. 313 bits<8> TSFlags = 0; 314} 315 316// The memberList in a RegisterClass is a dag of set operations. TableGen 317// evaluates these set operations and expand them into register lists. These 318// are the most common operation, see test/TableGen/SetTheory.td for more 319// examples of what is possible: 320// 321// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 322// register class, or a sub-expression. This is also the way to simply list 323// registers. 324// 325// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 326// 327// (and GPR, CSR) - Set intersection. All registers from the first set that are 328// also in the second set. 329// 330// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 331// numbered registers. Takes an optional 4th operand which is a stride to use 332// when generating the sequence. 333// 334// (shl GPR, 4) - Remove the first N elements. 335// 336// (trunc GPR, 4) - Truncate after the first N elements. 337// 338// (rotl GPR, 1) - Rotate N places to the left. 339// 340// (rotr GPR, 1) - Rotate N places to the right. 341// 342// (decimate GPR, 2) - Pick every N'th element, starting with the first. 343// 344// (interleave A, B, ...) - Interleave the elements from each argument list. 345// 346// All of these operators work on ordered sets, not lists. That means 347// duplicates are removed from sub-expressions. 348 349// Set operators. The rest is defined in TargetSelectionDAG.td. 350def sequence; 351def decimate; 352def interleave; 353 354// RegisterTuples - Automatically generate super-registers by forming tuples of 355// sub-registers. This is useful for modeling register sequence constraints 356// with pseudo-registers that are larger than the architectural registers. 357// 358// The sub-register lists are zipped together: 359// 360// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 361// 362// Generates the same registers as: 363// 364// let SubRegIndices = [sube, subo] in { 365// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 366// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 367// } 368// 369// The generated pseudo-registers inherit super-classes and fields from their 370// first sub-register. Most fields from the Register class are inferred, and 371// the AsmName and Dwarf numbers are cleared. 372// 373// RegisterTuples instances can be used in other set operations to form 374// register classes and so on. This is the only way of using the generated 375// registers. 376// 377// RegNames may be specified to supply asm names for the generated tuples. 378// If used must have the same size as the list of produced registers. 379class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs, 380 list<string> RegNames = []> { 381 // SubRegs - N lists of registers to be zipped up. Super-registers are 382 // synthesized from the first element of each SubRegs list, the second 383 // element and so on. 384 list<dag> SubRegs = Regs; 385 386 // SubRegIndices - N SubRegIndex instances. This provides the names of the 387 // sub-registers in the synthesized super-registers. 388 list<SubRegIndex> SubRegIndices = Indices; 389 390 // List of asm names for the generated tuple registers. 391 list<string> RegAsmNames = RegNames; 392} 393 394// RegisterCategory - This class is a list of RegisterClasses that belong to a 395// general cateogry --- e.g. "general purpose" or "fixed" registers. This is 396// useful for identifying registers in a generic way instead of having 397// information about a specific target's registers. 398class RegisterCategory<list<RegisterClass> classes> { 399 // Classes - A list of register classes that fall within the category. 400 list<RegisterClass> Classes = classes; 401} 402 403//===----------------------------------------------------------------------===// 404// DwarfRegNum - This class provides a mapping of the llvm register enumeration 405// to the register numbering used by gcc and gdb. These values are used by a 406// debug information writer to describe where values may be located during 407// execution. 408class DwarfRegNum<list<int> Numbers> { 409 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 410 // These values can be determined by locating the <target>.h file in the 411 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 412 // order of these names correspond to the enumeration used by gcc. A value of 413 // -1 indicates that the gcc number is undefined and -2 that register number 414 // is invalid for this mode/flavour. 415 list<int> DwarfNumbers = Numbers; 416} 417 418// DwarfRegAlias - This class declares that a given register uses the same dwarf 419// numbers as another one. This is useful for making it clear that the two 420// registers do have the same number. It also lets us build a mapping 421// from dwarf register number to llvm register. 422class DwarfRegAlias<Register reg> { 423 Register DwarfAlias = reg; 424} 425 426//===----------------------------------------------------------------------===// 427// Pull in the common support for MCPredicate (portable scheduling predicates). 428// 429include "llvm/Target/TargetInstrPredicate.td" 430 431//===----------------------------------------------------------------------===// 432// Pull in the common support for scheduling 433// 434include "llvm/Target/TargetSchedule.td" 435 436class Predicate; // Forward def 437 438class InstructionEncoding { 439 // Size of encoded instruction. 440 int Size; 441 442 // The "namespace" in which this instruction exists, on targets like ARM 443 // which multiple ISA namespaces exist. 444 string DecoderNamespace = ""; 445 446 // List of predicates which will be turned into isel matching code. 447 list<Predicate> Predicates = []; 448 449 string DecoderMethod = ""; 450 451 // Is the instruction decoder method able to completely determine if the 452 // given instruction is valid or not. If the TableGen definition of the 453 // instruction specifies bitpattern A??B where A and B are static bits, the 454 // hasCompleteDecoder flag says whether the decoder method fully handles the 455 // ?? space, i.e. if it is a final arbiter for the instruction validity. 456 // If not then the decoder attempts to continue decoding when the decoder 457 // method fails. 458 // 459 // This allows to handle situations where the encoding is not fully 460 // orthogonal. Example: 461 // * InstA with bitpattern 0b0000????, 462 // * InstB with bitpattern 0b000000?? but the associated decoder method 463 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11. 464 // 465 // The decoder tries to decode a bitpattern that matches both InstA and 466 // InstB bitpatterns first as InstB (because it is the most specific 467 // encoding). In the default case (hasCompleteDecoder = 1), when 468 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting 469 // hasCompleteDecoder = 0 in InstB, the decoder is informed that 470 // DecodeInstB() is not able to determine if all possible values of ?? are 471 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to 472 // decode the bitpattern as InstA too. 473 bit hasCompleteDecoder = true; 474} 475 476// Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies 477// an EncodingByHwMode, its Inst and Size members are ignored and Ts are used 478// to encode and decode based on HwMode. 479class EncodingByHwMode<list<HwMode> Ms = [], list<InstructionEncoding> Ts = []> 480 : HwModeSelect<Ms> { 481 // The length of this list must be the same as the length of Ms. 482 list<InstructionEncoding> Objects = Ts; 483} 484 485//===----------------------------------------------------------------------===// 486// Instruction set description - These classes correspond to the C++ classes in 487// the Target/TargetInstrInfo.h file. 488// 489class Instruction : InstructionEncoding { 490 string Namespace = ""; 491 492 dag OutOperandList; // An dag containing the MI def operand list. 493 dag InOperandList; // An dag containing the MI use operand list. 494 string AsmString = ""; // The .s format to print the instruction with. 495 496 // Allows specifying a canonical InstructionEncoding by HwMode. If non-empty, 497 // the Inst member of this Instruction is ignored. 498 EncodingByHwMode EncodingInfos; 499 500 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 501 // otherwise, uninitialized. 502 list<dag> Pattern; 503 504 // The follow state will eventually be inferred automatically from the 505 // instruction pattern. 506 507 list<Register> Uses = []; // Default to using no non-operand registers 508 list<Register> Defs = []; // Default to modifying no non-operand registers 509 510 // Predicates - List of predicates which will be turned into isel matching 511 // code. 512 list<Predicate> Predicates = []; 513 514 // Size - Size of encoded instruction, or zero if the size cannot be determined 515 // from the opcode. 516 int Size = 0; 517 518 // Code size, for instruction selection. 519 // FIXME: What does this actually mean? 520 int CodeSize = 0; 521 522 // Added complexity passed onto matching pattern. 523 int AddedComplexity = 0; 524 525 // Indicates if this is a pre-isel opcode that should be 526 // legalized/regbankselected/selected. 527 bit isPreISelOpcode = false; 528 529 // These bits capture information about the high-level semantics of the 530 // instruction. 531 bit isReturn = false; // Is this instruction a return instruction? 532 bit isBranch = false; // Is this instruction a branch instruction? 533 bit isEHScopeReturn = false; // Does this instruction end an EH scope? 534 bit isIndirectBranch = false; // Is this instruction an indirect branch? 535 bit isCompare = false; // Is this instruction a comparison instruction? 536 bit isMoveImm = false; // Is this instruction a move immediate instruction? 537 bit isMoveReg = false; // Is this instruction a move register instruction? 538 bit isBitcast = false; // Is this instruction a bitcast instruction? 539 bit isSelect = false; // Is this instruction a select instruction? 540 bit isBarrier = false; // Can control flow fall through this instruction? 541 bit isCall = false; // Is this instruction a call instruction? 542 bit isAdd = false; // Is this instruction an add instruction? 543 bit isTrap = false; // Is this instruction a trap instruction? 544 bit canFoldAsLoad = false; // Can this be folded as a simple memory operand? 545 bit mayLoad = ?; // Is it possible for this inst to read memory? 546 bit mayStore = ?; // Is it possible for this inst to write memory? 547 bit mayRaiseFPException = false; // Can this raise a floating-point exception? 548 bit isConvertibleToThreeAddress = false; // Can this 2-addr instruction promote? 549 bit isCommutable = false; // Is this 3 operand instruction commutable? 550 bit isTerminator = false; // Is this part of the terminator for a basic block? 551 bit isReMaterializable = false; // Is this instruction re-materializable? 552 bit isPredicable = false; // 1 means this instruction is predicable 553 // even if it does not have any operand 554 // tablegen can identify as a predicate 555 bit isUnpredicable = false; // 1 means this instruction is not predicable 556 // even if it _does_ have a predicate operand 557 bit hasDelaySlot = false; // Does this instruction have an delay slot? 558 bit usesCustomInserter = false; // Pseudo instr needing special help. 559 bit hasPostISelHook = false; // To be *adjusted* after isel by target hook. 560 bit hasCtrlDep = false; // Does this instruction r/w ctrl-flow chains? 561 bit isNotDuplicable = false; // Is it unsafe to duplicate this instruction? 562 bit isConvergent = false; // Is this instruction convergent? 563 bit isAuthenticated = false; // Does this instruction authenticate a pointer? 564 bit isAsCheapAsAMove = false; // As cheap (or cheaper) than a move instruction. 565 bit hasExtraSrcRegAllocReq = false; // Sources have special regalloc requirement? 566 bit hasExtraDefRegAllocReq = false; // Defs have special regalloc requirement? 567 bit isRegSequence = false; // Is this instruction a kind of reg sequence? 568 // If so, make sure to override 569 // TargetInstrInfo::getRegSequenceLikeInputs. 570 bit isPseudo = false; // Is this instruction a pseudo-instruction? 571 // If so, won't have encoding information for 572 // the [MC]CodeEmitter stuff. 573 bit isMeta = false; // Is this instruction a meta-instruction? 574 // If so, won't produce any output in the form of 575 // executable instructions 576 bit isExtractSubreg = false; // Is this instruction a kind of extract subreg? 577 // If so, make sure to override 578 // TargetInstrInfo::getExtractSubregLikeInputs. 579 bit isInsertSubreg = false; // Is this instruction a kind of insert subreg? 580 // If so, make sure to override 581 // TargetInstrInfo::getInsertSubregLikeInputs. 582 bit variadicOpsAreDefs = false; // Are variadic operands definitions? 583 584 // Does the instruction have side effects that are not captured by any 585 // operands of the instruction or other flags? 586 bit hasSideEffects = ?; 587 588 // Is this instruction a "real" instruction (with a distinct machine 589 // encoding), or is it a pseudo instruction used for codegen modeling 590 // purposes. 591 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 592 // instructions can (and often do) still have encoding information 593 // associated with them. Once we've migrated all of them over to true 594 // pseudo-instructions that are lowered to real instructions prior to 595 // the printer/emitter, we can remove this attribute and just use isPseudo. 596 // 597 // The intended use is: 598 // isPseudo: Does not have encoding information and should be expanded, 599 // at the latest, during lowering to MCInst. 600 // 601 // isCodeGenOnly: Does have encoding information and can go through to the 602 // CodeEmitter unchanged, but duplicates a canonical instruction 603 // definition's encoding and should be ignored when constructing the 604 // assembler match tables. 605 bit isCodeGenOnly = false; 606 607 // Is this instruction a pseudo instruction for use by the assembler parser. 608 bit isAsmParserOnly = false; 609 610 // This instruction is not expected to be queried for scheduling latencies 611 // and therefore needs no scheduling information even for a complete 612 // scheduling model. 613 bit hasNoSchedulingInfo = false; 614 615 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 616 617 // Scheduling information from TargetSchedule.td. 618 list<SchedReadWrite> SchedRW; 619 620 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 621 622 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 623 /// be encoded into the output machineinstr. 624 string DisableEncoding = ""; 625 626 string PostEncoderMethod = ""; 627 628 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 629 bits<64> TSFlags = 0; 630 631 ///@name Assembler Parser Support 632 ///@{ 633 634 string AsmMatchConverter = ""; 635 636 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 637 /// two-operand matcher inst-alias for a three operand instruction. 638 /// For example, the arm instruction "add r3, r3, r5" can be written 639 /// as "add r3, r5". The constraint is of the same form as a tied-operand 640 /// constraint. For example, "$Rn = $Rd". 641 string TwoOperandAliasConstraint = ""; 642 643 /// Assembler variant name to use for this instruction. If specified then 644 /// instruction will be presented only in MatchTable for this variant. If 645 /// not specified then assembler variants will be determined based on 646 /// AsmString 647 string AsmVariantName = ""; 648 649 ///@} 650 651 /// UseNamedOperandTable - If set, the operand indices of this instruction 652 /// can be queried via the getNamedOperandIdx() function which is generated 653 /// by TableGen. 654 bit UseNamedOperandTable = false; 655 656 /// Should generate helper functions that help you to map a logical operand's 657 /// index to the underlying MIOperand's index. 658 /// In most architectures logical operand indicies are equal to 659 /// MIOperand indicies, but for some CISC architectures, a logical operand 660 /// might be consist of multiple MIOperand (e.g. a logical operand that 661 /// uses complex address mode). 662 bit UseLogicalOperandMappings = false; 663 664 /// Should FastISel ignore this instruction. For certain ISAs, they have 665 /// instructions which map to the same ISD Opcode, value type operands and 666 /// instruction selection predicates. FastISel cannot handle such cases, but 667 /// SelectionDAG can. 668 bit FastISelShouldIgnore = false; 669 670 /// HasPositionOrder: Indicate tablegen to sort the instructions by record 671 /// ID, so that instruction that is defined earlier can be sorted earlier 672 /// in the assembly matching table. 673 bit HasPositionOrder = false; 674} 675 676/// Defines a Pat match between compressed and uncompressed instruction. 677/// The relationship and helper function generation are handled by 678/// CompressInstEmitter backend. 679class CompressPat<dag input, dag output, list<Predicate> predicates = []> { 680 /// Uncompressed instruction description. 681 dag Input = input; 682 /// Compressed instruction description. 683 dag Output = output; 684 /// Predicates that must be true for this to match. 685 list<Predicate> Predicates = predicates; 686 /// Duplicate match when tied operand is just different. 687 bit isCompressOnly = false; 688} 689 690/// Defines an additional encoding that disassembles to the given instruction 691/// Like Instruction, the Inst and SoftFail fields are omitted to allow targets 692// to specify their size. 693class AdditionalEncoding<Instruction I> : InstructionEncoding { 694 Instruction AliasOf = I; 695} 696 697/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 698/// Which instruction it expands to and how the operands map from the 699/// pseudo. 700class PseudoInstExpansion<dag Result> { 701 dag ResultInst = Result; // The instruction to generate. 702 bit isPseudo = true; 703} 704 705/// Predicates - These are extra conditionals which are turned into instruction 706/// selector matching code. Currently each predicate is just a string. 707class Predicate<string cond> { 708 string CondString = cond; 709 710 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 711 /// matcher, this is true. Targets should set this by inheriting their 712 /// feature from the AssemblerPredicate class in addition to Predicate. 713 bit AssemblerMatcherPredicate = false; 714 715 /// AssemblerCondDag - Set of subtarget features being tested used 716 /// as alternative condition string used for assembler matcher. Must be used 717 /// with (all_of) to indicate that all features must be present, or (any_of) 718 /// to indicate that at least one must be. The required lack of presence of 719 /// a feature can be tested using a (not) node including the feature. 720 /// e.g. "(all_of ModeThumb)" is translated to "(Bits & ModeThumb) != 0". 721 /// "(all_of (not ModeThumb))" is translated to 722 /// "(Bits & ModeThumb) == 0". 723 /// "(all_of ModeThumb, FeatureThumb2)" is translated to 724 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 725 /// "(any_of ModeTumb, FeatureThumb2)" is translated to 726 /// "(Bits & ModeThumb) != 0 || (Bits & FeatureThumb2) != 0". 727 /// all_of and any_of cannot be combined in a single dag, instead multiple 728 /// predicates can be placed onto Instruction definitions. 729 dag AssemblerCondDag; 730 731 /// PredicateName - User-level name to use for the predicate. Mainly for use 732 /// in diagnostics such as missing feature errors in the asm matcher. 733 string PredicateName = ""; 734 735 /// Setting this to '1' indicates that the predicate must be recomputed on 736 /// every function change. Most predicates can leave this at '0'. 737 /// 738 /// Ignored by SelectionDAG, it always recomputes the predicate on every use. 739 bit RecomputePerFunction = false; 740} 741 742/// NoHonorSignDependentRounding - This predicate is true if support for 743/// sign-dependent-rounding is not enabled. 744def NoHonorSignDependentRounding 745 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 746 747class Requires<list<Predicate> preds> { 748 list<Predicate> Predicates = preds; 749} 750 751/// ops definition - This is just a simple marker used to identify the operand 752/// list for an instruction. outs and ins are identical both syntactically and 753/// semantically; they are used to define def operands and use operands to 754/// improve readability. This should be used like this: 755/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 756def ops; 757def outs; 758def ins; 759 760/// variable_ops definition - Mark this instruction as taking a variable number 761/// of operands. 762def variable_ops; 763 764/// variable-length instruction encoding utilities. 765/// The `ascend` operator should be used like this: 766/// (ascend 0b0010, 0b1101) 767/// Which represent a seqence of encoding fragments placing from LSB to MSB. 768/// Thus, in this case the final encoding will be 0b1101_0010. 769/// The arguments for `ascend` can either be `bits` or another DAG. 770def ascend; 771/// In addition, we can use `descend` to describe an encoding that places 772/// its arguments (i.e. encoding fragments) from MSB to LSB. For instance: 773/// (descend 0b0010, 0b1101) 774/// This results in an encoding of 0b0010_1101. 775def descend; 776/// The `operand` operator should be used like this: 777/// (operand "$src", 4) 778/// Which represents a 4-bit encoding for an instruction operand named `$src`. 779def operand; 780/// Similar to `operand`, we can reference only part of the operand's encoding: 781/// (slice "$src", 6, 8) 782/// (slice "$src", 8, 6) 783/// Both DAG represent bit 6 to 8 (total of 3 bits) in the encoding of operand 784/// `$src`. 785def slice; 786/// You can use `encoder` to specify a custom encoder function for a specific 787/// `operand` or `encoder` directive. For example: 788/// (operand "$src", 4, (encoder "encodeMyImm")) 789/// (slice "$src", 8, 6, (encoder "encodeMyReg")) 790def encoder; 791 792/// PointerLikeRegClass - Values that are designed to have pointer width are 793/// derived from this. TableGen treats the register class as having a symbolic 794/// type that it doesn't know, and resolves the actual regclass to use by using 795/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 796class PointerLikeRegClass<int Kind> { 797 int RegClassKind = Kind; 798} 799 800 801/// ptr_rc definition - Mark this operand as being a pointer value whose 802/// register class is resolved dynamically via a callback to TargetInstrInfo. 803/// FIXME: We should probably change this to a class which contain a list of 804/// flags. But currently we have but one flag. 805def ptr_rc : PointerLikeRegClass<0>; 806 807/// unknown definition - Mark this operand as being of unknown type, causing 808/// it to be resolved by inference in the context it is used. 809class unknown_class; 810def unknown : unknown_class; 811 812/// AsmOperandClass - Representation for the kinds of operands which the target 813/// specific parser can create and the assembly matcher may need to distinguish. 814/// 815/// Operand classes are used to define the order in which instructions are 816/// matched, to ensure that the instruction which gets matched for any 817/// particular list of operands is deterministic. 818/// 819/// The target specific parser must be able to classify a parsed operand into a 820/// unique class which does not partially overlap with any other classes. It can 821/// match a subset of some other class, in which case the super class field 822/// should be defined. 823class AsmOperandClass { 824 /// The name to use for this class, which should be usable as an enum value. 825 string Name = ?; 826 827 /// The super classes of this operand. 828 list<AsmOperandClass> SuperClasses = []; 829 830 /// The name of the method on the target specific operand to call to test 831 /// whether the operand is an instance of this class. If not set, this will 832 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 833 /// signature should be: 834 /// bool isFoo() const; 835 string PredicateMethod = ?; 836 837 /// The name of the method on the target specific operand to call to add the 838 /// target specific operand to an MCInst. If not set, this will default to 839 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 840 /// signature should be: 841 /// void addFooOperands(MCInst &Inst, unsigned N) const; 842 string RenderMethod = ?; 843 844 /// The name of the method on the target specific operand to call to custom 845 /// handle the operand parsing. This is useful when the operands do not relate 846 /// to immediates or registers and are very instruction specific (as flags to 847 /// set in a processor register, coprocessor number, ...). 848 string ParserMethod = ?; 849 850 // The diagnostic type to present when referencing this operand in a 851 // match failure error message. By default, use a generic "invalid operand" 852 // diagnostic. The target AsmParser maps these codes to text. 853 string DiagnosticType = ""; 854 855 /// A diagnostic message to emit when an invalid value is provided for this 856 /// operand. 857 string DiagnosticString = ""; 858 859 /// Set to 1 if this operand is optional and not always required. Typically, 860 /// the AsmParser will emit an error when it finishes parsing an 861 /// instruction if it hasn't matched all the operands yet. However, this 862 /// error will be suppressed if all of the remaining unmatched operands are 863 /// marked as IsOptional. 864 /// 865 /// Optional arguments must be at the end of the operand list. 866 bit IsOptional = false; 867 868 /// The name of the method on the target specific asm parser that returns the 869 /// default operand for this optional operand. This method is only used if 870 /// IsOptional == 1. If not set, this will default to "defaultFooOperands", 871 /// where Foo is the AsmOperandClass name. The method signature should be: 872 /// std::unique_ptr<MCParsedAsmOperand> defaultFooOperands() const; 873 string DefaultMethod = ?; 874} 875 876def ImmAsmOperand : AsmOperandClass { 877 let Name = "Imm"; 878} 879 880/// Operand Types - These provide the built-in operand types that may be used 881/// by a target. Targets can optionally provide their own operand types as 882/// needed, though this should not be needed for RISC targets. 883class Operand<ValueType ty> : DAGOperand { 884 ValueType Type = ty; 885 string PrintMethod = "printOperand"; 886 string EncoderMethod = ""; 887 bit hasCompleteDecoder = true; 888 string OperandType = "OPERAND_UNKNOWN"; 889 dag MIOperandInfo = (ops); 890 891 // MCOperandPredicate - Optionally, a code fragment operating on 892 // const MCOperand &MCOp, and returning a bool, to indicate if 893 // the value of MCOp is valid for the specific subclass of Operand 894 code MCOperandPredicate; 895 896 // ParserMatchClass - The "match class" that operands of this type fit 897 // in. Match classes are used to define the order in which instructions are 898 // match, to ensure that which instructions gets matched is deterministic. 899 // 900 // The target specific parser must be able to classify an parsed operand into 901 // a unique class, which does not partially overlap with any other classes. It 902 // can match a subset of some other class, in which case the AsmOperandClass 903 // should declare the other operand as one of its super classes. 904 AsmOperandClass ParserMatchClass = ImmAsmOperand; 905} 906 907class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> 908 : DAGOperand { 909 // RegClass - The register class of the operand. 910 RegisterClass RegClass = regclass; 911 // PrintMethod - The target method to call to print register operands of 912 // this type. The method normally will just use an alt-name index to look 913 // up the name to print. Default to the generic printOperand(). 914 string PrintMethod = pm; 915 916 // EncoderMethod - The target method name to call to encode this register 917 // operand. 918 string EncoderMethod = ""; 919 920 // ParserMatchClass - The "match class" that operands of this type fit 921 // in. Match classes are used to define the order in which instructions are 922 // match, to ensure that which instructions gets matched is deterministic. 923 // 924 // The target specific parser must be able to classify an parsed operand into 925 // a unique class, which does not partially overlap with any other classes. It 926 // can match a subset of some other class, in which case the AsmOperandClass 927 // should declare the other operand as one of its super classes. 928 AsmOperandClass ParserMatchClass; 929 930 string OperandType = "OPERAND_REGISTER"; 931 932 // When referenced in the result of a CodeGen pattern, GlobalISel will 933 // normally copy the matched operand to the result. When this is set, it will 934 // emit a special copy that will replace zero-immediates with the specified 935 // zero-register. 936 Register GIZeroRegister = ?; 937} 938 939let OperandType = "OPERAND_IMMEDIATE" in { 940def i1imm : Operand<i1>; 941def i8imm : Operand<i8>; 942def i16imm : Operand<i16>; 943def i32imm : Operand<i32>; 944def i64imm : Operand<i64>; 945 946def f32imm : Operand<f32>; 947def f64imm : Operand<f64>; 948} 949 950// Register operands for generic instructions don't have an MVT, but do have 951// constraints linking the operands (e.g. all operands of a G_ADD must 952// have the same LLT). 953class TypedOperand<string Ty> : Operand<untyped> { 954 let OperandType = Ty; 955 bit IsPointer = false; 956 bit IsImmediate = false; 957} 958 959def type0 : TypedOperand<"OPERAND_GENERIC_0">; 960def type1 : TypedOperand<"OPERAND_GENERIC_1">; 961def type2 : TypedOperand<"OPERAND_GENERIC_2">; 962def type3 : TypedOperand<"OPERAND_GENERIC_3">; 963def type4 : TypedOperand<"OPERAND_GENERIC_4">; 964def type5 : TypedOperand<"OPERAND_GENERIC_5">; 965 966let IsPointer = true in { 967 def ptype0 : TypedOperand<"OPERAND_GENERIC_0">; 968 def ptype1 : TypedOperand<"OPERAND_GENERIC_1">; 969 def ptype2 : TypedOperand<"OPERAND_GENERIC_2">; 970 def ptype3 : TypedOperand<"OPERAND_GENERIC_3">; 971 def ptype4 : TypedOperand<"OPERAND_GENERIC_4">; 972 def ptype5 : TypedOperand<"OPERAND_GENERIC_5">; 973} 974 975// untyped_imm is for operands where isImm() will be true. It currently has no 976// special behaviour and is only used for clarity. 977def untyped_imm_0 : TypedOperand<"OPERAND_GENERIC_IMM_0"> { 978 let IsImmediate = true; 979} 980 981/// zero_reg definition - Special node to stand for the zero register. 982/// 983def zero_reg; 984 985/// undef_tied_input - Special node to indicate an input register tied 986/// to an output which defaults to IMPLICIT_DEF. 987def undef_tied_input; 988 989/// All operands which the MC layer classifies as predicates should inherit from 990/// this class in some manner. This is already handled for the most commonly 991/// used PredicateOperand, but may be useful in other circumstances. 992class PredicateOp; 993 994/// OperandWithDefaultOps - This Operand class can be used as the parent class 995/// for an Operand that needs to be initialized with a default value if 996/// no value is supplied in a pattern. This class can be used to simplify the 997/// pattern definitions for instructions that have target specific flags 998/// encoded as immediate operands. 999class OperandWithDefaultOps<ValueType ty, dag defaultops> 1000 : Operand<ty> { 1001 dag DefaultOps = defaultops; 1002} 1003 1004/// PredicateOperand - This can be used to define a predicate operand for an 1005/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 1006/// AlwaysVal specifies the value of this predicate when set to "always 1007/// execute". 1008class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 1009 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp { 1010 let MIOperandInfo = OpTypes; 1011} 1012 1013/// OptionalDefOperand - This is used to define a optional definition operand 1014/// for an instruction. DefaultOps is the register the operand represents if 1015/// none is supplied, e.g. zero_reg. 1016class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 1017 : OperandWithDefaultOps<ty, defaultops> { 1018 let MIOperandInfo = OpTypes; 1019} 1020 1021 1022// InstrInfo - This class should only be instantiated once to provide parameters 1023// which are global to the target machine. 1024// 1025class InstrInfo { 1026 // Target can specify its instructions in either big or little-endian formats. 1027 // For instance, while both Sparc and PowerPC are big-endian platforms, the 1028 // Sparc manual specifies its instructions in the format [31..0] (big), while 1029 // PowerPC specifies them using the format [0..31] (little). 1030 bit isLittleEndianEncoding = false; 1031 1032 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset 1033 // by default, and TableGen will infer their value from the instruction 1034 // pattern when possible. 1035 // 1036 // Normally, TableGen will issue an error if it can't infer the value of a 1037 // property that hasn't been set explicitly. When guessInstructionProperties 1038 // is set, it will guess a safe value instead. 1039 // 1040 // This option is a temporary migration help. It will go away. 1041 bit guessInstructionProperties = true; 1042 1043 // TableGen's instruction encoder generator has support for matching operands 1044 // to bit-field variables both by name and by position. While matching by 1045 // name is preferred, this is currently not possible for complex operands, 1046 // and some targets still reply on the positional encoding rules. When 1047 // generating a decoder for such targets, the positional encoding rules must 1048 // be used by the decoder generator as well. 1049 // 1050 // This option is temporary; it will go away once the TableGen decoder 1051 // generator has better support for complex operands and targets have 1052 // migrated away from using positionally encoded operands. 1053 bit decodePositionallyEncodedOperands = false; 1054 1055 // When set, this indicates that there will be no overlap between those 1056 // operands that are matched by ordering (positional operands) and those 1057 // matched by name. 1058 // 1059 // This option is temporary; it will go away once the TableGen decoder 1060 // generator has better support for complex operands and targets have 1061 // migrated away from using positionally encoded operands. 1062 bit noNamedPositionallyEncodedOperands = false; 1063} 1064 1065// Standard Pseudo Instructions. 1066// This list must match TargetOpcodes.def. 1067// Only these instructions are allowed in the TargetOpcode namespace. 1068// Ensure mayLoad and mayStore have a default value, so as not to break 1069// targets that set guessInstructionProperties=0. Any local definition of 1070// mayLoad/mayStore takes precedence over these default values. 1071class StandardPseudoInstruction : Instruction { 1072 let mayLoad = false; 1073 let mayStore = false; 1074 let isCodeGenOnly = true; 1075 let isPseudo = true; 1076 let hasNoSchedulingInfo = true; 1077 let Namespace = "TargetOpcode"; 1078} 1079def PHI : StandardPseudoInstruction { 1080 let OutOperandList = (outs unknown:$dst); 1081 let InOperandList = (ins variable_ops); 1082 let AsmString = "PHINODE"; 1083 let hasSideEffects = false; 1084} 1085def INLINEASM : StandardPseudoInstruction { 1086 let OutOperandList = (outs); 1087 let InOperandList = (ins variable_ops); 1088 let AsmString = ""; 1089 let hasSideEffects = false; // Note side effect is encoded in an operand. 1090} 1091def INLINEASM_BR : StandardPseudoInstruction { 1092 let OutOperandList = (outs); 1093 let InOperandList = (ins variable_ops); 1094 let AsmString = ""; 1095 // Unlike INLINEASM, this is always treated as having side-effects. 1096 let hasSideEffects = true; 1097 // Despite potentially branching, this instruction is intentionally _not_ 1098 // marked as a terminator or a branch. 1099} 1100def CFI_INSTRUCTION : StandardPseudoInstruction { 1101 let OutOperandList = (outs); 1102 let InOperandList = (ins i32imm:$id); 1103 let AsmString = ""; 1104 let hasCtrlDep = true; 1105 let hasSideEffects = false; 1106 let isNotDuplicable = true; 1107 let isMeta = true; 1108} 1109def EH_LABEL : StandardPseudoInstruction { 1110 let OutOperandList = (outs); 1111 let InOperandList = (ins i32imm:$id); 1112 let AsmString = ""; 1113 let hasCtrlDep = true; 1114 let hasSideEffects = false; 1115 let isNotDuplicable = true; 1116 let isMeta = true; 1117} 1118def GC_LABEL : StandardPseudoInstruction { 1119 let OutOperandList = (outs); 1120 let InOperandList = (ins i32imm:$id); 1121 let AsmString = ""; 1122 let hasCtrlDep = true; 1123 let hasSideEffects = false; 1124 let isNotDuplicable = true; 1125 let isMeta = true; 1126} 1127def ANNOTATION_LABEL : StandardPseudoInstruction { 1128 let OutOperandList = (outs); 1129 let InOperandList = (ins i32imm:$id); 1130 let AsmString = ""; 1131 let hasCtrlDep = true; 1132 let hasSideEffects = false; 1133 let isNotDuplicable = true; 1134} 1135def KILL : StandardPseudoInstruction { 1136 let OutOperandList = (outs); 1137 let InOperandList = (ins variable_ops); 1138 let AsmString = ""; 1139 let hasSideEffects = false; 1140 let isMeta = true; 1141} 1142def EXTRACT_SUBREG : StandardPseudoInstruction { 1143 let OutOperandList = (outs unknown:$dst); 1144 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 1145 let AsmString = ""; 1146 let hasSideEffects = false; 1147} 1148def INSERT_SUBREG : StandardPseudoInstruction { 1149 let OutOperandList = (outs unknown:$dst); 1150 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 1151 let AsmString = ""; 1152 let hasSideEffects = false; 1153 let Constraints = "$supersrc = $dst"; 1154} 1155def IMPLICIT_DEF : StandardPseudoInstruction { 1156 let OutOperandList = (outs unknown:$dst); 1157 let InOperandList = (ins); 1158 let AsmString = ""; 1159 let hasSideEffects = false; 1160 let isReMaterializable = true; 1161 let isAsCheapAsAMove = true; 1162 let isMeta = true; 1163} 1164def SUBREG_TO_REG : StandardPseudoInstruction { 1165 let OutOperandList = (outs unknown:$dst); 1166 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 1167 let AsmString = ""; 1168 let hasSideEffects = false; 1169} 1170def COPY_TO_REGCLASS : StandardPseudoInstruction { 1171 let OutOperandList = (outs unknown:$dst); 1172 let InOperandList = (ins unknown:$src, i32imm:$regclass); 1173 let AsmString = ""; 1174 let hasSideEffects = false; 1175 let isAsCheapAsAMove = true; 1176} 1177def DBG_VALUE : StandardPseudoInstruction { 1178 let OutOperandList = (outs); 1179 let InOperandList = (ins variable_ops); 1180 let AsmString = "DBG_VALUE"; 1181 let hasSideEffects = false; 1182 let isMeta = true; 1183} 1184def DBG_VALUE_LIST : StandardPseudoInstruction { 1185 let OutOperandList = (outs); 1186 let InOperandList = (ins variable_ops); 1187 let AsmString = "DBG_VALUE_LIST"; 1188 let hasSideEffects = 0; 1189 let isMeta = true; 1190} 1191def DBG_INSTR_REF : StandardPseudoInstruction { 1192 let OutOperandList = (outs); 1193 let InOperandList = (ins variable_ops); 1194 let AsmString = "DBG_INSTR_REF"; 1195 let hasSideEffects = false; 1196 let isMeta = true; 1197} 1198def DBG_PHI : StandardPseudoInstruction { 1199 let OutOperandList = (outs); 1200 let InOperandList = (ins variable_ops); 1201 let AsmString = "DBG_PHI"; 1202 let hasSideEffects = 0; 1203 let isMeta = true; 1204} 1205def DBG_LABEL : StandardPseudoInstruction { 1206 let OutOperandList = (outs); 1207 let InOperandList = (ins unknown:$label); 1208 let AsmString = "DBG_LABEL"; 1209 let hasSideEffects = false; 1210 let isMeta = true; 1211} 1212def REG_SEQUENCE : StandardPseudoInstruction { 1213 let OutOperandList = (outs unknown:$dst); 1214 let InOperandList = (ins unknown:$supersrc, variable_ops); 1215 let AsmString = ""; 1216 let hasSideEffects = false; 1217 let isAsCheapAsAMove = true; 1218} 1219def COPY : StandardPseudoInstruction { 1220 let OutOperandList = (outs unknown:$dst); 1221 let InOperandList = (ins unknown:$src); 1222 let AsmString = ""; 1223 let hasSideEffects = false; 1224 let isAsCheapAsAMove = true; 1225 let hasNoSchedulingInfo = false; 1226} 1227def BUNDLE : StandardPseudoInstruction { 1228 let OutOperandList = (outs); 1229 let InOperandList = (ins variable_ops); 1230 let AsmString = "BUNDLE"; 1231 let hasSideEffects = false; 1232} 1233def LIFETIME_START : StandardPseudoInstruction { 1234 let OutOperandList = (outs); 1235 let InOperandList = (ins i32imm:$id); 1236 let AsmString = "LIFETIME_START"; 1237 let hasSideEffects = false; 1238 let isMeta = true; 1239} 1240def LIFETIME_END : StandardPseudoInstruction { 1241 let OutOperandList = (outs); 1242 let InOperandList = (ins i32imm:$id); 1243 let AsmString = "LIFETIME_END"; 1244 let hasSideEffects = false; 1245 let isMeta = true; 1246} 1247def PSEUDO_PROBE : StandardPseudoInstruction { 1248 let OutOperandList = (outs); 1249 let InOperandList = (ins i64imm:$guid, i64imm:$index, i8imm:$type, i32imm:$attr); 1250 let AsmString = "PSEUDO_PROBE"; 1251 let hasSideEffects = 1; 1252 let isMeta = true; 1253} 1254def ARITH_FENCE : StandardPseudoInstruction { 1255 let OutOperandList = (outs unknown:$dst); 1256 let InOperandList = (ins unknown:$src); 1257 let AsmString = ""; 1258 let hasSideEffects = false; 1259 let Constraints = "$src = $dst"; 1260 let isMeta = true; 1261} 1262 1263def STACKMAP : StandardPseudoInstruction { 1264 let OutOperandList = (outs); 1265 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops); 1266 let hasSideEffects = true; 1267 let isCall = true; 1268 let mayLoad = true; 1269 let usesCustomInserter = true; 1270} 1271def PATCHPOINT : StandardPseudoInstruction { 1272 let OutOperandList = (outs unknown:$dst); 1273 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee, 1274 i32imm:$nargs, i32imm:$cc, variable_ops); 1275 let hasSideEffects = true; 1276 let isCall = true; 1277 let mayLoad = true; 1278 let usesCustomInserter = true; 1279} 1280def STATEPOINT : StandardPseudoInstruction { 1281 let OutOperandList = (outs variable_ops); 1282 let InOperandList = (ins variable_ops); 1283 let usesCustomInserter = true; 1284 let mayLoad = true; 1285 let mayStore = true; 1286 let hasSideEffects = true; 1287 let isCall = true; 1288} 1289def LOAD_STACK_GUARD : StandardPseudoInstruction { 1290 let OutOperandList = (outs ptr_rc:$dst); 1291 let InOperandList = (ins); 1292 let mayLoad = true; 1293 bit isReMaterializable = true; 1294 let hasSideEffects = false; 1295 bit isPseudo = true; 1296} 1297def PREALLOCATED_SETUP : StandardPseudoInstruction { 1298 let OutOperandList = (outs); 1299 let InOperandList = (ins i32imm:$a); 1300 let usesCustomInserter = true; 1301 let hasSideEffects = true; 1302} 1303def PREALLOCATED_ARG : StandardPseudoInstruction { 1304 let OutOperandList = (outs ptr_rc:$loc); 1305 let InOperandList = (ins i32imm:$a, i32imm:$b); 1306 let usesCustomInserter = true; 1307 let hasSideEffects = true; 1308} 1309def LOCAL_ESCAPE : StandardPseudoInstruction { 1310 // This instruction is really just a label. It has to be part of the chain so 1311 // that it doesn't get dropped from the DAG, but it produces nothing and has 1312 // no side effects. 1313 let OutOperandList = (outs); 1314 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id); 1315 let hasSideEffects = false; 1316 let hasCtrlDep = true; 1317} 1318def FAULTING_OP : StandardPseudoInstruction { 1319 let OutOperandList = (outs unknown:$dst); 1320 let InOperandList = (ins variable_ops); 1321 let usesCustomInserter = true; 1322 let hasSideEffects = true; 1323 let mayLoad = true; 1324 let mayStore = true; 1325 let isTerminator = true; 1326 let isBranch = true; 1327} 1328def PATCHABLE_OP : StandardPseudoInstruction { 1329 let OutOperandList = (outs); 1330 let InOperandList = (ins variable_ops); 1331 let usesCustomInserter = true; 1332 let mayLoad = true; 1333 let mayStore = true; 1334 let hasSideEffects = true; 1335} 1336def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction { 1337 let OutOperandList = (outs); 1338 let InOperandList = (ins); 1339 let AsmString = "# XRay Function Enter."; 1340 let usesCustomInserter = true; 1341 let hasSideEffects = true; 1342} 1343def PATCHABLE_RET : StandardPseudoInstruction { 1344 let OutOperandList = (outs); 1345 let InOperandList = (ins variable_ops); 1346 let AsmString = "# XRay Function Patchable RET."; 1347 let usesCustomInserter = true; 1348 let hasSideEffects = true; 1349 let isTerminator = true; 1350 let isReturn = true; 1351} 1352def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction { 1353 let OutOperandList = (outs); 1354 let InOperandList = (ins); 1355 let AsmString = "# XRay Function Exit."; 1356 let usesCustomInserter = true; 1357 let hasSideEffects = true; 1358 let isReturn = false; // Original return instruction will follow 1359} 1360def PATCHABLE_TAIL_CALL : StandardPseudoInstruction { 1361 let OutOperandList = (outs); 1362 let InOperandList = (ins variable_ops); 1363 let AsmString = "# XRay Tail Call Exit."; 1364 let usesCustomInserter = true; 1365 let hasSideEffects = true; 1366 let isReturn = true; 1367} 1368def PATCHABLE_EVENT_CALL : StandardPseudoInstruction { 1369 let OutOperandList = (outs); 1370 let InOperandList = (ins ptr_rc:$event, unknown:$size); 1371 let AsmString = "# XRay Custom Event Log."; 1372 let usesCustomInserter = true; 1373 let isCall = true; 1374 let mayLoad = true; 1375 let mayStore = true; 1376 let hasSideEffects = true; 1377} 1378def PATCHABLE_TYPED_EVENT_CALL : StandardPseudoInstruction { 1379 let OutOperandList = (outs); 1380 let InOperandList = (ins unknown:$type, ptr_rc:$event, unknown:$size); 1381 let AsmString = "# XRay Typed Event Log."; 1382 let usesCustomInserter = true; 1383 let isCall = true; 1384 let mayLoad = true; 1385 let mayStore = true; 1386 let hasSideEffects = true; 1387} 1388def FENTRY_CALL : StandardPseudoInstruction { 1389 let OutOperandList = (outs); 1390 let InOperandList = (ins); 1391 let AsmString = "# FEntry call"; 1392 let usesCustomInserter = true; 1393 let isCall = true; 1394 let mayLoad = true; 1395 let mayStore = true; 1396 let hasSideEffects = true; 1397} 1398def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction { 1399 let OutOperandList = (outs); 1400 let InOperandList = (ins variable_ops); 1401 let AsmString = ""; 1402 let hasSideEffects = true; 1403} 1404 1405// Generic opcodes used in GlobalISel. 1406include "llvm/Target/GenericOpcodes.td" 1407 1408//===----------------------------------------------------------------------===// 1409// AsmParser - This class can be implemented by targets that wish to implement 1410// .s file parsing. 1411// 1412// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 1413// syntax on X86 for example). 1414// 1415class AsmParser { 1416 // AsmParserClassName - This specifies the suffix to use for the asmparser 1417 // class. Generated AsmParser classes are always prefixed with the target 1418 // name. 1419 string AsmParserClassName = "AsmParser"; 1420 1421 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 1422 // function of the AsmParser class to call on every matched instruction. 1423 // This can be used to perform target specific instruction post-processing. 1424 string AsmParserInstCleanup = ""; 1425 1426 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand 1427 // written register name matcher 1428 bit ShouldEmitMatchRegisterName = true; 1429 1430 // Set to true if the target needs a generated 'alternative register name' 1431 // matcher. 1432 // 1433 // This generates a function which can be used to lookup registers from 1434 // their aliases. This function will fail when called on targets where 1435 // several registers share the same alias (i.e. not a 1:1 mapping). 1436 bit ShouldEmitMatchRegisterAltName = false; 1437 1438 // Set to true if MatchRegisterName and MatchRegisterAltName functions 1439 // should be generated even if there are duplicate register names. The 1440 // target is responsible for coercing aliased registers as necessary 1441 // (e.g. in validateTargetOperandClass), and there are no guarantees about 1442 // which numeric register identifier will be returned in the case of 1443 // multiple matches. 1444 bit AllowDuplicateRegisterNames = false; 1445 1446 // HasMnemonicFirst - Set to false if target instructions don't always 1447 // start with a mnemonic as the first token. 1448 bit HasMnemonicFirst = true; 1449 1450 // ReportMultipleNearMisses - 1451 // When 0, the assembly matcher reports an error for one encoding or operand 1452 // that did not match the parsed instruction. 1453 // When 1, the assembly matcher returns a list of encodings that were close 1454 // to matching the parsed instruction, so to allow more detailed error 1455 // messages. 1456 bit ReportMultipleNearMisses = false; 1457} 1458def DefaultAsmParser : AsmParser; 1459 1460//===----------------------------------------------------------------------===// 1461// AsmParserVariant - Subtargets can have multiple different assembly parsers 1462// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 1463// implemented by targets to describe such variants. 1464// 1465class AsmParserVariant { 1466 // Variant - AsmParsers can be of multiple different variants. Variants are 1467 // used to support targets that need to parse multiple formats for the 1468 // assembly language. 1469 int Variant = 0; 1470 1471 // Name - The AsmParser variant name (e.g., AT&T vs Intel). 1472 string Name = ""; 1473 1474 // CommentDelimiter - If given, the delimiter string used to recognize 1475 // comments which are hard coded in the .td assembler strings for individual 1476 // instructions. 1477 string CommentDelimiter = ""; 1478 1479 // RegisterPrefix - If given, the token prefix which indicates a register 1480 // token. This is used by the matcher to automatically recognize hard coded 1481 // register tokens as constrained registers, instead of tokens, for the 1482 // purposes of matching. 1483 string RegisterPrefix = ""; 1484 1485 // TokenizingCharacters - Characters that are standalone tokens 1486 string TokenizingCharacters = "[]*!"; 1487 1488 // SeparatorCharacters - Characters that are not tokens 1489 string SeparatorCharacters = " \t,"; 1490 1491 // BreakCharacters - Characters that start new identifiers 1492 string BreakCharacters = ""; 1493} 1494def DefaultAsmParserVariant : AsmParserVariant; 1495 1496// Operators for combining SubtargetFeatures in AssemblerPredicates 1497def any_of; 1498def all_of; 1499 1500/// AssemblerPredicate - This is a Predicate that can be used when the assembler 1501/// matches instructions and aliases. 1502class AssemblerPredicate<dag cond, string name = ""> { 1503 bit AssemblerMatcherPredicate = true; 1504 dag AssemblerCondDag = cond; 1505 string PredicateName = name; 1506} 1507 1508/// TokenAlias - This class allows targets to define assembler token 1509/// operand aliases. That is, a token literal operand which is equivalent 1510/// to another, canonical, token literal. For example, ARM allows: 1511/// vmov.u32 s4, #0 -> vmov.i32, #0 1512/// 'u32' is a more specific designator for the 32-bit integer type specifier 1513/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 1514/// def : TokenAlias<".u32", ".i32">; 1515/// 1516/// This works by marking the match class of 'From' as a subclass of the 1517/// match class of 'To'. 1518class TokenAlias<string From, string To> { 1519 string FromToken = From; 1520 string ToToken = To; 1521} 1522 1523/// MnemonicAlias - This class allows targets to define assembler mnemonic 1524/// aliases. This should be used when all forms of one mnemonic are accepted 1525/// with a different mnemonic. For example, X86 allows: 1526/// sal %al, 1 -> shl %al, 1 1527/// sal %ax, %cl -> shl %ax, %cl 1528/// sal %eax, %cl -> shl %eax, %cl 1529/// etc. Though "sal" is accepted with many forms, all of them are directly 1530/// translated to a shl, so it can be handled with (in the case of X86, it 1531/// actually has one for each suffix as well): 1532/// def : MnemonicAlias<"sal", "shl">; 1533/// 1534/// Mnemonic aliases are mapped before any other translation in the match phase, 1535/// and do allow Requires predicates, e.g.: 1536/// 1537/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 1538/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 1539/// 1540/// Mnemonic aliases can also be constrained to specific variants, e.g.: 1541/// 1542/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 1543/// 1544/// If no variant (e.g., "att" or "intel") is specified then the alias is 1545/// applied unconditionally. 1546class MnemonicAlias<string From, string To, string VariantName = ""> { 1547 string FromMnemonic = From; 1548 string ToMnemonic = To; 1549 string AsmVariantName = VariantName; 1550 1551 // Predicates - Predicates that must be true for this remapping to happen. 1552 list<Predicate> Predicates = []; 1553} 1554 1555/// InstAlias - This defines an alternate assembly syntax that is allowed to 1556/// match an instruction that has a different (more canonical) assembly 1557/// representation. 1558class InstAlias<string Asm, dag Result, int Emit = 1, string VariantName = ""> { 1559 string AsmString = Asm; // The .s format to match the instruction with. 1560 dag ResultInst = Result; // The MCInst to generate. 1561 1562 // This determines which order the InstPrinter detects aliases for 1563 // printing. A larger value makes the alias more likely to be 1564 // emitted. The Instruction's own definition is notionally 0.5, so 0 1565 // disables printing and 1 enables it if there are no conflicting aliases. 1566 int EmitPriority = Emit; 1567 1568 // Predicates - Predicates that must be true for this to match. 1569 list<Predicate> Predicates = []; 1570 1571 // If the instruction specified in Result has defined an AsmMatchConverter 1572 // then setting this to 1 will cause the alias to use the AsmMatchConverter 1573 // function when converting the OperandVector into an MCInst instead of the 1574 // function that is generated by the dag Result. 1575 // Setting this to 0 will cause the alias to ignore the Result instruction's 1576 // defined AsmMatchConverter and instead use the function generated by the 1577 // dag Result. 1578 bit UseInstAsmMatchConverter = true; 1579 1580 // Assembler variant name to use for this alias. If not specified then 1581 // assembler variants will be determined based on AsmString 1582 string AsmVariantName = VariantName; 1583} 1584 1585//===----------------------------------------------------------------------===// 1586// AsmWriter - This class can be implemented by targets that need to customize 1587// the format of the .s file writer. 1588// 1589// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 1590// on X86 for example). 1591// 1592class AsmWriter { 1593 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 1594 // class. Generated AsmWriter classes are always prefixed with the target 1595 // name. 1596 string AsmWriterClassName = "InstPrinter"; 1597 1598 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to 1599 // the various print methods. 1600 // FIXME: Remove after all ports are updated. 1601 int PassSubtarget = 0; 1602 1603 // Variant - AsmWriters can be of multiple different variants. Variants are 1604 // used to support targets that need to emit assembly code in ways that are 1605 // mostly the same for different targets, but have minor differences in 1606 // syntax. If the asmstring contains {|} characters in them, this integer 1607 // will specify which alternative to use. For example "{x|y|z}" with Variant 1608 // == 1, will expand to "y". 1609 int Variant = 0; 1610} 1611def DefaultAsmWriter : AsmWriter; 1612 1613 1614//===----------------------------------------------------------------------===// 1615// Target - This class contains the "global" target information 1616// 1617class Target { 1618 // InstructionSet - Instruction set description for this target. 1619 InstrInfo InstructionSet; 1620 1621 // AssemblyParsers - The AsmParser instances available for this target. 1622 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 1623 1624 /// AssemblyParserVariants - The AsmParserVariant instances available for 1625 /// this target. 1626 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 1627 1628 // AssemblyWriters - The AsmWriter instances available for this target. 1629 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 1630 1631 // AllowRegisterRenaming - Controls whether this target allows 1632 // post-register-allocation renaming of registers. This is done by 1633 // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1 1634 // for all opcodes if this flag is set to 0. 1635 int AllowRegisterRenaming = 0; 1636} 1637 1638//===----------------------------------------------------------------------===// 1639// SubtargetFeature - A characteristic of the chip set. 1640// 1641class SubtargetFeature<string n, string a, string v, string d, 1642 list<SubtargetFeature> i = []> { 1643 // Name - Feature name. Used by command line (-mattr=) to determine the 1644 // appropriate target chip. 1645 // 1646 string Name = n; 1647 1648 // Attribute - Attribute to be set by feature. 1649 // 1650 string Attribute = a; 1651 1652 // Value - Value the attribute to be set to by feature. 1653 // 1654 string Value = v; 1655 1656 // Desc - Feature description. Used by command line (-mattr=) to display help 1657 // information. 1658 // 1659 string Desc = d; 1660 1661 // Implies - Features that this feature implies are present. If one of those 1662 // features isn't set, then this one shouldn't be set either. 1663 // 1664 list<SubtargetFeature> Implies = i; 1665} 1666 1667/// Specifies a Subtarget feature that this instruction is deprecated on. 1668class Deprecated<SubtargetFeature dep> { 1669 SubtargetFeature DeprecatedFeatureMask = dep; 1670} 1671 1672/// A custom predicate used to determine if an instruction is 1673/// deprecated or not. 1674class ComplexDeprecationPredicate<string dep> { 1675 string ComplexDeprecationPredicate = dep; 1676} 1677 1678//===----------------------------------------------------------------------===// 1679// Processor chip sets - These values represent each of the chip sets supported 1680// by the scheduler. Each Processor definition requires corresponding 1681// instruction itineraries. 1682// 1683class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f, 1684 list<SubtargetFeature> tunef = []> { 1685 // Name - Chip set name. Used by command line (-mcpu=) to determine the 1686 // appropriate target chip. 1687 // 1688 string Name = n; 1689 1690 // SchedModel - The machine model for scheduling and instruction cost. 1691 // 1692 SchedMachineModel SchedModel = NoSchedModel; 1693 1694 // ProcItin - The scheduling information for the target processor. 1695 // 1696 ProcessorItineraries ProcItin = pi; 1697 1698 // Features - list of 1699 list<SubtargetFeature> Features = f; 1700 1701 // TuneFeatures - list of features for tuning for this CPU. If the target 1702 // supports -mtune, this should contain the list of features used to make 1703 // microarchitectural optimization decisions for a given processor. While 1704 // Features should contain the architectural features for the processor. 1705 list<SubtargetFeature> TuneFeatures = tunef; 1706} 1707 1708// ProcessorModel allows subtargets to specify the more general 1709// SchedMachineModel instead if a ProcessorItinerary. Subtargets will 1710// gradually move to this newer form. 1711// 1712// Although this class always passes NoItineraries to the Processor 1713// class, the SchedMachineModel may still define valid Itineraries. 1714class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f, 1715 list<SubtargetFeature> tunef = []> 1716 : Processor<n, NoItineraries, f, tunef> { 1717 let SchedModel = m; 1718} 1719 1720//===----------------------------------------------------------------------===// 1721// InstrMapping - This class is used to create mapping tables to relate 1722// instructions with each other based on the values specified in RowFields, 1723// ColFields, KeyCol and ValueCols. 1724// 1725class InstrMapping { 1726 // FilterClass - Used to limit search space only to the instructions that 1727 // define the relationship modeled by this InstrMapping record. 1728 string FilterClass; 1729 1730 // RowFields - List of fields/attributes that should be same for all the 1731 // instructions in a row of the relation table. Think of this as a set of 1732 // properties shared by all the instructions related by this relationship 1733 // model and is used to categorize instructions into subgroups. For instance, 1734 // if we want to define a relation that maps 'Add' instruction to its 1735 // predicated forms, we can define RowFields like this: 1736 // 1737 // let RowFields = BaseOp 1738 // All add instruction predicated/non-predicated will have to set their BaseOp 1739 // to the same value. 1740 // 1741 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } 1742 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } 1743 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' } 1744 list<string> RowFields = []; 1745 1746 // List of fields/attributes that are same for all the instructions 1747 // in a column of the relation table. 1748 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged 1749 // based on the 'predSense' values. All the instruction in a specific 1750 // column have the same value and it is fixed for the column according 1751 // to the values set in 'ValueCols'. 1752 list<string> ColFields = []; 1753 1754 // Values for the fields/attributes listed in 'ColFields'. 1755 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction 1756 // that models this relation) should be non-predicated. 1757 // In the example above, 'Add' is the key instruction. 1758 list<string> KeyCol = []; 1759 1760 // List of values for the fields/attributes listed in 'ColFields', one for 1761 // each column in the relation table. 1762 // 1763 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the 1764 // table. First column requires all the instructions to have predSense 1765 // set to 'true' and second column requires it to be 'false'. 1766 list<list<string> > ValueCols = []; 1767} 1768 1769//===----------------------------------------------------------------------===// 1770// Pull in the common support for calling conventions. 1771// 1772include "llvm/Target/TargetCallingConv.td" 1773 1774//===----------------------------------------------------------------------===// 1775// Pull in the common support for DAG isel generation. 1776// 1777include "llvm/Target/TargetSelectionDAG.td" 1778 1779//===----------------------------------------------------------------------===// 1780// Pull in the common support for Global ISel register bank info generation. 1781// 1782include "llvm/Target/GlobalISel/RegisterBank.td" 1783 1784//===----------------------------------------------------------------------===// 1785// Pull in the common support for DAG isel generation. 1786// 1787include "llvm/Target/GlobalISel/Target.td" 1788 1789//===----------------------------------------------------------------------===// 1790// Pull in the common support for the Global ISel DAG-based selector generation. 1791// 1792include "llvm/Target/GlobalISel/SelectionDAGCompat.td" 1793 1794//===----------------------------------------------------------------------===// 1795// Pull in the common support for Pfm Counters generation. 1796// 1797include "llvm/Target/TargetPfmCounters.td" 1798