1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target-independent interfaces which should be 10// implemented by each target which is using a TableGen based code generator. 11// 12//===----------------------------------------------------------------------===// 13 14// Include all information about LLVM intrinsics. 15include "llvm/IR/Intrinsics.td" 16 17//===----------------------------------------------------------------------===// 18// Register file description - These classes are used to fill in the target 19// description classes. 20 21class RegisterClass; // Forward def 22 23class HwMode<string FS> { 24 // A string representing subtarget features that turn on this HW mode. 25 // For example, "+feat1,-feat2" will indicate that the mode is active 26 // when "feat1" is enabled and "feat2" is disabled at the same time. 27 // Any other features are not checked. 28 // When multiple modes are used, they should be mutually exclusive, 29 // otherwise the results are unpredictable. 30 string Features = FS; 31} 32 33// A special mode recognized by tablegen. This mode is considered active 34// when no other mode is active. For targets that do not use specific hw 35// modes, this is the only mode. 36def DefaultMode : HwMode<"">; 37 38// A class used to associate objects with HW modes. It is only intended to 39// be used as a base class, where the derived class should contain a member 40// "Objects", which is a list of the same length as the list of modes. 41// The n-th element on the Objects list will be associated with the n-th 42// element on the Modes list. 43class HwModeSelect<list<HwMode> Ms> { 44 list<HwMode> Modes = Ms; 45} 46 47// A common class that implements a counterpart of ValueType, which is 48// dependent on a HW mode. This class inherits from ValueType itself, 49// which makes it possible to use objects of this class where ValueType 50// objects could be used. This is specifically applicable to selection 51// patterns. 52class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts> 53 : HwModeSelect<Ms>, ValueType<0, 0> { 54 // The length of this list must be the same as the length of Ms. 55 list<ValueType> Objects = Ts; 56} 57 58// A class representing the register size, spill size and spill alignment 59// in bits of a register. 60class RegInfo<int RS, int SS, int SA> { 61 int RegSize = RS; // Register size in bits. 62 int SpillSize = SS; // Spill slot size in bits. 63 int SpillAlignment = SA; // Spill slot alignment in bits. 64} 65 66// The register size/alignment information, parameterized by a HW mode. 67class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []> 68 : HwModeSelect<Ms> { 69 // The length of this list must be the same as the length of Ms. 70 list<RegInfo> Objects = Ts; 71} 72 73// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 74class SubRegIndex<int size, int offset = 0> { 75 string Namespace = ""; 76 77 // Size - Size (in bits) of the sub-registers represented by this index. 78 int Size = size; 79 80 // Offset - Offset of the first bit that is part of this sub-register index. 81 // Set it to -1 if the same index is used to represent sub-registers that can 82 // be at different offsets (for example when using an index to access an 83 // element in a register tuple). 84 int Offset = offset; 85 86 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 87 // This indicates that this SubRegIndex is the result of composing A and B. 88 // See ComposedSubRegIndex. 89 list<SubRegIndex> ComposedOf = []; 90 91 // CoveringSubRegIndices - A list of two or more sub-register indexes that 92 // cover this sub-register. 93 // 94 // This field should normally be left blank as TableGen can infer it. 95 // 96 // TableGen automatically detects sub-registers that straddle the registers 97 // in the SubRegs field of a Register definition. For example: 98 // 99 // Q0 = dsub_0 -> D0, dsub_1 -> D1 100 // Q1 = dsub_0 -> D2, dsub_1 -> D3 101 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 102 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 103 // 104 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given 105 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 106 // CoveringSubRegIndices = [dsub_1, dsub_2]. 107 list<SubRegIndex> CoveringSubRegIndices = []; 108} 109 110// ComposedSubRegIndex - A sub-register that is the result of composing A and B. 111// Offset is set to the sum of A and B's Offsets. Size is set to B's Size. 112class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> 113 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1, 114 !if(!eq(B.Offset, -1), -1, 115 !add(A.Offset, B.Offset)))> { 116 // See SubRegIndex. 117 let ComposedOf = [A, B]; 118} 119 120// RegAltNameIndex - The alternate name set to use for register operands of 121// this register class when printing. 122class RegAltNameIndex { 123 string Namespace = ""; 124 125 // A set to be used if the name for a register is not defined in this set. 126 // This allows creating name sets with only a few alternative names. 127 RegAltNameIndex FallbackRegAltNameIndex = ?; 128} 129def NoRegAltName : RegAltNameIndex; 130 131// Register - You should define one instance of this class for each register 132// in the target machine. String n will become the "name" of the register. 133class Register<string n, list<string> altNames = []> { 134 string Namespace = ""; 135 string AsmName = n; 136 list<string> AltNames = altNames; 137 138 // Aliases - A list of registers that this register overlaps with. A read or 139 // modification of this register can potentially read or modify the aliased 140 // registers. 141 list<Register> Aliases = []; 142 143 // SubRegs - A list of registers that are parts of this register. Note these 144 // are "immediate" sub-registers and the registers within the list do not 145 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 146 // not [AX, AH, AL]. 147 list<Register> SubRegs = []; 148 149 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 150 // to address it. Sub-sub-register indices are automatically inherited from 151 // SubRegs. 152 list<SubRegIndex> SubRegIndices = []; 153 154 // RegAltNameIndices - The alternate name indices which are valid for this 155 // register. 156 list<RegAltNameIndex> RegAltNameIndices = []; 157 158 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 159 // These values can be determined by locating the <target>.h file in the 160 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 161 // order of these names correspond to the enumeration used by gcc. A value of 162 // -1 indicates that the gcc number is undefined and -2 that register number 163 // is invalid for this mode/flavour. 164 list<int> DwarfNumbers = []; 165 166 // CostPerUse - Additional cost of instructions using this register compared 167 // to other registers in its class. The register allocator will try to 168 // minimize the number of instructions using a register with a CostPerUse. 169 // This is used by the x86-64 and ARM Thumb targets where some registers 170 // require larger instruction encodings. 171 int CostPerUse = 0; 172 173 // CoveredBySubRegs - When this bit is set, the value of this register is 174 // completely determined by the value of its sub-registers. For example, the 175 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 176 // covered by its sub-register AX. 177 bit CoveredBySubRegs = 0; 178 179 // HWEncoding - The target specific hardware encoding for this register. 180 bits<16> HWEncoding = 0; 181 182 bit isArtificial = 0; 183} 184 185// RegisterWithSubRegs - This can be used to define instances of Register which 186// need to specify sub-registers. 187// List "subregs" specifies which registers are sub-registers to this one. This 188// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 189// This allows the code generator to be careful not to put two values with 190// overlapping live ranges into registers which alias. 191class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 192 let SubRegs = subregs; 193} 194 195// DAGOperand - An empty base class that unifies RegisterClass's and other forms 196// of Operand's that are legal as type qualifiers in DAG patterns. This should 197// only ever be used for defining multiclasses that are polymorphic over both 198// RegisterClass's and other Operand's. 199class DAGOperand { 200 string OperandNamespace = "MCOI"; 201 string DecoderMethod = ""; 202} 203 204// RegisterClass - Now that all of the registers are defined, and aliases 205// between registers are defined, specify which registers belong to which 206// register classes. This also defines the default allocation order of 207// registers by register allocators. 208// 209class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 210 dag regList, RegAltNameIndex idx = NoRegAltName> 211 : DAGOperand { 212 string Namespace = namespace; 213 214 // The register size/alignment information, parameterized by a HW mode. 215 RegInfoByHwMode RegInfos; 216 217 // RegType - Specify the list ValueType of the registers in this register 218 // class. Note that all registers in a register class must have the same 219 // ValueTypes. This is a list because some targets permit storing different 220 // types in same register, for example vector values with 128-bit total size, 221 // but different count/size of items, like SSE on x86. 222 // 223 list<ValueType> RegTypes = regTypes; 224 225 // Size - Specify the spill size in bits of the registers. A default value of 226 // zero lets tablgen pick an appropriate size. 227 int Size = 0; 228 229 // Alignment - Specify the alignment required of the registers when they are 230 // stored or loaded to memory. 231 // 232 int Alignment = alignment; 233 234 // CopyCost - This value is used to specify the cost of copying a value 235 // between two registers in this register class. The default value is one 236 // meaning it takes a single instruction to perform the copying. A negative 237 // value means copying is extremely expensive or impossible. 238 int CopyCost = 1; 239 240 // MemberList - Specify which registers are in this class. If the 241 // allocation_order_* method are not specified, this also defines the order of 242 // allocation used by the register allocator. 243 // 244 dag MemberList = regList; 245 246 // AltNameIndex - The alternate register name to use when printing operands 247 // of this register class. Every register in the register class must have 248 // a valid alternate name for the given index. 249 RegAltNameIndex altNameIndex = idx; 250 251 // isAllocatable - Specify that the register class can be used for virtual 252 // registers and register allocation. Some register classes are only used to 253 // model instruction operand constraints, and should have isAllocatable = 0. 254 bit isAllocatable = 1; 255 256 // AltOrders - List of alternative allocation orders. The default order is 257 // MemberList itself, and that is good enough for most targets since the 258 // register allocators automatically remove reserved registers and move 259 // callee-saved registers to the end. 260 list<dag> AltOrders = []; 261 262 // AltOrderSelect - The body of a function that selects the allocation order 263 // to use in a given machine function. The code will be inserted in a 264 // function like this: 265 // 266 // static inline unsigned f(const MachineFunction &MF) { ... } 267 // 268 // The function should return 0 to select the default order defined by 269 // MemberList, 1 to select the first AltOrders entry and so on. 270 code AltOrderSelect = [{}]; 271 272 // Specify allocation priority for register allocators using a greedy 273 // heuristic. Classes with higher priority values are assigned first. This is 274 // useful as it is sometimes beneficial to assign registers to highly 275 // constrained classes first. The value has to be in the range [0,63]. 276 int AllocationPriority = 0; 277 278 // The diagnostic type to present when referencing this operand in a match 279 // failure error message. If this is empty, the default Match_InvalidOperand 280 // diagnostic type will be used. If this is "<name>", a Match_<name> enum 281 // value will be generated and used for this operand type. The target 282 // assembly parser is responsible for converting this into a user-facing 283 // diagnostic message. 284 string DiagnosticType = ""; 285 286 // A diagnostic message to emit when an invalid value is provided for this 287 // register class when it is being used an an assembly operand. If this is 288 // non-empty, an anonymous diagnostic type enum value will be generated, and 289 // the assembly matcher will provide a function to map from diagnostic types 290 // to message strings. 291 string DiagnosticString = ""; 292} 293 294// The memberList in a RegisterClass is a dag of set operations. TableGen 295// evaluates these set operations and expand them into register lists. These 296// are the most common operation, see test/TableGen/SetTheory.td for more 297// examples of what is possible: 298// 299// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 300// register class, or a sub-expression. This is also the way to simply list 301// registers. 302// 303// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 304// 305// (and GPR, CSR) - Set intersection. All registers from the first set that are 306// also in the second set. 307// 308// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 309// numbered registers. Takes an optional 4th operand which is a stride to use 310// when generating the sequence. 311// 312// (shl GPR, 4) - Remove the first N elements. 313// 314// (trunc GPR, 4) - Truncate after the first N elements. 315// 316// (rotl GPR, 1) - Rotate N places to the left. 317// 318// (rotr GPR, 1) - Rotate N places to the right. 319// 320// (decimate GPR, 2) - Pick every N'th element, starting with the first. 321// 322// (interleave A, B, ...) - Interleave the elements from each argument list. 323// 324// All of these operators work on ordered sets, not lists. That means 325// duplicates are removed from sub-expressions. 326 327// Set operators. The rest is defined in TargetSelectionDAG.td. 328def sequence; 329def decimate; 330def interleave; 331 332// RegisterTuples - Automatically generate super-registers by forming tuples of 333// sub-registers. This is useful for modeling register sequence constraints 334// with pseudo-registers that are larger than the architectural registers. 335// 336// The sub-register lists are zipped together: 337// 338// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 339// 340// Generates the same registers as: 341// 342// let SubRegIndices = [sube, subo] in { 343// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 344// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 345// } 346// 347// The generated pseudo-registers inherit super-classes and fields from their 348// first sub-register. Most fields from the Register class are inferred, and 349// the AsmName and Dwarf numbers are cleared. 350// 351// RegisterTuples instances can be used in other set operations to form 352// register classes and so on. This is the only way of using the generated 353// registers. 354// 355// RegNames may be specified to supply asm names for the generated tuples. 356// If used must have the same size as the list of produced registers. 357class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs, 358 list<string> RegNames = []> { 359 // SubRegs - N lists of registers to be zipped up. Super-registers are 360 // synthesized from the first element of each SubRegs list, the second 361 // element and so on. 362 list<dag> SubRegs = Regs; 363 364 // SubRegIndices - N SubRegIndex instances. This provides the names of the 365 // sub-registers in the synthesized super-registers. 366 list<SubRegIndex> SubRegIndices = Indices; 367 368 // List of asm names for the generated tuple registers. 369 list<string> RegAsmNames = RegNames; 370} 371 372 373//===----------------------------------------------------------------------===// 374// DwarfRegNum - This class provides a mapping of the llvm register enumeration 375// to the register numbering used by gcc and gdb. These values are used by a 376// debug information writer to describe where values may be located during 377// execution. 378class DwarfRegNum<list<int> Numbers> { 379 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 380 // These values can be determined by locating the <target>.h file in the 381 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 382 // order of these names correspond to the enumeration used by gcc. A value of 383 // -1 indicates that the gcc number is undefined and -2 that register number 384 // is invalid for this mode/flavour. 385 list<int> DwarfNumbers = Numbers; 386} 387 388// DwarfRegAlias - This class declares that a given register uses the same dwarf 389// numbers as another one. This is useful for making it clear that the two 390// registers do have the same number. It also lets us build a mapping 391// from dwarf register number to llvm register. 392class DwarfRegAlias<Register reg> { 393 Register DwarfAlias = reg; 394} 395 396//===----------------------------------------------------------------------===// 397// Pull in the common support for MCPredicate (portable scheduling predicates). 398// 399include "llvm/Target/TargetInstrPredicate.td" 400 401//===----------------------------------------------------------------------===// 402// Pull in the common support for scheduling 403// 404include "llvm/Target/TargetSchedule.td" 405 406class Predicate; // Forward def 407 408class InstructionEncoding { 409 // Size of encoded instruction. 410 int Size; 411 412 // The "namespace" in which this instruction exists, on targets like ARM 413 // which multiple ISA namespaces exist. 414 string DecoderNamespace = ""; 415 416 // List of predicates which will be turned into isel matching code. 417 list<Predicate> Predicates = []; 418 419 string DecoderMethod = ""; 420 421 // Is the instruction decoder method able to completely determine if the 422 // given instruction is valid or not. If the TableGen definition of the 423 // instruction specifies bitpattern A??B where A and B are static bits, the 424 // hasCompleteDecoder flag says whether the decoder method fully handles the 425 // ?? space, i.e. if it is a final arbiter for the instruction validity. 426 // If not then the decoder attempts to continue decoding when the decoder 427 // method fails. 428 // 429 // This allows to handle situations where the encoding is not fully 430 // orthogonal. Example: 431 // * InstA with bitpattern 0b0000????, 432 // * InstB with bitpattern 0b000000?? but the associated decoder method 433 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11. 434 // 435 // The decoder tries to decode a bitpattern that matches both InstA and 436 // InstB bitpatterns first as InstB (because it is the most specific 437 // encoding). In the default case (hasCompleteDecoder = 1), when 438 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting 439 // hasCompleteDecoder = 0 in InstB, the decoder is informed that 440 // DecodeInstB() is not able to determine if all possible values of ?? are 441 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to 442 // decode the bitpattern as InstA too. 443 bit hasCompleteDecoder = 1; 444} 445 446// Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies 447// an EncodingByHwMode, its Inst and Size members are ignored and Ts are used 448// to encode and decode based on HwMode. 449class EncodingByHwMode<list<HwMode> Ms = [], list<InstructionEncoding> Ts = []> 450 : HwModeSelect<Ms> { 451 // The length of this list must be the same as the length of Ms. 452 list<InstructionEncoding> Objects = Ts; 453} 454 455//===----------------------------------------------------------------------===// 456// Instruction set description - These classes correspond to the C++ classes in 457// the Target/TargetInstrInfo.h file. 458// 459class Instruction : InstructionEncoding { 460 string Namespace = ""; 461 462 dag OutOperandList; // An dag containing the MI def operand list. 463 dag InOperandList; // An dag containing the MI use operand list. 464 string AsmString = ""; // The .s format to print the instruction with. 465 466 // Allows specifying a canonical InstructionEncoding by HwMode. If non-empty, 467 // the Inst member of this Instruction is ignored. 468 EncodingByHwMode EncodingInfos; 469 470 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 471 // otherwise, uninitialized. 472 list<dag> Pattern; 473 474 // The follow state will eventually be inferred automatically from the 475 // instruction pattern. 476 477 list<Register> Uses = []; // Default to using no non-operand registers 478 list<Register> Defs = []; // Default to modifying no non-operand registers 479 480 // Predicates - List of predicates which will be turned into isel matching 481 // code. 482 list<Predicate> Predicates = []; 483 484 // Size - Size of encoded instruction, or zero if the size cannot be determined 485 // from the opcode. 486 int Size = 0; 487 488 // Code size, for instruction selection. 489 // FIXME: What does this actually mean? 490 int CodeSize = 0; 491 492 // Added complexity passed onto matching pattern. 493 int AddedComplexity = 0; 494 495 // Indicates if this is a pre-isel opcode that should be 496 // legalized/regbankselected/selected. 497 bit isPreISelOpcode = 0; 498 499 // These bits capture information about the high-level semantics of the 500 // instruction. 501 bit isReturn = 0; // Is this instruction a return instruction? 502 bit isBranch = 0; // Is this instruction a branch instruction? 503 bit isEHScopeReturn = 0; // Does this instruction end an EH scope? 504 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 505 bit isCompare = 0; // Is this instruction a comparison instruction? 506 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 507 bit isMoveReg = 0; // Is this instruction a move register instruction? 508 bit isBitcast = 0; // Is this instruction a bitcast instruction? 509 bit isSelect = 0; // Is this instruction a select instruction? 510 bit isBarrier = 0; // Can control flow fall through this instruction? 511 bit isCall = 0; // Is this instruction a call instruction? 512 bit isAdd = 0; // Is this instruction an add instruction? 513 bit isTrap = 0; // Is this instruction a trap instruction? 514 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 515 bit mayLoad = ?; // Is it possible for this inst to read memory? 516 bit mayStore = ?; // Is it possible for this inst to write memory? 517 bit mayRaiseFPException = 0; // Can this raise a floating-point exception? 518 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 519 bit isCommutable = 0; // Is this 3 operand instruction commutable? 520 bit isTerminator = 0; // Is this part of the terminator for a basic block? 521 bit isReMaterializable = 0; // Is this instruction re-materializable? 522 bit isPredicable = 0; // 1 means this instruction is predicable 523 // even if it does not have any operand 524 // tablegen can identify as a predicate 525 bit isUnpredicable = 0; // 1 means this instruction is not predicable 526 // even if it _does_ have a predicate operand 527 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 528 bit usesCustomInserter = 0; // Pseudo instr needing special help. 529 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. 530 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 531 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 532 bit isConvergent = 0; // Is this instruction convergent? 533 bit isAuthenticated = 0; // Does this instruction authenticate a pointer? 534 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 535 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 536 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 537 bit isRegSequence = 0; // Is this instruction a kind of reg sequence? 538 // If so, make sure to override 539 // TargetInstrInfo::getRegSequenceLikeInputs. 540 bit isPseudo = 0; // Is this instruction a pseudo-instruction? 541 // If so, won't have encoding information for 542 // the [MC]CodeEmitter stuff. 543 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg? 544 // If so, make sure to override 545 // TargetInstrInfo::getExtractSubregLikeInputs. 546 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg? 547 // If so, make sure to override 548 // TargetInstrInfo::getInsertSubregLikeInputs. 549 bit variadicOpsAreDefs = 0; // Are variadic operands definitions? 550 551 // Does the instruction have side effects that are not captured by any 552 // operands of the instruction or other flags? 553 bit hasSideEffects = ?; 554 555 // Is this instruction a "real" instruction (with a distinct machine 556 // encoding), or is it a pseudo instruction used for codegen modeling 557 // purposes. 558 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 559 // instructions can (and often do) still have encoding information 560 // associated with them. Once we've migrated all of them over to true 561 // pseudo-instructions that are lowered to real instructions prior to 562 // the printer/emitter, we can remove this attribute and just use isPseudo. 563 // 564 // The intended use is: 565 // isPseudo: Does not have encoding information and should be expanded, 566 // at the latest, during lowering to MCInst. 567 // 568 // isCodeGenOnly: Does have encoding information and can go through to the 569 // CodeEmitter unchanged, but duplicates a canonical instruction 570 // definition's encoding and should be ignored when constructing the 571 // assembler match tables. 572 bit isCodeGenOnly = 0; 573 574 // Is this instruction a pseudo instruction for use by the assembler parser. 575 bit isAsmParserOnly = 0; 576 577 // This instruction is not expected to be queried for scheduling latencies 578 // and therefore needs no scheduling information even for a complete 579 // scheduling model. 580 bit hasNoSchedulingInfo = 0; 581 582 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 583 584 // Scheduling information from TargetSchedule.td. 585 list<SchedReadWrite> SchedRW; 586 587 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 588 589 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 590 /// be encoded into the output machineinstr. 591 string DisableEncoding = ""; 592 593 string PostEncoderMethod = ""; 594 595 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 596 bits<64> TSFlags = 0; 597 598 ///@name Assembler Parser Support 599 ///@{ 600 601 string AsmMatchConverter = ""; 602 603 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 604 /// two-operand matcher inst-alias for a three operand instruction. 605 /// For example, the arm instruction "add r3, r3, r5" can be written 606 /// as "add r3, r5". The constraint is of the same form as a tied-operand 607 /// constraint. For example, "$Rn = $Rd". 608 string TwoOperandAliasConstraint = ""; 609 610 /// Assembler variant name to use for this instruction. If specified then 611 /// instruction will be presented only in MatchTable for this variant. If 612 /// not specified then assembler variants will be determined based on 613 /// AsmString 614 string AsmVariantName = ""; 615 616 ///@} 617 618 /// UseNamedOperandTable - If set, the operand indices of this instruction 619 /// can be queried via the getNamedOperandIdx() function which is generated 620 /// by TableGen. 621 bit UseNamedOperandTable = 0; 622 623 /// Should FastISel ignore this instruction. For certain ISAs, they have 624 /// instructions which map to the same ISD Opcode, value type operands and 625 /// instruction selection predicates. FastISel cannot handle such cases, but 626 /// SelectionDAG can. 627 bit FastISelShouldIgnore = 0; 628} 629 630/// Defines an additional encoding that disassembles to the given instruction 631/// Like Instruction, the Inst and SoftFail fields are omitted to allow targets 632// to specify their size. 633class AdditionalEncoding<Instruction I> : InstructionEncoding { 634 Instruction AliasOf = I; 635} 636 637/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 638/// Which instruction it expands to and how the operands map from the 639/// pseudo. 640class PseudoInstExpansion<dag Result> { 641 dag ResultInst = Result; // The instruction to generate. 642 bit isPseudo = 1; 643} 644 645/// Predicates - These are extra conditionals which are turned into instruction 646/// selector matching code. Currently each predicate is just a string. 647class Predicate<string cond> { 648 string CondString = cond; 649 650 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 651 /// matcher, this is true. Targets should set this by inheriting their 652 /// feature from the AssemblerPredicate class in addition to Predicate. 653 bit AssemblerMatcherPredicate = 0; 654 655 /// AssemblerCondString - Name of the subtarget feature being tested used 656 /// as alternative condition string used for assembler matcher. 657 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". 658 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". 659 /// It can also list multiple features separated by ",". 660 /// e.g. "ModeThumb,FeatureThumb2" is translated to 661 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 662 string AssemblerCondString = ""; 663 664 /// PredicateName - User-level name to use for the predicate. Mainly for use 665 /// in diagnostics such as missing feature errors in the asm matcher. 666 string PredicateName = ""; 667 668 /// Setting this to '1' indicates that the predicate must be recomputed on 669 /// every function change. Most predicates can leave this at '0'. 670 /// 671 /// Ignored by SelectionDAG, it always recomputes the predicate on every use. 672 bit RecomputePerFunction = 0; 673} 674 675/// NoHonorSignDependentRounding - This predicate is true if support for 676/// sign-dependent-rounding is not enabled. 677def NoHonorSignDependentRounding 678 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 679 680class Requires<list<Predicate> preds> { 681 list<Predicate> Predicates = preds; 682} 683 684/// ops definition - This is just a simple marker used to identify the operand 685/// list for an instruction. outs and ins are identical both syntactically and 686/// semantically; they are used to define def operands and use operands to 687/// improve readibility. This should be used like this: 688/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 689def ops; 690def outs; 691def ins; 692 693/// variable_ops definition - Mark this instruction as taking a variable number 694/// of operands. 695def variable_ops; 696 697 698/// PointerLikeRegClass - Values that are designed to have pointer width are 699/// derived from this. TableGen treats the register class as having a symbolic 700/// type that it doesn't know, and resolves the actual regclass to use by using 701/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 702class PointerLikeRegClass<int Kind> { 703 int RegClassKind = Kind; 704} 705 706 707/// ptr_rc definition - Mark this operand as being a pointer value whose 708/// register class is resolved dynamically via a callback to TargetInstrInfo. 709/// FIXME: We should probably change this to a class which contain a list of 710/// flags. But currently we have but one flag. 711def ptr_rc : PointerLikeRegClass<0>; 712 713/// unknown definition - Mark this operand as being of unknown type, causing 714/// it to be resolved by inference in the context it is used. 715class unknown_class; 716def unknown : unknown_class; 717 718/// AsmOperandClass - Representation for the kinds of operands which the target 719/// specific parser can create and the assembly matcher may need to distinguish. 720/// 721/// Operand classes are used to define the order in which instructions are 722/// matched, to ensure that the instruction which gets matched for any 723/// particular list of operands is deterministic. 724/// 725/// The target specific parser must be able to classify a parsed operand into a 726/// unique class which does not partially overlap with any other classes. It can 727/// match a subset of some other class, in which case the super class field 728/// should be defined. 729class AsmOperandClass { 730 /// The name to use for this class, which should be usable as an enum value. 731 string Name = ?; 732 733 /// The super classes of this operand. 734 list<AsmOperandClass> SuperClasses = []; 735 736 /// The name of the method on the target specific operand to call to test 737 /// whether the operand is an instance of this class. If not set, this will 738 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 739 /// signature should be: 740 /// bool isFoo() const; 741 string PredicateMethod = ?; 742 743 /// The name of the method on the target specific operand to call to add the 744 /// target specific operand to an MCInst. If not set, this will default to 745 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 746 /// signature should be: 747 /// void addFooOperands(MCInst &Inst, unsigned N) const; 748 string RenderMethod = ?; 749 750 /// The name of the method on the target specific operand to call to custom 751 /// handle the operand parsing. This is useful when the operands do not relate 752 /// to immediates or registers and are very instruction specific (as flags to 753 /// set in a processor register, coprocessor number, ...). 754 string ParserMethod = ?; 755 756 // The diagnostic type to present when referencing this operand in a 757 // match failure error message. By default, use a generic "invalid operand" 758 // diagnostic. The target AsmParser maps these codes to text. 759 string DiagnosticType = ""; 760 761 /// A diagnostic message to emit when an invalid value is provided for this 762 /// operand. 763 string DiagnosticString = ""; 764 765 /// Set to 1 if this operand is optional and not always required. Typically, 766 /// the AsmParser will emit an error when it finishes parsing an 767 /// instruction if it hasn't matched all the operands yet. However, this 768 /// error will be suppressed if all of the remaining unmatched operands are 769 /// marked as IsOptional. 770 /// 771 /// Optional arguments must be at the end of the operand list. 772 bit IsOptional = 0; 773 774 /// The name of the method on the target specific asm parser that returns the 775 /// default operand for this optional operand. This method is only used if 776 /// IsOptional == 1. If not set, this will default to "defaultFooOperands", 777 /// where Foo is the AsmOperandClass name. The method signature should be: 778 /// std::unique_ptr<MCParsedAsmOperand> defaultFooOperands() const; 779 string DefaultMethod = ?; 780} 781 782def ImmAsmOperand : AsmOperandClass { 783 let Name = "Imm"; 784} 785 786/// Operand Types - These provide the built-in operand types that may be used 787/// by a target. Targets can optionally provide their own operand types as 788/// needed, though this should not be needed for RISC targets. 789class Operand<ValueType ty> : DAGOperand { 790 ValueType Type = ty; 791 string PrintMethod = "printOperand"; 792 string EncoderMethod = ""; 793 bit hasCompleteDecoder = 1; 794 string OperandType = "OPERAND_UNKNOWN"; 795 dag MIOperandInfo = (ops); 796 797 // MCOperandPredicate - Optionally, a code fragment operating on 798 // const MCOperand &MCOp, and returning a bool, to indicate if 799 // the value of MCOp is valid for the specific subclass of Operand 800 code MCOperandPredicate; 801 802 // ParserMatchClass - The "match class" that operands of this type fit 803 // in. Match classes are used to define the order in which instructions are 804 // match, to ensure that which instructions gets matched is deterministic. 805 // 806 // The target specific parser must be able to classify an parsed operand into 807 // a unique class, which does not partially overlap with any other classes. It 808 // can match a subset of some other class, in which case the AsmOperandClass 809 // should declare the other operand as one of its super classes. 810 AsmOperandClass ParserMatchClass = ImmAsmOperand; 811} 812 813class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> 814 : DAGOperand { 815 // RegClass - The register class of the operand. 816 RegisterClass RegClass = regclass; 817 // PrintMethod - The target method to call to print register operands of 818 // this type. The method normally will just use an alt-name index to look 819 // up the name to print. Default to the generic printOperand(). 820 string PrintMethod = pm; 821 822 // EncoderMethod - The target method name to call to encode this register 823 // operand. 824 string EncoderMethod = ""; 825 826 // ParserMatchClass - The "match class" that operands of this type fit 827 // in. Match classes are used to define the order in which instructions are 828 // match, to ensure that which instructions gets matched is deterministic. 829 // 830 // The target specific parser must be able to classify an parsed operand into 831 // a unique class, which does not partially overlap with any other classes. It 832 // can match a subset of some other class, in which case the AsmOperandClass 833 // should declare the other operand as one of its super classes. 834 AsmOperandClass ParserMatchClass; 835 836 string OperandType = "OPERAND_REGISTER"; 837 838 // When referenced in the result of a CodeGen pattern, GlobalISel will 839 // normally copy the matched operand to the result. When this is set, it will 840 // emit a special copy that will replace zero-immediates with the specified 841 // zero-register. 842 Register GIZeroRegister = ?; 843} 844 845let OperandType = "OPERAND_IMMEDIATE" in { 846def i1imm : Operand<i1>; 847def i8imm : Operand<i8>; 848def i16imm : Operand<i16>; 849def i32imm : Operand<i32>; 850def i64imm : Operand<i64>; 851 852def f32imm : Operand<f32>; 853def f64imm : Operand<f64>; 854} 855 856// Register operands for generic instructions don't have an MVT, but do have 857// constraints linking the operands (e.g. all operands of a G_ADD must 858// have the same LLT). 859class TypedOperand<string Ty> : Operand<untyped> { 860 let OperandType = Ty; 861 bit IsPointer = 0; 862 bit IsImmediate = 0; 863} 864 865def type0 : TypedOperand<"OPERAND_GENERIC_0">; 866def type1 : TypedOperand<"OPERAND_GENERIC_1">; 867def type2 : TypedOperand<"OPERAND_GENERIC_2">; 868def type3 : TypedOperand<"OPERAND_GENERIC_3">; 869def type4 : TypedOperand<"OPERAND_GENERIC_4">; 870def type5 : TypedOperand<"OPERAND_GENERIC_5">; 871 872let IsPointer = 1 in { 873 def ptype0 : TypedOperand<"OPERAND_GENERIC_0">; 874 def ptype1 : TypedOperand<"OPERAND_GENERIC_1">; 875 def ptype2 : TypedOperand<"OPERAND_GENERIC_2">; 876 def ptype3 : TypedOperand<"OPERAND_GENERIC_3">; 877 def ptype4 : TypedOperand<"OPERAND_GENERIC_4">; 878 def ptype5 : TypedOperand<"OPERAND_GENERIC_5">; 879} 880 881// untyped_imm is for operands where isImm() will be true. It currently has no 882// special behaviour and is only used for clarity. 883def untyped_imm_0 : TypedOperand<"OPERAND_GENERIC_IMM_0"> { 884 let IsImmediate = 1; 885} 886 887/// zero_reg definition - Special node to stand for the zero register. 888/// 889def zero_reg; 890 891/// All operands which the MC layer classifies as predicates should inherit from 892/// this class in some manner. This is already handled for the most commonly 893/// used PredicateOperand, but may be useful in other circumstances. 894class PredicateOp; 895 896/// OperandWithDefaultOps - This Operand class can be used as the parent class 897/// for an Operand that needs to be initialized with a default value if 898/// no value is supplied in a pattern. This class can be used to simplify the 899/// pattern definitions for instructions that have target specific flags 900/// encoded as immediate operands. 901class OperandWithDefaultOps<ValueType ty, dag defaultops> 902 : Operand<ty> { 903 dag DefaultOps = defaultops; 904} 905 906/// PredicateOperand - This can be used to define a predicate operand for an 907/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 908/// AlwaysVal specifies the value of this predicate when set to "always 909/// execute". 910class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 911 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp { 912 let MIOperandInfo = OpTypes; 913} 914 915/// OptionalDefOperand - This is used to define a optional definition operand 916/// for an instruction. DefaultOps is the register the operand represents if 917/// none is supplied, e.g. zero_reg. 918class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 919 : OperandWithDefaultOps<ty, defaultops> { 920 let MIOperandInfo = OpTypes; 921} 922 923 924// InstrInfo - This class should only be instantiated once to provide parameters 925// which are global to the target machine. 926// 927class InstrInfo { 928 // Target can specify its instructions in either big or little-endian formats. 929 // For instance, while both Sparc and PowerPC are big-endian platforms, the 930 // Sparc manual specifies its instructions in the format [31..0] (big), while 931 // PowerPC specifies them using the format [0..31] (little). 932 bit isLittleEndianEncoding = 0; 933 934 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset 935 // by default, and TableGen will infer their value from the instruction 936 // pattern when possible. 937 // 938 // Normally, TableGen will issue an error it it can't infer the value of a 939 // property that hasn't been set explicitly. When guessInstructionProperties 940 // is set, it will guess a safe value instead. 941 // 942 // This option is a temporary migration help. It will go away. 943 bit guessInstructionProperties = 1; 944 945 // TableGen's instruction encoder generator has support for matching operands 946 // to bit-field variables both by name and by position. While matching by 947 // name is preferred, this is currently not possible for complex operands, 948 // and some targets still reply on the positional encoding rules. When 949 // generating a decoder for such targets, the positional encoding rules must 950 // be used by the decoder generator as well. 951 // 952 // This option is temporary; it will go away once the TableGen decoder 953 // generator has better support for complex operands and targets have 954 // migrated away from using positionally encoded operands. 955 bit decodePositionallyEncodedOperands = 0; 956 957 // When set, this indicates that there will be no overlap between those 958 // operands that are matched by ordering (positional operands) and those 959 // matched by name. 960 // 961 // This option is temporary; it will go away once the TableGen decoder 962 // generator has better support for complex operands and targets have 963 // migrated away from using positionally encoded operands. 964 bit noNamedPositionallyEncodedOperands = 0; 965} 966 967// Standard Pseudo Instructions. 968// This list must match TargetOpcodes.def. 969// Only these instructions are allowed in the TargetOpcode namespace. 970// Ensure mayLoad and mayStore have a default value, so as not to break 971// targets that set guessInstructionProperties=0. Any local definition of 972// mayLoad/mayStore takes precedence over these default values. 973class StandardPseudoInstruction : Instruction { 974 let mayLoad = 0; 975 let mayStore = 0; 976 let isCodeGenOnly = 1; 977 let isPseudo = 1; 978 let hasNoSchedulingInfo = 1; 979 let Namespace = "TargetOpcode"; 980} 981def PHI : StandardPseudoInstruction { 982 let OutOperandList = (outs unknown:$dst); 983 let InOperandList = (ins variable_ops); 984 let AsmString = "PHINODE"; 985 let hasSideEffects = 0; 986} 987def INLINEASM : StandardPseudoInstruction { 988 let OutOperandList = (outs); 989 let InOperandList = (ins variable_ops); 990 let AsmString = ""; 991 let hasSideEffects = 0; // Note side effect is encoded in an operand. 992} 993def INLINEASM_BR : StandardPseudoInstruction { 994 let OutOperandList = (outs); 995 let InOperandList = (ins variable_ops); 996 let AsmString = ""; 997 let hasSideEffects = 0; // Note side effect is encoded in an operand. 998 let isTerminator = 1; 999 let isBranch = 1; 1000 let isIndirectBranch = 1; 1001} 1002def CFI_INSTRUCTION : StandardPseudoInstruction { 1003 let OutOperandList = (outs); 1004 let InOperandList = (ins i32imm:$id); 1005 let AsmString = ""; 1006 let hasCtrlDep = 1; 1007 let hasSideEffects = 0; 1008 let isNotDuplicable = 1; 1009} 1010def EH_LABEL : StandardPseudoInstruction { 1011 let OutOperandList = (outs); 1012 let InOperandList = (ins i32imm:$id); 1013 let AsmString = ""; 1014 let hasCtrlDep = 1; 1015 let hasSideEffects = 0; 1016 let isNotDuplicable = 1; 1017} 1018def GC_LABEL : StandardPseudoInstruction { 1019 let OutOperandList = (outs); 1020 let InOperandList = (ins i32imm:$id); 1021 let AsmString = ""; 1022 let hasCtrlDep = 1; 1023 let hasSideEffects = 0; 1024 let isNotDuplicable = 1; 1025} 1026def ANNOTATION_LABEL : StandardPseudoInstruction { 1027 let OutOperandList = (outs); 1028 let InOperandList = (ins i32imm:$id); 1029 let AsmString = ""; 1030 let hasCtrlDep = 1; 1031 let hasSideEffects = 0; 1032 let isNotDuplicable = 1; 1033} 1034def KILL : StandardPseudoInstruction { 1035 let OutOperandList = (outs); 1036 let InOperandList = (ins variable_ops); 1037 let AsmString = ""; 1038 let hasSideEffects = 0; 1039} 1040def EXTRACT_SUBREG : StandardPseudoInstruction { 1041 let OutOperandList = (outs unknown:$dst); 1042 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 1043 let AsmString = ""; 1044 let hasSideEffects = 0; 1045} 1046def INSERT_SUBREG : StandardPseudoInstruction { 1047 let OutOperandList = (outs unknown:$dst); 1048 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 1049 let AsmString = ""; 1050 let hasSideEffects = 0; 1051 let Constraints = "$supersrc = $dst"; 1052} 1053def IMPLICIT_DEF : StandardPseudoInstruction { 1054 let OutOperandList = (outs unknown:$dst); 1055 let InOperandList = (ins); 1056 let AsmString = ""; 1057 let hasSideEffects = 0; 1058 let isReMaterializable = 1; 1059 let isAsCheapAsAMove = 1; 1060} 1061def SUBREG_TO_REG : StandardPseudoInstruction { 1062 let OutOperandList = (outs unknown:$dst); 1063 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 1064 let AsmString = ""; 1065 let hasSideEffects = 0; 1066} 1067def COPY_TO_REGCLASS : StandardPseudoInstruction { 1068 let OutOperandList = (outs unknown:$dst); 1069 let InOperandList = (ins unknown:$src, i32imm:$regclass); 1070 let AsmString = ""; 1071 let hasSideEffects = 0; 1072 let isAsCheapAsAMove = 1; 1073} 1074def DBG_VALUE : StandardPseudoInstruction { 1075 let OutOperandList = (outs); 1076 let InOperandList = (ins variable_ops); 1077 let AsmString = "DBG_VALUE"; 1078 let hasSideEffects = 0; 1079} 1080def DBG_LABEL : StandardPseudoInstruction { 1081 let OutOperandList = (outs); 1082 let InOperandList = (ins unknown:$label); 1083 let AsmString = "DBG_LABEL"; 1084 let hasSideEffects = 0; 1085} 1086def REG_SEQUENCE : StandardPseudoInstruction { 1087 let OutOperandList = (outs unknown:$dst); 1088 let InOperandList = (ins unknown:$supersrc, variable_ops); 1089 let AsmString = ""; 1090 let hasSideEffects = 0; 1091 let isAsCheapAsAMove = 1; 1092} 1093def COPY : StandardPseudoInstruction { 1094 let OutOperandList = (outs unknown:$dst); 1095 let InOperandList = (ins unknown:$src); 1096 let AsmString = ""; 1097 let hasSideEffects = 0; 1098 let isAsCheapAsAMove = 1; 1099 let hasNoSchedulingInfo = 0; 1100} 1101def BUNDLE : StandardPseudoInstruction { 1102 let OutOperandList = (outs); 1103 let InOperandList = (ins variable_ops); 1104 let AsmString = "BUNDLE"; 1105 let hasSideEffects = 0; 1106} 1107def LIFETIME_START : StandardPseudoInstruction { 1108 let OutOperandList = (outs); 1109 let InOperandList = (ins i32imm:$id); 1110 let AsmString = "LIFETIME_START"; 1111 let hasSideEffects = 0; 1112} 1113def LIFETIME_END : StandardPseudoInstruction { 1114 let OutOperandList = (outs); 1115 let InOperandList = (ins i32imm:$id); 1116 let AsmString = "LIFETIME_END"; 1117 let hasSideEffects = 0; 1118} 1119def STACKMAP : StandardPseudoInstruction { 1120 let OutOperandList = (outs); 1121 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops); 1122 let hasSideEffects = 1; 1123 let isCall = 1; 1124 let mayLoad = 1; 1125 let usesCustomInserter = 1; 1126} 1127def PATCHPOINT : StandardPseudoInstruction { 1128 let OutOperandList = (outs unknown:$dst); 1129 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee, 1130 i32imm:$nargs, i32imm:$cc, variable_ops); 1131 let hasSideEffects = 1; 1132 let isCall = 1; 1133 let mayLoad = 1; 1134 let usesCustomInserter = 1; 1135} 1136def STATEPOINT : StandardPseudoInstruction { 1137 let OutOperandList = (outs); 1138 let InOperandList = (ins variable_ops); 1139 let usesCustomInserter = 1; 1140 let mayLoad = 1; 1141 let mayStore = 1; 1142 let hasSideEffects = 1; 1143 let isCall = 1; 1144} 1145def LOAD_STACK_GUARD : StandardPseudoInstruction { 1146 let OutOperandList = (outs ptr_rc:$dst); 1147 let InOperandList = (ins); 1148 let mayLoad = 1; 1149 bit isReMaterializable = 1; 1150 let hasSideEffects = 0; 1151 bit isPseudo = 1; 1152} 1153def LOCAL_ESCAPE : StandardPseudoInstruction { 1154 // This instruction is really just a label. It has to be part of the chain so 1155 // that it doesn't get dropped from the DAG, but it produces nothing and has 1156 // no side effects. 1157 let OutOperandList = (outs); 1158 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id); 1159 let hasSideEffects = 0; 1160 let hasCtrlDep = 1; 1161} 1162def FAULTING_OP : StandardPseudoInstruction { 1163 let OutOperandList = (outs unknown:$dst); 1164 let InOperandList = (ins variable_ops); 1165 let usesCustomInserter = 1; 1166 let hasSideEffects = 1; 1167 let mayLoad = 1; 1168 let mayStore = 1; 1169 let isTerminator = 1; 1170 let isBranch = 1; 1171} 1172def PATCHABLE_OP : StandardPseudoInstruction { 1173 let OutOperandList = (outs); 1174 let InOperandList = (ins variable_ops); 1175 let usesCustomInserter = 1; 1176 let mayLoad = 1; 1177 let mayStore = 1; 1178 let hasSideEffects = 1; 1179} 1180def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction { 1181 let OutOperandList = (outs); 1182 let InOperandList = (ins); 1183 let AsmString = "# XRay Function Enter."; 1184 let usesCustomInserter = 1; 1185 let hasSideEffects = 1; 1186} 1187def PATCHABLE_RET : StandardPseudoInstruction { 1188 let OutOperandList = (outs); 1189 let InOperandList = (ins variable_ops); 1190 let AsmString = "# XRay Function Patchable RET."; 1191 let usesCustomInserter = 1; 1192 let hasSideEffects = 1; 1193 let isTerminator = 1; 1194 let isReturn = 1; 1195} 1196def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction { 1197 let OutOperandList = (outs); 1198 let InOperandList = (ins); 1199 let AsmString = "# XRay Function Exit."; 1200 let usesCustomInserter = 1; 1201 let hasSideEffects = 1; 1202 let isReturn = 0; // Original return instruction will follow 1203} 1204def PATCHABLE_TAIL_CALL : StandardPseudoInstruction { 1205 let OutOperandList = (outs); 1206 let InOperandList = (ins variable_ops); 1207 let AsmString = "# XRay Tail Call Exit."; 1208 let usesCustomInserter = 1; 1209 let hasSideEffects = 1; 1210 let isReturn = 1; 1211} 1212def PATCHABLE_EVENT_CALL : StandardPseudoInstruction { 1213 let OutOperandList = (outs); 1214 let InOperandList = (ins ptr_rc:$event, unknown:$size); 1215 let AsmString = "# XRay Custom Event Log."; 1216 let usesCustomInserter = 1; 1217 let isCall = 1; 1218 let mayLoad = 1; 1219 let mayStore = 1; 1220 let hasSideEffects = 1; 1221} 1222def PATCHABLE_TYPED_EVENT_CALL : StandardPseudoInstruction { 1223 let OutOperandList = (outs); 1224 let InOperandList = (ins unknown:$type, ptr_rc:$event, unknown:$size); 1225 let AsmString = "# XRay Typed Event Log."; 1226 let usesCustomInserter = 1; 1227 let isCall = 1; 1228 let mayLoad = 1; 1229 let mayStore = 1; 1230 let hasSideEffects = 1; 1231} 1232def FENTRY_CALL : StandardPseudoInstruction { 1233 let OutOperandList = (outs); 1234 let InOperandList = (ins); 1235 let AsmString = "# FEntry call"; 1236 let usesCustomInserter = 1; 1237 let mayLoad = 1; 1238 let mayStore = 1; 1239 let hasSideEffects = 1; 1240} 1241def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction { 1242 let OutOperandList = (outs); 1243 let InOperandList = (ins variable_ops); 1244 let AsmString = ""; 1245 let hasSideEffects = 1; 1246} 1247 1248// Generic opcodes used in GlobalISel. 1249include "llvm/Target/GenericOpcodes.td" 1250 1251//===----------------------------------------------------------------------===// 1252// AsmParser - This class can be implemented by targets that wish to implement 1253// .s file parsing. 1254// 1255// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 1256// syntax on X86 for example). 1257// 1258class AsmParser { 1259 // AsmParserClassName - This specifies the suffix to use for the asmparser 1260 // class. Generated AsmParser classes are always prefixed with the target 1261 // name. 1262 string AsmParserClassName = "AsmParser"; 1263 1264 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 1265 // function of the AsmParser class to call on every matched instruction. 1266 // This can be used to perform target specific instruction post-processing. 1267 string AsmParserInstCleanup = ""; 1268 1269 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand 1270 // written register name matcher 1271 bit ShouldEmitMatchRegisterName = 1; 1272 1273 // Set to true if the target needs a generated 'alternative register name' 1274 // matcher. 1275 // 1276 // This generates a function which can be used to lookup registers from 1277 // their aliases. This function will fail when called on targets where 1278 // several registers share the same alias (i.e. not a 1:1 mapping). 1279 bit ShouldEmitMatchRegisterAltName = 0; 1280 1281 // Set to true if MatchRegisterName and MatchRegisterAltName functions 1282 // should be generated even if there are duplicate register names. The 1283 // target is responsible for coercing aliased registers as necessary 1284 // (e.g. in validateTargetOperandClass), and there are no guarantees about 1285 // which numeric register identifier will be returned in the case of 1286 // multiple matches. 1287 bit AllowDuplicateRegisterNames = 0; 1288 1289 // HasMnemonicFirst - Set to false if target instructions don't always 1290 // start with a mnemonic as the first token. 1291 bit HasMnemonicFirst = 1; 1292 1293 // ReportMultipleNearMisses - 1294 // When 0, the assembly matcher reports an error for one encoding or operand 1295 // that did not match the parsed instruction. 1296 // When 1, the assembly matcher returns a list of encodings that were close 1297 // to matching the parsed instruction, so to allow more detailed error 1298 // messages. 1299 bit ReportMultipleNearMisses = 0; 1300} 1301def DefaultAsmParser : AsmParser; 1302 1303//===----------------------------------------------------------------------===// 1304// AsmParserVariant - Subtargets can have multiple different assembly parsers 1305// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 1306// implemented by targets to describe such variants. 1307// 1308class AsmParserVariant { 1309 // Variant - AsmParsers can be of multiple different variants. Variants are 1310 // used to support targets that need to parser multiple formats for the 1311 // assembly language. 1312 int Variant = 0; 1313 1314 // Name - The AsmParser variant name (e.g., AT&T vs Intel). 1315 string Name = ""; 1316 1317 // CommentDelimiter - If given, the delimiter string used to recognize 1318 // comments which are hard coded in the .td assembler strings for individual 1319 // instructions. 1320 string CommentDelimiter = ""; 1321 1322 // RegisterPrefix - If given, the token prefix which indicates a register 1323 // token. This is used by the matcher to automatically recognize hard coded 1324 // register tokens as constrained registers, instead of tokens, for the 1325 // purposes of matching. 1326 string RegisterPrefix = ""; 1327 1328 // TokenizingCharacters - Characters that are standalone tokens 1329 string TokenizingCharacters = "[]*!"; 1330 1331 // SeparatorCharacters - Characters that are not tokens 1332 string SeparatorCharacters = " \t,"; 1333 1334 // BreakCharacters - Characters that start new identifiers 1335 string BreakCharacters = ""; 1336} 1337def DefaultAsmParserVariant : AsmParserVariant; 1338 1339/// AssemblerPredicate - This is a Predicate that can be used when the assembler 1340/// matches instructions and aliases. 1341class AssemblerPredicate<string cond, string name = ""> { 1342 bit AssemblerMatcherPredicate = 1; 1343 string AssemblerCondString = cond; 1344 string PredicateName = name; 1345} 1346 1347/// TokenAlias - This class allows targets to define assembler token 1348/// operand aliases. That is, a token literal operand which is equivalent 1349/// to another, canonical, token literal. For example, ARM allows: 1350/// vmov.u32 s4, #0 -> vmov.i32, #0 1351/// 'u32' is a more specific designator for the 32-bit integer type specifier 1352/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 1353/// def : TokenAlias<".u32", ".i32">; 1354/// 1355/// This works by marking the match class of 'From' as a subclass of the 1356/// match class of 'To'. 1357class TokenAlias<string From, string To> { 1358 string FromToken = From; 1359 string ToToken = To; 1360} 1361 1362/// MnemonicAlias - This class allows targets to define assembler mnemonic 1363/// aliases. This should be used when all forms of one mnemonic are accepted 1364/// with a different mnemonic. For example, X86 allows: 1365/// sal %al, 1 -> shl %al, 1 1366/// sal %ax, %cl -> shl %ax, %cl 1367/// sal %eax, %cl -> shl %eax, %cl 1368/// etc. Though "sal" is accepted with many forms, all of them are directly 1369/// translated to a shl, so it can be handled with (in the case of X86, it 1370/// actually has one for each suffix as well): 1371/// def : MnemonicAlias<"sal", "shl">; 1372/// 1373/// Mnemonic aliases are mapped before any other translation in the match phase, 1374/// and do allow Requires predicates, e.g.: 1375/// 1376/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 1377/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 1378/// 1379/// Mnemonic aliases can also be constrained to specific variants, e.g.: 1380/// 1381/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 1382/// 1383/// If no variant (e.g., "att" or "intel") is specified then the alias is 1384/// applied unconditionally. 1385class MnemonicAlias<string From, string To, string VariantName = ""> { 1386 string FromMnemonic = From; 1387 string ToMnemonic = To; 1388 string AsmVariantName = VariantName; 1389 1390 // Predicates - Predicates that must be true for this remapping to happen. 1391 list<Predicate> Predicates = []; 1392} 1393 1394/// InstAlias - This defines an alternate assembly syntax that is allowed to 1395/// match an instruction that has a different (more canonical) assembly 1396/// representation. 1397class InstAlias<string Asm, dag Result, int Emit = 1, string VariantName = ""> { 1398 string AsmString = Asm; // The .s format to match the instruction with. 1399 dag ResultInst = Result; // The MCInst to generate. 1400 1401 // This determines which order the InstPrinter detects aliases for 1402 // printing. A larger value makes the alias more likely to be 1403 // emitted. The Instruction's own definition is notionally 0.5, so 0 1404 // disables printing and 1 enables it if there are no conflicting aliases. 1405 int EmitPriority = Emit; 1406 1407 // Predicates - Predicates that must be true for this to match. 1408 list<Predicate> Predicates = []; 1409 1410 // If the instruction specified in Result has defined an AsmMatchConverter 1411 // then setting this to 1 will cause the alias to use the AsmMatchConverter 1412 // function when converting the OperandVector into an MCInst instead of the 1413 // function that is generated by the dag Result. 1414 // Setting this to 0 will cause the alias to ignore the Result instruction's 1415 // defined AsmMatchConverter and instead use the function generated by the 1416 // dag Result. 1417 bit UseInstAsmMatchConverter = 1; 1418 1419 // Assembler variant name to use for this alias. If not specified then 1420 // assembler variants will be determined based on AsmString 1421 string AsmVariantName = VariantName; 1422} 1423 1424//===----------------------------------------------------------------------===// 1425// AsmWriter - This class can be implemented by targets that need to customize 1426// the format of the .s file writer. 1427// 1428// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 1429// on X86 for example). 1430// 1431class AsmWriter { 1432 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 1433 // class. Generated AsmWriter classes are always prefixed with the target 1434 // name. 1435 string AsmWriterClassName = "InstPrinter"; 1436 1437 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to 1438 // the various print methods. 1439 // FIXME: Remove after all ports are updated. 1440 int PassSubtarget = 0; 1441 1442 // Variant - AsmWriters can be of multiple different variants. Variants are 1443 // used to support targets that need to emit assembly code in ways that are 1444 // mostly the same for different targets, but have minor differences in 1445 // syntax. If the asmstring contains {|} characters in them, this integer 1446 // will specify which alternative to use. For example "{x|y|z}" with Variant 1447 // == 1, will expand to "y". 1448 int Variant = 0; 1449} 1450def DefaultAsmWriter : AsmWriter; 1451 1452 1453//===----------------------------------------------------------------------===// 1454// Target - This class contains the "global" target information 1455// 1456class Target { 1457 // InstructionSet - Instruction set description for this target. 1458 InstrInfo InstructionSet; 1459 1460 // AssemblyParsers - The AsmParser instances available for this target. 1461 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 1462 1463 /// AssemblyParserVariants - The AsmParserVariant instances available for 1464 /// this target. 1465 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 1466 1467 // AssemblyWriters - The AsmWriter instances available for this target. 1468 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 1469 1470 // AllowRegisterRenaming - Controls whether this target allows 1471 // post-register-allocation renaming of registers. This is done by 1472 // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1 1473 // for all opcodes if this flag is set to 0. 1474 int AllowRegisterRenaming = 0; 1475} 1476 1477//===----------------------------------------------------------------------===// 1478// SubtargetFeature - A characteristic of the chip set. 1479// 1480class SubtargetFeature<string n, string a, string v, string d, 1481 list<SubtargetFeature> i = []> { 1482 // Name - Feature name. Used by command line (-mattr=) to determine the 1483 // appropriate target chip. 1484 // 1485 string Name = n; 1486 1487 // Attribute - Attribute to be set by feature. 1488 // 1489 string Attribute = a; 1490 1491 // Value - Value the attribute to be set to by feature. 1492 // 1493 string Value = v; 1494 1495 // Desc - Feature description. Used by command line (-mattr=) to display help 1496 // information. 1497 // 1498 string Desc = d; 1499 1500 // Implies - Features that this feature implies are present. If one of those 1501 // features isn't set, then this one shouldn't be set either. 1502 // 1503 list<SubtargetFeature> Implies = i; 1504} 1505 1506/// Specifies a Subtarget feature that this instruction is deprecated on. 1507class Deprecated<SubtargetFeature dep> { 1508 SubtargetFeature DeprecatedFeatureMask = dep; 1509} 1510 1511/// A custom predicate used to determine if an instruction is 1512/// deprecated or not. 1513class ComplexDeprecationPredicate<string dep> { 1514 string ComplexDeprecationPredicate = dep; 1515} 1516 1517//===----------------------------------------------------------------------===// 1518// Processor chip sets - These values represent each of the chip sets supported 1519// by the scheduler. Each Processor definition requires corresponding 1520// instruction itineraries. 1521// 1522class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 1523 // Name - Chip set name. Used by command line (-mcpu=) to determine the 1524 // appropriate target chip. 1525 // 1526 string Name = n; 1527 1528 // SchedModel - The machine model for scheduling and instruction cost. 1529 // 1530 SchedMachineModel SchedModel = NoSchedModel; 1531 1532 // ProcItin - The scheduling information for the target processor. 1533 // 1534 ProcessorItineraries ProcItin = pi; 1535 1536 // Features - list of 1537 list<SubtargetFeature> Features = f; 1538} 1539 1540// ProcessorModel allows subtargets to specify the more general 1541// SchedMachineModel instead if a ProcessorItinerary. Subtargets will 1542// gradually move to this newer form. 1543// 1544// Although this class always passes NoItineraries to the Processor 1545// class, the SchedMachineModel may still define valid Itineraries. 1546class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f> 1547 : Processor<n, NoItineraries, f> { 1548 let SchedModel = m; 1549} 1550 1551//===----------------------------------------------------------------------===// 1552// InstrMapping - This class is used to create mapping tables to relate 1553// instructions with each other based on the values specified in RowFields, 1554// ColFields, KeyCol and ValueCols. 1555// 1556class InstrMapping { 1557 // FilterClass - Used to limit search space only to the instructions that 1558 // define the relationship modeled by this InstrMapping record. 1559 string FilterClass; 1560 1561 // RowFields - List of fields/attributes that should be same for all the 1562 // instructions in a row of the relation table. Think of this as a set of 1563 // properties shared by all the instructions related by this relationship 1564 // model and is used to categorize instructions into subgroups. For instance, 1565 // if we want to define a relation that maps 'Add' instruction to its 1566 // predicated forms, we can define RowFields like this: 1567 // 1568 // let RowFields = BaseOp 1569 // All add instruction predicated/non-predicated will have to set their BaseOp 1570 // to the same value. 1571 // 1572 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } 1573 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } 1574 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' } 1575 list<string> RowFields = []; 1576 1577 // List of fields/attributes that are same for all the instructions 1578 // in a column of the relation table. 1579 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged 1580 // based on the 'predSense' values. All the instruction in a specific 1581 // column have the same value and it is fixed for the column according 1582 // to the values set in 'ValueCols'. 1583 list<string> ColFields = []; 1584 1585 // Values for the fields/attributes listed in 'ColFields'. 1586 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction 1587 // that models this relation) should be non-predicated. 1588 // In the example above, 'Add' is the key instruction. 1589 list<string> KeyCol = []; 1590 1591 // List of values for the fields/attributes listed in 'ColFields', one for 1592 // each column in the relation table. 1593 // 1594 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the 1595 // table. First column requires all the instructions to have predSense 1596 // set to 'true' and second column requires it to be 'false'. 1597 list<list<string> > ValueCols = []; 1598} 1599 1600//===----------------------------------------------------------------------===// 1601// Pull in the common support for calling conventions. 1602// 1603include "llvm/Target/TargetCallingConv.td" 1604 1605//===----------------------------------------------------------------------===// 1606// Pull in the common support for DAG isel generation. 1607// 1608include "llvm/Target/TargetSelectionDAG.td" 1609 1610//===----------------------------------------------------------------------===// 1611// Pull in the common support for Global ISel register bank info generation. 1612// 1613include "llvm/Target/GlobalISel/RegisterBank.td" 1614 1615//===----------------------------------------------------------------------===// 1616// Pull in the common support for DAG isel generation. 1617// 1618include "llvm/Target/GlobalISel/Target.td" 1619 1620//===----------------------------------------------------------------------===// 1621// Pull in the common support for the Global ISel DAG-based selector generation. 1622// 1623include "llvm/Target/GlobalISel/SelectionDAGCompat.td" 1624 1625//===----------------------------------------------------------------------===// 1626// Pull in the common support for Pfm Counters generation. 1627// 1628include "llvm/Target/TargetPfmCounters.td" 1629