1//===- TargetInstrPredicate.td - ---------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines class MCInstPredicate and its subclasses. 10// 11// MCInstPredicate definitions are used by target scheduling models to describe 12// constraints on instructions. 13// 14// Here is an example of an MCInstPredicate definition in TableGen: 15// 16// def MCInstPredicateExample : CheckAll<[ 17// CheckOpcode<[BLR]>, 18// CheckIsRegOperand<0>, 19// CheckNot<CheckRegOperand<0, LR>>]>; 20// 21// The syntax for MCInstPredicate is declarative, and predicate definitions can 22// be composed together in order to generate more complex constraints. 23// 24// The `CheckAll` from the example defines a composition of three different 25// predicates. Definition `MCInstPredicateExample` identifies instructions 26// whose opcode is BLR, and whose first operand is a register different from 27// register `LR`. 28// 29// Every MCInstPredicate class has a well-known semantic in tablegen. For 30// example, `CheckOpcode` is a special type of predicate used to describe a 31// constraint on the value of an instruction opcode. 32// 33// MCInstPredicate definitions are typically used by scheduling models to 34// construct MCSchedPredicate definitions (see the definition of class 35// MCSchedPredicate in llvm/Target/TargetSchedule.td). 36// In particular, an MCSchedPredicate can be used instead of a SchedPredicate 37// when defining the set of SchedReadVariant and SchedWriteVariant of a 38// processor scheduling model. 39// 40// The `MCInstPredicateExample` definition above is equivalent (and therefore 41// could replace) the following definition from a previous ExynosM3 model (see 42// AArch64SchedExynosM3.td): 43// 44// def M3BranchLinkFastPred : SchedPredicate<[{ 45// MI->getOpcode() == AArch64::BLR && 46// MI->getOperand(0).isReg() && 47// MI->getOperand(0).getReg() != AArch64::LR}]>; 48// 49// The main advantage of using MCInstPredicate instead of SchedPredicate is 50// portability: users don't need to specify predicates in C++. As a consequence 51// of this, MCInstPredicate definitions are not bound to a particular 52// representation (i.e. MachineInstr vs MCInst). 53// 54// Tablegen backends know how to expand MCInstPredicate definitions into actual 55// C++ code that works on MachineInstr (and/or MCInst). 56// 57// Instances of class PredicateExpander (see utils/Tablegen/PredicateExpander.h) 58// know how to expand a predicate. For each MCInstPredicate class, there must be 59// an "expand" method available in the PredicateExpander interface. 60// 61// For example, a `CheckOpcode` predicate is expanded using method 62// `PredicateExpander::expandCheckOpcode()`. 63// 64// New MCInstPredicate classes must be added to this file. For each new class 65// XYZ, an "expandXYZ" method must be added to the PredicateExpander. 66// 67//===----------------------------------------------------------------------===// 68 69// Forward declarations. 70class Instruction; 71class SchedMachineModel; 72 73// A generic machine instruction predicate. 74class MCInstPredicate; 75 76class MCTrue : MCInstPredicate; // A predicate that always evaluates to True. 77class MCFalse : MCInstPredicate; // A predicate that always evaluates to False. 78def TruePred : MCTrue; 79def FalsePred : MCFalse; 80 81// A predicate used to negate the outcome of another predicate. 82// It allows to easily express "set difference" operations. For example, it 83// makes it easy to describe a check that tests if an opcode is not part of a 84// set of opcodes. 85class CheckNot<MCInstPredicate P> : MCInstPredicate { 86 MCInstPredicate Pred = P; 87} 88 89// This class is used as a building block to define predicates on instruction 90// operands. It is used to reference a specific machine operand. 91class MCOperandPredicate<int Index> : MCInstPredicate { 92 int OpIndex = Index; 93} 94 95// Return true if machine operand at position `Index` is a register operand. 96class CheckIsRegOperand<int Index> : MCOperandPredicate<Index>; 97 98// Return true if machine operand at position `Index` is an immediate operand. 99class CheckIsImmOperand<int Index> : MCOperandPredicate<Index>; 100 101// Check if machine operands at index `First` and index `Second` both reference 102// the same register. 103class CheckSameRegOperand<int First, int Second> : MCInstPredicate { 104 int FirstIndex = First; 105 int SecondIndex = Second; 106} 107 108// Base class for checks on register/immediate operands. 109// It allows users to define checks like: 110// MyFunction(MI->getOperand(Index).getImm()) == Val; 111// 112// In the example above, `MyFunction` is a function that takes as input an 113// immediate operand value, and returns another value. Field `FunctionMapper` is 114// the name of the function to call on the operand value. 115class CheckOperandBase<int Index, string Fn = ""> : MCOperandPredicate<Index> { 116 string FunctionMapper = Fn; 117} 118 119// Check that the machine register operand at position `Index` references 120// register R. This predicate assumes that we already checked that the machine 121// operand at position `Index` is a register operand. 122class CheckRegOperand<int Index, Register R> : CheckOperandBase<Index> { 123 Register Reg = R; 124} 125 126// Check if register operand at index `Index` is the invalid register. 127class CheckInvalidRegOperand<int Index> : CheckOperandBase<Index>; 128 129// Return true if machine operand at position `Index` is a valid 130// register operand. 131class CheckValidRegOperand<int Index> : 132 CheckNot<CheckInvalidRegOperand<Index>>; 133 134// Check that the operand at position `Index` is immediate `Imm`. 135// If field `FunctionMapper` is a non-empty string, then function 136// `FunctionMapper` is applied to the operand value, and the return value is then 137// compared against `Imm`. 138class CheckImmOperand<int Index, int Imm> : CheckOperandBase<Index> { 139 int ImmVal = Imm; 140} 141 142// Similar to CheckImmOperand, however the immediate is not a literal number. 143// This is useful when we want to compare the value of an operand against an 144// enum value, and we know the actual integer value of that enum. 145class CheckImmOperand_s<int Index, string Value> : CheckOperandBase<Index> { 146 string ImmVal = Value; 147} 148 149// Expands to a call to `FunctionMapper` if field `FunctionMapper` is set. 150// Otherwise, it expands to a CheckNot<CheckInvalidRegOperand<Index>>. 151class CheckRegOperandSimple<int Index> : CheckOperandBase<Index>; 152 153// Expands to a call to `FunctionMapper` if field `FunctionMapper` is set. 154// Otherwise, it simply evaluates to TruePred. 155class CheckImmOperandSimple<int Index> : CheckOperandBase<Index>; 156 157// Check that the operand at position `Index` is immediate value zero. 158class CheckZeroOperand<int Index> : CheckImmOperand<Index, 0>; 159 160// Check that the instruction has exactly `Num` operands. 161class CheckNumOperands<int Num> : MCInstPredicate { 162 int NumOps = Num; 163} 164 165// Check that the instruction opcode is one of the opcodes in set `Opcodes`. 166// This is a simple set membership query. The easier way to check if an opcode 167// is not a member of the set is by using a `CheckNot<CheckOpcode<[...]>>` 168// sequence. 169class CheckOpcode<list<Instruction> Opcodes> : MCInstPredicate { 170 list<Instruction> ValidOpcodes = Opcodes; 171} 172 173// Check that the instruction opcode is a pseudo opcode member of the set 174// `Opcodes`. This check is always expanded to "false" if we are generating 175// code for MCInst. 176class CheckPseudo<list<Instruction> Opcodes> : CheckOpcode<Opcodes>; 177 178// A non-portable predicate. Only to use as a last resort when a block of code 179// cannot possibly be converted in a declarative way using other MCInstPredicate 180// classes. This check is always expanded to "false" when generating code for 181// MCInst. 182class CheckNonPortable<string Code> : MCInstPredicate { 183 string CodeBlock = Code; 184} 185 186// A sequence of predicates. It is used as the base class for CheckAll, and 187// CheckAny. It allows to describe compositions of predicates. 188class CheckPredicateSequence<list<MCInstPredicate> Preds> : MCInstPredicate { 189 list<MCInstPredicate> Predicates = Preds; 190} 191 192// Check that all of the predicates in `Preds` evaluate to true. 193class CheckAll<list<MCInstPredicate> Sequence> 194 : CheckPredicateSequence<Sequence>; 195 196// Check that at least one of the predicates in `Preds` evaluates to true. 197class CheckAny<list<MCInstPredicate> Sequence> 198 : CheckPredicateSequence<Sequence>; 199 200 201// Used to expand the body of a function predicate. See the definition of 202// TIIPredicate below. 203class MCStatement; 204 205// Expands to a return statement. The return expression is a boolean expression 206// described by a MCInstPredicate. 207class MCReturnStatement<MCInstPredicate predicate> : MCStatement { 208 MCInstPredicate Pred = predicate; 209} 210 211// Used to automatically construct cases of a switch statement where the switch 212// variable is an instruction opcode. There is a 'case' for every opcode in the 213// `opcodes` list, and each case is associated with MCStatement `caseStmt`. 214class MCOpcodeSwitchCase<list<Instruction> opcodes, MCStatement caseStmt> { 215 list<Instruction> Opcodes = opcodes; 216 MCStatement CaseStmt = caseStmt; 217} 218 219// Expands to a switch statement. The switch variable is an instruction opcode. 220// The auto-generated switch is populated by a number of cases based on the 221// `cases` list in input. A default case is automatically generated, and it 222// evaluates to `default`. 223class MCOpcodeSwitchStatement<list<MCOpcodeSwitchCase> cases, 224 MCStatement default> : MCStatement { 225 list<MCOpcodeSwitchCase> Cases = cases; 226 MCStatement DefaultCase = default; 227} 228 229// Base class for function predicates. 230class FunctionPredicateBase<string name, MCStatement body> { 231 string FunctionName = name; 232 MCStatement Body = body; 233} 234 235// Check that a call to method `Name` in class "XXXInstrInfo" (where XXX is 236// the name of a target) returns true. 237// 238// TIIPredicate definitions are used to model calls to the target-specific 239// InstrInfo. A TIIPredicate is treated specially by the InstrInfoEmitter 240// tablegen backend, which will use it to automatically generate a definition in 241// the target specific `InstrInfo` class. 242// 243// There cannot be multiple TIIPredicate definitions with the same name for the 244// same target. 245class TIIPredicate<string Name, MCStatement body> 246 : FunctionPredicateBase<Name, body>, MCInstPredicate; 247 248// A function predicate that takes as input a machine instruction, and returns 249// a boolean value. 250// 251// This predicate is expanded into a function call by the PredicateExpander. 252// In particular, the PredicateExpander would either expand this predicate into 253// a call to `MCInstFn`, or into a call to`MachineInstrFn` depending on whether 254// it is lowering predicates for MCInst or MachineInstr. 255// 256// In this context, `MCInstFn` and `MachineInstrFn` are both function names. 257class CheckFunctionPredicate<string MCInstFn, string MachineInstrFn> : MCInstPredicate { 258 string MCInstFnName = MCInstFn; 259 string MachineInstrFnName = MachineInstrFn; 260} 261 262// Similar to CheckFunctionPredicate. However it assumes that MachineInstrFn is 263// a method in TargetInstrInfo, and MCInstrFn takes an extra pointer to 264// MCInstrInfo. 265// 266// It Expands to: 267// - TIIPointer->MachineInstrFn(MI) 268// - MCInstrFn(MI, MCII); 269class CheckFunctionPredicateWithTII<string MCInstFn, string MachineInstrFn, string 270TIIPointer = "TII"> : MCInstPredicate { 271 string MCInstFnName = MCInstFn; 272 string TIIPtrName = TIIPointer; 273 string MachineInstrFnName = MachineInstrFn; 274} 275 276// Used to classify machine instructions based on a machine instruction 277// predicate. 278// 279// Let IC be an InstructionEquivalenceClass definition, and MI a machine 280// instruction. We say that MI belongs to the equivalence class described by IC 281// if and only if the following two conditions are met: 282// a) MI's opcode is in the `opcodes` set, and 283// b) `Predicate` evaluates to true when applied to MI. 284// 285// Instances of this class can be used by processor scheduling models to 286// describe instructions that have a property in common. For example, 287// InstructionEquivalenceClass definitions can be used to identify the set of 288// dependency breaking instructions for a processor model. 289// 290// An (optional) list of operand indices can be used to further describe 291// properties that apply to instruction operands. For example, it can be used to 292// identify register uses of a dependency breaking instructions that are not in 293// a RAW dependency. 294class InstructionEquivalenceClass<list<Instruction> opcodes, 295 MCInstPredicate pred, 296 list<int> operands = []> { 297 list<Instruction> Opcodes = opcodes; 298 MCInstPredicate Predicate = pred; 299 list<int> OperandIndices = operands; 300} 301 302// Used by processor models to describe dependency breaking instructions. 303// 304// This is mainly an alias for InstructionEquivalenceClass. Input operand 305// `BrokenDeps` identifies the set of "broken dependencies". There is one bit 306// per each implicit and explicit input operand. An empty set of broken 307// dependencies means: "explicit input register operands are independent." 308class DepBreakingClass<list<Instruction> opcodes, MCInstPredicate pred, 309 list<int> BrokenDeps = []> 310 : InstructionEquivalenceClass<opcodes, pred, BrokenDeps>; 311 312// A function descriptor used to describe the signature of a predicate methods 313// which will be expanded by the STIPredicateExpander into a tablegen'd 314// XXXGenSubtargetInfo class member definition (here, XXX is a target name). 315// 316// It describes the signature of a TargetSubtarget hook, as well as a few extra 317// properties. Examples of extra properties are: 318// - The default return value for the auto-generate function hook. 319// - A list of subtarget hooks (Delegates) that are called from this function. 320// 321class STIPredicateDecl<string name, MCInstPredicate default = FalsePred, 322 bit overrides = true, bit expandForMC = true, 323 bit updatesOpcodeMask = false, 324 list<STIPredicateDecl> delegates = []> { 325 string Name = name; 326 327 MCInstPredicate DefaultReturnValue = default; 328 329 // True if this method is declared as virtual in class TargetSubtargetInfo. 330 bit OverridesBaseClassMember = overrides; 331 332 // True if we need an equivalent predicate function in the MC layer. 333 bit ExpandForMC = expandForMC; 334 335 // True if the autogenerated method has a extra in/out APInt param used as a 336 // mask of operands. 337 bit UpdatesOpcodeMask = updatesOpcodeMask; 338 339 // A list of STIPredicates used by this definition to delegate part of the 340 // computation. For example, STIPredicateFunction `isDependencyBreaking()` 341 // delegates to `isZeroIdiom()` part of its computation. 342 list<STIPredicateDecl> Delegates = delegates; 343} 344 345// A predicate function definition member of class `XXXGenSubtargetInfo`. 346// 347// If `Declaration.ExpandForMC` is true, then SubtargetEmitter 348// will also expand another definition of this method that accepts a MCInst. 349class STIPredicate<STIPredicateDecl declaration, 350 list<InstructionEquivalenceClass> classes> { 351 STIPredicateDecl Declaration = declaration; 352 list<InstructionEquivalenceClass> Classes = classes; 353 SchedMachineModel SchedModel = ?; 354} 355 356// Convenience classes and definitions used by processor scheduling models to 357// describe dependency breaking instructions and move elimination candidates. 358let UpdatesOpcodeMask = true in { 359 360def IsZeroIdiomDecl : STIPredicateDecl<"isZeroIdiom">; 361 362let Delegates = [IsZeroIdiomDecl] in 363def IsDepBreakingDecl : STIPredicateDecl<"isDependencyBreaking">; 364 365} // UpdatesOpcodeMask 366 367def IsOptimizableRegisterMoveDecl 368 : STIPredicateDecl<"isOptimizableRegisterMove">; 369 370class IsZeroIdiomFunction<list<DepBreakingClass> classes> 371 : STIPredicate<IsZeroIdiomDecl, classes>; 372 373class IsDepBreakingFunction<list<DepBreakingClass> classes> 374 : STIPredicate<IsDepBreakingDecl, classes>; 375 376class IsOptimizableRegisterMove<list<InstructionEquivalenceClass> classes> 377 : STIPredicate<IsOptimizableRegisterMoveDecl, classes>; 378