10b57cec5SDimitry Andric//===- TargetItinerary.td - Target Itinerary Description --*- tablegen -*-====// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file defines the target-independent scheduling interfaces 100b57cec5SDimitry Andric// which should be implemented by each target that uses instruction 110b57cec5SDimitry Andric// itineraries for scheduling. Itineraries are detailed reservation 120b57cec5SDimitry Andric// tables for each instruction class. They are most appropriate for 130b57cec5SDimitry Andric// in-order machine with complicated scheduling or bundling constraints. 140b57cec5SDimitry Andric// 150b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 180b57cec5SDimitry Andric// Processor functional unit - These values represent the function units 190b57cec5SDimitry Andric// available across all chip sets for the target. Eg., IntUnit, FPUnit, ... 200b57cec5SDimitry Andric// These may be independent values for each chip set or may be shared across 210b57cec5SDimitry Andric// all chip sets of the target. Each functional unit is treated as a resource 220b57cec5SDimitry Andric// during scheduling and has an affect instruction order based on availability 230b57cec5SDimitry Andric// during a time interval. 240b57cec5SDimitry Andric// 250b57cec5SDimitry Andricclass FuncUnit; 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 280b57cec5SDimitry Andric// Pipeline bypass / forwarding - These values specifies the symbolic names of 290b57cec5SDimitry Andric// pipeline bypasses which can be used to forward results of instructions 300b57cec5SDimitry Andric// that are forwarded to uses. 310b57cec5SDimitry Andricclass Bypass; 320b57cec5SDimitry Andricdef NoBypass : Bypass; 330b57cec5SDimitry Andric 340b57cec5SDimitry Andricclass ReservationKind<bits<1> val> { 350b57cec5SDimitry Andric int Value = val; 360b57cec5SDimitry Andric} 370b57cec5SDimitry Andric 380b57cec5SDimitry Andricdef Required : ReservationKind<0>; 390b57cec5SDimitry Andricdef Reserved : ReservationKind<1>; 400b57cec5SDimitry Andric 410b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 420b57cec5SDimitry Andric// Instruction stage - These values represent a non-pipelined step in 430b57cec5SDimitry Andric// the execution of an instruction. Cycles represents the number of 440b57cec5SDimitry Andric// discrete time slots needed to complete the stage. Units represent 450b57cec5SDimitry Andric// the choice of functional units that can be used to complete the 460b57cec5SDimitry Andric// stage. Eg. IntUnit1, IntUnit2. TimeInc indicates how many cycles 470b57cec5SDimitry Andric// should elapse from the start of this stage to the start of the next 480b57cec5SDimitry Andric// stage in the itinerary. For example: 490b57cec5SDimitry Andric// 500b57cec5SDimitry Andric// A stage is specified in one of two ways: 510b57cec5SDimitry Andric// 520b57cec5SDimitry Andric// InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles 530b57cec5SDimitry Andric// InstrStage<1, [FU_x, FU_y], 0> - TimeInc explicit 540b57cec5SDimitry Andric// 550b57cec5SDimitry Andric 560b57cec5SDimitry Andricclass InstrStage<int cycles, list<FuncUnit> units, 570b57cec5SDimitry Andric int timeinc = -1, 580b57cec5SDimitry Andric ReservationKind kind = Required> { 590b57cec5SDimitry Andric int Cycles = cycles; // length of stage in machine cycles 600b57cec5SDimitry Andric list<FuncUnit> Units = units; // choice of functional units 610b57cec5SDimitry Andric int TimeInc = timeinc; // cycles till start of next stage 620b57cec5SDimitry Andric int Kind = kind.Value; // kind of FU reservation 630b57cec5SDimitry Andric} 640b57cec5SDimitry Andric 650b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 660b57cec5SDimitry Andric// Instruction itinerary - An itinerary represents a sequential series of steps 670b57cec5SDimitry Andric// required to complete an instruction. Itineraries are represented as lists of 680b57cec5SDimitry Andric// instruction stages. 690b57cec5SDimitry Andric// 700b57cec5SDimitry Andric 710b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 720b57cec5SDimitry Andric// Instruction itinerary classes - These values represent 'named' instruction 730b57cec5SDimitry Andric// itinerary. Using named itineraries simplifies managing groups of 740b57cec5SDimitry Andric// instructions across chip sets. An instruction uses the same itinerary class 750b57cec5SDimitry Andric// across all chip sets. Thus a new chip set can be added without modifying 760b57cec5SDimitry Andric// instruction information. 770b57cec5SDimitry Andric// 780b57cec5SDimitry Andricclass InstrItinClass; 790b57cec5SDimitry Andricdef NoItinerary : InstrItinClass; 800b57cec5SDimitry Andric 810b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 820b57cec5SDimitry Andric// Instruction itinerary data - These values provide a runtime map of an 830b57cec5SDimitry Andric// instruction itinerary class (name) to its itinerary data. 840b57cec5SDimitry Andric// 850b57cec5SDimitry Andric// NumMicroOps represents the number of micro-operations that each instruction 860b57cec5SDimitry Andric// in the class are decoded to. If the number is zero, then it means the 870b57cec5SDimitry Andric// instruction can decode into variable number of micro-ops and it must be 880b57cec5SDimitry Andric// determined dynamically. This directly relates to the itineraries 890b57cec5SDimitry Andric// global IssueWidth property, which constrains the number of microops 900b57cec5SDimitry Andric// that can issue per cycle. 910b57cec5SDimitry Andric// 920b57cec5SDimitry Andric// OperandCycles are optional "cycle counts". They specify the cycle after 930b57cec5SDimitry Andric// instruction issue the values which correspond to specific operand indices 940b57cec5SDimitry Andric// are defined or read. Bypasses are optional "pipeline forwarding paths", if 950b57cec5SDimitry Andric// a def by an instruction is available on a specific bypass and the use can 960b57cec5SDimitry Andric// read from the same bypass, then the operand use latency is reduced by one. 970b57cec5SDimitry Andric// 980b57cec5SDimitry Andric// InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>, 990b57cec5SDimitry Andric// InstrStage<1, [A9_AGU]>], 1000b57cec5SDimitry Andric// [3, 1], [A9_LdBypass]>, 1010b57cec5SDimitry Andric// InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], 1020b57cec5SDimitry Andric// [1, 1], [NoBypass, A9_LdBypass]>, 1030b57cec5SDimitry Andric// 1040b57cec5SDimitry Andric// In this example, the instruction of IIC_iLoadi reads its input on cycle 1 1050b57cec5SDimitry Andric// (after issue) and the result of the load is available on cycle 3. The result 1060b57cec5SDimitry Andric// is available via forwarding path A9_LdBypass. If it's used by the first 1070b57cec5SDimitry Andric// source operand of instructions of IIC_iMVNr class, then the operand latency 1080b57cec5SDimitry Andric// is reduced by 1. 1090b57cec5SDimitry Andricclass InstrItinData<InstrItinClass Class, list<InstrStage> stages, 1100b57cec5SDimitry Andric list<int> operandcycles = [], 1110b57cec5SDimitry Andric list<Bypass> bypasses = [], int uops = 1> { 1120b57cec5SDimitry Andric InstrItinClass TheClass = Class; 1130b57cec5SDimitry Andric int NumMicroOps = uops; 1140b57cec5SDimitry Andric list<InstrStage> Stages = stages; 1150b57cec5SDimitry Andric list<int> OperandCycles = operandcycles; 1160b57cec5SDimitry Andric list<Bypass> Bypasses = bypasses; 1170b57cec5SDimitry Andric} 1180b57cec5SDimitry Andric 1190b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 1200b57cec5SDimitry Andric// Processor itineraries - These values represent the set of all itinerary 1210b57cec5SDimitry Andric// classes for a given chip set. 1220b57cec5SDimitry Andric// 1230b57cec5SDimitry Andric// Set property values to -1 to use the default. 1240b57cec5SDimitry Andric// See InstrItineraryProps for comments and defaults. 1250b57cec5SDimitry Andricclass ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp, 1260b57cec5SDimitry Andric list<InstrItinData> iid> { 1270b57cec5SDimitry Andric list<FuncUnit> FU = fu; 1280b57cec5SDimitry Andric list<Bypass> BP = bp; 1290b57cec5SDimitry Andric list<InstrItinData> IID = iid; 1300b57cec5SDimitry Andric // The packetizer automaton to use for this itinerary. By default all 1310b57cec5SDimitry Andric // itineraries for a target are bundled up into the same automaton. This only 1320b57cec5SDimitry Andric // works correctly when there are no conflicts in functional unit IDs between 1330b57cec5SDimitry Andric // itineraries. For example, given two itineraries A<[SLOT_A]>, B<[SLOT_B]>, 1340b57cec5SDimitry Andric // SLOT_A and SLOT_B will be assigned the same functional unit index, and 1350b57cec5SDimitry Andric // the generated packetizer will confuse instructions referencing these slots. 1360b57cec5SDimitry Andric // 1370b57cec5SDimitry Andric // To avoid this, setting PacketizerNamespace to non-"" will cause this 1380b57cec5SDimitry Andric // itinerary to be generated in a different automaton. The subtarget will need 1390b57cec5SDimitry Andric // to declare a method "create##Namespace##DFAPacketizer()". 1400b57cec5SDimitry Andric string PacketizerNamespace = ""; 1410b57cec5SDimitry Andric} 1420b57cec5SDimitry Andric 1430b57cec5SDimitry Andric// NoItineraries - A marker that can be used by processors without schedule 1440b57cec5SDimitry Andric// info. Subtargets using NoItineraries can bypass the scheduler's 1450b57cec5SDimitry Andric// expensive HazardRecognizer because no reservation table is needed. 1460b57cec5SDimitry Andricdef NoItineraries : ProcessorItineraries<[], [], []>; 1470b57cec5SDimitry Andric 1480b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 1490b57cec5SDimitry Andric// Combo Function Unit data - This is a map of combo function unit names to 1500b57cec5SDimitry Andric// the list of functional units that are included in the combination. 1510b57cec5SDimitry Andric// 152class ComboFuncData<FuncUnit ComboFunc, list<FuncUnit> funclist> { 153 FuncUnit TheComboFunc = ComboFunc; 154 list<FuncUnit> FuncList = funclist; 155} 156 157//===----------------------------------------------------------------------===// 158// Combo Function Units - This is a list of all combo function unit data. 159class ComboFuncUnits<list<ComboFuncData> cfd> { 160 list<ComboFuncData> CFD = cfd; 161} 162 163