1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise ARM hardware features
10 // such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_TARGETPARSER_ARMTARGETPARSER_H
15 #define LLVM_TARGETPARSER_ARMTARGETPARSER_H
16 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/Support/ARMBuildAttributes.h"
19 #include "llvm/TargetParser/ARMTargetParserCommon.h"
20 #include <vector>
21 
22 namespace llvm {
23 
24 class Triple;
25 
26 namespace ARM {
27 
28 // Arch extension modifiers for CPUs.
29 // Note that this is not the same as the AArch64 list
30 enum ArchExtKind : uint64_t {
31   AEK_INVALID =     0,
32   AEK_NONE =        1,
33   AEK_CRC =         1 << 1,
34   AEK_CRYPTO =      1 << 2,
35   AEK_FP =          1 << 3,
36   AEK_HWDIVTHUMB =  1 << 4,
37   AEK_HWDIVARM =    1 << 5,
38   AEK_MP =          1 << 6,
39   AEK_SIMD =        1 << 7,
40   AEK_SEC =         1 << 8,
41   AEK_VIRT =        1 << 9,
42   AEK_DSP =         1 << 10,
43   AEK_FP16 =        1 << 11,
44   AEK_RAS =         1 << 12,
45   AEK_DOTPROD =     1 << 13,
46   AEK_SHA2    =     1 << 14,
47   AEK_AES     =     1 << 15,
48   AEK_FP16FML =     1 << 16,
49   AEK_SB      =     1 << 17,
50   AEK_FP_DP   =     1 << 18,
51   AEK_LOB     =     1 << 19,
52   AEK_BF16    =     1 << 20,
53   AEK_I8MM    =     1 << 21,
54   AEK_CDECP0 =      1 << 22,
55   AEK_CDECP1 =      1 << 23,
56   AEK_CDECP2 =      1 << 24,
57   AEK_CDECP3 =      1 << 25,
58   AEK_CDECP4 =      1 << 26,
59   AEK_CDECP5 =      1 << 27,
60   AEK_CDECP6 =      1 << 28,
61   AEK_CDECP7 =      1 << 29,
62   AEK_PACBTI =      1 << 30,
63   // Unsupported extensions.
64   AEK_OS       =    1ULL << 59,
65   AEK_IWMMXT   =    1ULL << 60,
66   AEK_IWMMXT2  =    1ULL << 61,
67   AEK_MAVERICK =    1ULL << 62,
68   AEK_XSCALE   =    1ULL << 63,
69 };
70 
71 // List of Arch Extension names.
72 struct ExtName {
73   StringRef Name;
74   uint64_t ID;
75   StringRef Feature;
76   StringRef NegFeature;
77 };
78 
79 const ExtName ARCHExtNames[] = {
80 #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)                       \
81   {NAME, ID, FEATURE, NEGFEATURE},
82 #include "ARMTargetParser.def"
83 };
84 
85 // List of HWDiv names (use getHWDivSynonym) and which architectural
86 // features they correspond to (use getHWDivFeatures).
87 const struct {
88   StringRef Name;
89   uint64_t ID;
90 } HWDivNames[] = {
91 #define ARM_HW_DIV_NAME(NAME, ID) {NAME, ID},
92 #include "ARMTargetParser.def"
93 };
94 
95 // Arch names.
96 enum class ArchKind {
97 #define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU,        \
98                  ARCH_BASE_EXT)                                                \
99   ID,
100 #include "ARMTargetParser.def"
101 };
102 
103 // List of CPU names and their arches.
104 // The same CPU can have multiple arches and can be default on multiple arches.
105 // When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
106 // When this becomes table-generated, we'd probably need two tables.
107 struct CpuNames {
108   StringRef Name;
109   ArchKind ArchID;
110   bool Default; // is $Name the default CPU for $ArchID ?
111   uint64_t DefaultExtensions;
112 };
113 
114 const CpuNames CPUNames[] = {
115 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)           \
116   {NAME, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
117 #include "ARMTargetParser.def"
118 };
119 
120 // FPU names.
121 enum FPUKind {
122 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,
123 #include "ARMTargetParser.def"
124   FK_LAST
125 };
126 
127 // FPU Version
128 enum class FPUVersion {
129   NONE,
130   VFPV2,
131   VFPV3,
132   VFPV3_FP16,
133   VFPV4,
134   VFPV5,
135   VFPV5_FULLFP16,
136 };
137 
138 // An FPU name restricts the FPU in one of three ways:
139 enum class FPURestriction {
140   None = 0, ///< No restriction
141   D16,      ///< Only 16 D registers
142   SP_D16    ///< Only single-precision instructions, with 16 D registers
143 };
144 
145 // An FPU name implies one of three levels of Neon support:
146 enum class NeonSupportLevel {
147   None = 0, ///< No Neon
148   Neon,     ///< Neon
149   Crypto    ///< Neon with Crypto
150 };
151 
152 // v6/v7/v8 Profile
153 enum class ProfileKind { INVALID = 0, A, R, M };
154 
155 // List of canonical FPU names (use getFPUSynonym) and which architectural
156 // features they correspond to (use getFPUFeatures).
157 // The entries must appear in the order listed in ARM::FPUKind for correct
158 // indexing
159 struct FPUName {
160   StringRef Name;
161   FPUKind ID;
162   FPUVersion FPUVer;
163   NeonSupportLevel NeonSupport;
164   FPURestriction Restriction;
165 };
166 
167 static const FPUName FPUNames[] = {
168 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION)                \
169   {NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION},
170 #include "llvm/TargetParser/ARMTargetParser.def"
171 };
172 
173 // List of canonical arch names (use getArchSynonym).
174 // This table also provides the build attribute fields for CPU arch
175 // and Arch ID, according to the Addenda to the ARM ABI, chapters
176 // 2.4 and 2.3.5.2 respectively.
177 // FIXME: SubArch values were simplified to fit into the expectations
178 // of the triples and are not conforming with their official names.
179 // Check to see if the expectation should be changed.
180 struct ArchNames {
181   StringRef Name;
182   StringRef CPUAttr; // CPU class in build attributes.
183   StringRef ArchFeature;
184   FPUKind DefaultFPU;
185   uint64_t ArchBaseExtensions;
186   ArchKind ID;
187   ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
188 
189   // Return ArchFeature without the leading "+".
190   StringRef getSubArch() const { return ArchFeature.substr(1); }
191 };
192 
193 static const ArchNames ARMArchNames[] = {
194 #define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU,        \
195                  ARCH_BASE_EXT)                                                \
196   {NAME,          CPU_ATTR,     ARCH_FEATURE, ARCH_FPU,                        \
197    ARCH_BASE_EXT, ArchKind::ID, ARCH_ATTR},
198 #include "llvm/TargetParser/ARMTargetParser.def"
199 };
200 
201 inline ArchKind &operator--(ArchKind &Kind) {
202   assert((Kind >= ArchKind::ARMV8A && Kind <= ArchKind::ARMV9_3A) &&
203          "We only expect operator-- to be called with ARMV8/V9");
204   if (Kind == ArchKind::INVALID || Kind == ArchKind::ARMV8A ||
205       Kind == ArchKind::ARMV8_1A || Kind == ArchKind::ARMV9A ||
206       Kind == ArchKind::ARMV8R)
207     Kind = ArchKind::INVALID;
208   else {
209     unsigned KindAsInteger = static_cast<unsigned>(Kind);
210     Kind = static_cast<ArchKind>(--KindAsInteger);
211   }
212   return Kind;
213 }
214 
215 // Information by ID
216 StringRef getFPUName(FPUKind FPUKind);
217 FPUVersion getFPUVersion(FPUKind FPUKind);
218 NeonSupportLevel getFPUNeonSupportLevel(FPUKind FPUKind);
219 FPURestriction getFPURestriction(FPUKind FPUKind);
220 
221 bool getFPUFeatures(FPUKind FPUKind, std::vector<StringRef> &Features);
222 bool getHWDivFeatures(uint64_t HWDivKind, std::vector<StringRef> &Features);
223 bool getExtensionFeatures(uint64_t Extensions,
224                           std::vector<StringRef> &Features);
225 
226 StringRef getArchName(ArchKind AK);
227 unsigned getArchAttr(ArchKind AK);
228 StringRef getCPUAttr(ArchKind AK);
229 StringRef getSubArch(ArchKind AK);
230 StringRef getArchExtName(uint64_t ArchExtKind);
231 StringRef getArchExtFeature(StringRef ArchExt);
232 bool appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK, StringRef ArchExt,
233                            std::vector<StringRef> &Features,
234                            FPUKind &ArgFPUKind);
235 ArchKind convertV9toV8(ArchKind AK);
236 
237 // Information by Name
238 FPUKind getDefaultFPU(StringRef CPU, ArchKind AK);
239 uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK);
240 StringRef getDefaultCPU(StringRef Arch);
241 StringRef getCanonicalArchName(StringRef Arch);
242 StringRef getFPUSynonym(StringRef FPU);
243 
244 // Parser
245 uint64_t parseHWDiv(StringRef HWDiv);
246 FPUKind parseFPU(StringRef FPU);
247 ArchKind parseArch(StringRef Arch);
248 uint64_t parseArchExt(StringRef ArchExt);
249 ArchKind parseCPUArch(StringRef CPU);
250 ProfileKind parseArchProfile(StringRef Arch);
251 unsigned parseArchVersion(StringRef Arch);
252 
253 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
254 StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
255 
256 /// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
257 ///
258 /// \param Arch the architecture name (e.g., "armv7s"). If it is an empty
259 /// string then the triple's arch name is used.
260 StringRef getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch = {});
261 
262 } // namespace ARM
263 } // namespace llvm
264 
265 #endif
266