1 //===-- RISCVTargetParser - Parser for target features ----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise hardware features 10 // for RISC-V CPUs. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGETPARSER_RISCVTARGETPARSER_H 15 #define LLVM_TARGETPARSER_RISCVTARGETPARSER_H 16 17 #include "llvm/ADT/StringRef.h" 18 19 namespace llvm { 20 21 class Triple; 22 23 namespace RISCV { 24 25 // We use 64 bits as the known part in the scalable vector types. 26 static constexpr unsigned RVVBitsPerBlock = 64; 27 28 bool parseCPU(StringRef CPU, bool IsRV64); 29 bool parseTuneCPU(StringRef CPU, bool IsRV64); 30 StringRef getMArchFromMcpu(StringRef CPU); 31 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64); 32 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64); 33 bool hasFastUnalignedAccess(StringRef CPU); 34 35 } // namespace RISCV 36 } // namespace llvm 37 38 #endif 39