1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains support for writing dwarf debug info into asm files.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "DwarfExpression.h"
14 #include "DwarfCompileUnit.h"
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/BinaryFormat/Dwarf.h"
18 #include "llvm/CodeGen/Register.h"
19 #include "llvm/CodeGen/TargetRegisterInfo.h"
20 #include "llvm/IR/DebugInfoMetadata.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include <algorithm>
23 #include <cassert>
24 #include <cstdint>
25 
26 using namespace llvm;
27 
28 void DwarfExpression::emitConstu(uint64_t Value) {
29   if (Value < 32)
30     emitOp(dwarf::DW_OP_lit0 + Value);
31   else if (Value == std::numeric_limits<uint64_t>::max()) {
32     // Only do this for 64-bit values as the DWARF expression stack uses
33     // target-address-size values.
34     emitOp(dwarf::DW_OP_lit0);
35     emitOp(dwarf::DW_OP_not);
36   } else {
37     emitOp(dwarf::DW_OP_constu);
38     emitUnsigned(Value);
39   }
40 }
41 
42 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
43  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
44  assert((isUnknownLocation() || isRegisterLocation()) &&
45         "location description already locked down");
46  LocationKind = Register;
47  if (DwarfReg < 32) {
48    emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
49   } else {
50     emitOp(dwarf::DW_OP_regx, Comment);
51     emitUnsigned(DwarfReg);
52   }
53 }
54 
55 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
56   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
57   assert(!isRegisterLocation() && "location description already locked down");
58   if (DwarfReg < 32) {
59     emitOp(dwarf::DW_OP_breg0 + DwarfReg);
60   } else {
61     emitOp(dwarf::DW_OP_bregx);
62     emitUnsigned(DwarfReg);
63   }
64   emitSigned(Offset);
65 }
66 
67 void DwarfExpression::addFBReg(int Offset) {
68   emitOp(dwarf::DW_OP_fbreg);
69   emitSigned(Offset);
70 }
71 
72 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
73   if (!SizeInBits)
74     return;
75 
76   const unsigned SizeOfByte = 8;
77   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
78     emitOp(dwarf::DW_OP_bit_piece);
79     emitUnsigned(SizeInBits);
80     emitUnsigned(OffsetInBits);
81   } else {
82     emitOp(dwarf::DW_OP_piece);
83     unsigned ByteSize = SizeInBits / SizeOfByte;
84     emitUnsigned(ByteSize);
85   }
86   this->OffsetInBits += SizeInBits;
87 }
88 
89 void DwarfExpression::addShr(unsigned ShiftBy) {
90   emitConstu(ShiftBy);
91   emitOp(dwarf::DW_OP_shr);
92 }
93 
94 void DwarfExpression::addAnd(unsigned Mask) {
95   emitConstu(Mask);
96   emitOp(dwarf::DW_OP_and);
97 }
98 
99 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
100                                     unsigned MachineReg, unsigned MaxSize) {
101   if (!llvm::Register::isPhysicalRegister(MachineReg)) {
102     if (isFrameRegister(TRI, MachineReg)) {
103       DwarfRegs.push_back({-1, 0, nullptr});
104       return true;
105     }
106     return false;
107   }
108 
109   int Reg = TRI.getDwarfRegNum(MachineReg, false);
110 
111   // If this is a valid register number, emit it.
112   if (Reg >= 0) {
113     DwarfRegs.push_back({Reg, 0, nullptr});
114     return true;
115   }
116 
117   // Walk up the super-register chain until we find a valid number.
118   // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
119   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
120     Reg = TRI.getDwarfRegNum(*SR, false);
121     if (Reg >= 0) {
122       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
123       unsigned Size = TRI.getSubRegIdxSize(Idx);
124       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
125       DwarfRegs.push_back({Reg, 0, "super-register"});
126       // Use a DW_OP_bit_piece to describe the sub-register.
127       setSubRegisterPiece(Size, RegOffset);
128       return true;
129     }
130   }
131 
132   // Otherwise, attempt to find a covering set of sub-register numbers.
133   // For example, Q0 on ARM is a composition of D0+D1.
134   unsigned CurPos = 0;
135   // The size of the register in bits.
136   const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
137   unsigned RegSize = TRI.getRegSizeInBits(*RC);
138   // Keep track of the bits in the register we already emitted, so we
139   // can avoid emitting redundant aliasing subregs. Because this is
140   // just doing a greedy scan of all subregisters, it is possible that
141   // this doesn't find a combination of subregisters that fully cover
142   // the register (even though one may exist).
143   SmallBitVector Coverage(RegSize, false);
144   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
145     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
146     unsigned Size = TRI.getSubRegIdxSize(Idx);
147     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
148     Reg = TRI.getDwarfRegNum(*SR, false);
149     if (Reg < 0)
150       continue;
151 
152     // Intersection between the bits we already emitted and the bits
153     // covered by this subregister.
154     SmallBitVector CurSubReg(RegSize, false);
155     CurSubReg.set(Offset, Offset + Size);
156 
157     // If this sub-register has a DWARF number and we haven't covered
158     // its range, and its range covers the value, emit a DWARF piece for it.
159     if (Offset < MaxSize && CurSubReg.test(Coverage)) {
160       // Emit a piece for any gap in the coverage.
161       if (Offset > CurPos)
162         DwarfRegs.push_back(
163             {-1, Offset - CurPos, "no DWARF register encoding"});
164       DwarfRegs.push_back(
165           {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
166     }
167     // Mark it as emitted.
168     Coverage.set(Offset, Offset + Size);
169     CurPos = Offset + Size;
170   }
171   // Failed to find any DWARF encoding.
172   if (CurPos == 0)
173     return false;
174   // Found a partial or complete DWARF encoding.
175   if (CurPos < RegSize)
176     DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
177   return true;
178 }
179 
180 void DwarfExpression::addStackValue() {
181   if (DwarfVersion >= 4)
182     emitOp(dwarf::DW_OP_stack_value);
183 }
184 
185 void DwarfExpression::addSignedConstant(int64_t Value) {
186   assert(isImplicitLocation() || isUnknownLocation());
187   LocationKind = Implicit;
188   emitOp(dwarf::DW_OP_consts);
189   emitSigned(Value);
190 }
191 
192 void DwarfExpression::addUnsignedConstant(uint64_t Value) {
193   assert(isImplicitLocation() || isUnknownLocation());
194   LocationKind = Implicit;
195   emitConstu(Value);
196 }
197 
198 void DwarfExpression::addUnsignedConstant(const APInt &Value) {
199   assert(isImplicitLocation() || isUnknownLocation());
200   LocationKind = Implicit;
201 
202   unsigned Size = Value.getBitWidth();
203   const uint64_t *Data = Value.getRawData();
204 
205   // Chop it up into 64-bit pieces, because that's the maximum that
206   // addUnsignedConstant takes.
207   unsigned Offset = 0;
208   while (Offset < Size) {
209     addUnsignedConstant(*Data++);
210     if (Offset == 0 && Size <= 64)
211       break;
212     addStackValue();
213     addOpPiece(std::min(Size - Offset, 64u), Offset);
214     Offset += 64;
215   }
216 }
217 
218 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
219                                               DIExpressionCursor &ExprCursor,
220                                               unsigned MachineReg,
221                                               unsigned FragmentOffsetInBits) {
222   auto Fragment = ExprCursor.getFragmentInfo();
223   if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
224     LocationKind = Unknown;
225     return false;
226   }
227 
228   bool HasComplexExpression = false;
229   auto Op = ExprCursor.peek();
230   if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
231     HasComplexExpression = true;
232 
233   // If the register can only be described by a complex expression (i.e.,
234   // multiple subregisters) it doesn't safely compose with another complex
235   // expression. For example, it is not possible to apply a DW_OP_deref
236   // operation to multiple DW_OP_pieces.
237   if (HasComplexExpression && DwarfRegs.size() > 1) {
238     DwarfRegs.clear();
239     LocationKind = Unknown;
240     return false;
241   }
242 
243   // Handle simple register locations. If we are supposed to emit
244   // a call site parameter expression and if that expression is just a register
245   // location, emit it with addBReg and offset 0, because we should emit a DWARF
246   // expression representing a value, rather than a location.
247   if (!isMemoryLocation() && !HasComplexExpression && (!isParameterValue() ||
248                                                        isEntryValue())) {
249     for (auto &Reg : DwarfRegs) {
250       if (Reg.DwarfRegNo >= 0)
251         addReg(Reg.DwarfRegNo, Reg.Comment);
252       addOpPiece(Reg.Size);
253     }
254 
255     if (isEntryValue())
256       finalizeEntryValue();
257 
258     if (isEntryValue() && !isParameterValue() && DwarfVersion >= 4)
259       emitOp(dwarf::DW_OP_stack_value);
260 
261     DwarfRegs.clear();
262     return true;
263   }
264 
265   // Don't emit locations that cannot be expressed without DW_OP_stack_value.
266   if (DwarfVersion < 4)
267     if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
268           return Op.getOp() == dwarf::DW_OP_stack_value;
269         })) {
270       DwarfRegs.clear();
271       LocationKind = Unknown;
272       return false;
273     }
274 
275   assert(DwarfRegs.size() == 1);
276   auto Reg = DwarfRegs[0];
277   bool FBReg = isFrameRegister(TRI, MachineReg);
278   int SignedOffset = 0;
279   assert(Reg.Size == 0 && "subregister has same size as superregister");
280 
281   // Pattern-match combinations for which more efficient representations exist.
282   // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
283   if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
284     uint64_t Offset = Op->getArg(0);
285     uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
286     if (Offset <= IntMax) {
287       SignedOffset = Offset;
288       ExprCursor.take();
289     }
290   }
291 
292   // [Reg, DW_OP_constu, Offset, DW_OP_plus]  --> [DW_OP_breg, Offset]
293   // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
294   // If Reg is a subregister we need to mask it out before subtracting.
295   if (Op && Op->getOp() == dwarf::DW_OP_constu) {
296     uint64_t Offset = Op->getArg(0);
297     uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
298     auto N = ExprCursor.peekNext();
299     if (N && N->getOp() == dwarf::DW_OP_plus && Offset <= IntMax) {
300       SignedOffset = Offset;
301       ExprCursor.consume(2);
302     } else if (N && N->getOp() == dwarf::DW_OP_minus &&
303                !SubRegisterSizeInBits && Offset <= IntMax + 1) {
304       SignedOffset = -static_cast<int64_t>(Offset);
305       ExprCursor.consume(2);
306     }
307   }
308 
309   if (FBReg)
310     addFBReg(SignedOffset);
311   else
312     addBReg(Reg.DwarfRegNo, SignedOffset);
313   DwarfRegs.clear();
314   return true;
315 }
316 
317 void DwarfExpression::beginEntryValueExpression(
318     DIExpressionCursor &ExprCursor) {
319   auto Op = ExprCursor.take();
320   (void)Op;
321   assert(Op && Op->getOp() == dwarf::DW_OP_LLVM_entry_value);
322   assert(!isMemoryLocation() &&
323          "We don't support entry values of memory locations yet");
324   assert(!IsEmittingEntryValue && "Already emitting entry value?");
325   assert(Op->getArg(0) == 1 &&
326          "Can currently only emit entry values covering a single operation");
327 
328   emitOp(CU.getDwarf5OrGNULocationAtom(dwarf::DW_OP_entry_value));
329   IsEmittingEntryValue = true;
330   enableTemporaryBuffer();
331 }
332 
333 void DwarfExpression::finalizeEntryValue() {
334   assert(IsEmittingEntryValue && "Entry value not open?");
335   disableTemporaryBuffer();
336 
337   // Emit the entry value's size operand.
338   unsigned Size = getTemporaryBufferSize();
339   emitUnsigned(Size);
340 
341   // Emit the entry value's DWARF block operand.
342   commitTemporaryBuffer();
343 
344   IsEmittingEntryValue = false;
345 }
346 
347 /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
348 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
349   while (ExprCursor) {
350     auto Op = ExprCursor.take();
351     switch (Op->getOp()) {
352     case dwarf::DW_OP_deref:
353     case dwarf::DW_OP_LLVM_fragment:
354       break;
355     default:
356       return false;
357     }
358   }
359   return true;
360 }
361 
362 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
363                                     unsigned FragmentOffsetInBits) {
364   // If we need to mask out a subregister, do it now, unless the next
365   // operation would emit an OpPiece anyway.
366   auto N = ExprCursor.peek();
367   if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
368     maskSubRegister();
369 
370   Optional<DIExpression::ExprOperand> PrevConvertOp = None;
371 
372   while (ExprCursor) {
373     auto Op = ExprCursor.take();
374     uint64_t OpNum = Op->getOp();
375 
376     if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
377       emitOp(OpNum);
378       continue;
379     } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
380       addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
381       continue;
382     }
383 
384     switch (OpNum) {
385     case dwarf::DW_OP_LLVM_fragment: {
386       unsigned SizeInBits = Op->getArg(1);
387       unsigned FragmentOffset = Op->getArg(0);
388       // The fragment offset must have already been adjusted by emitting an
389       // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
390       // location.
391       assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
392       assert(SizeInBits >= OffsetInBits - FragmentOffset && "size underflow");
393 
394       // If addMachineReg already emitted DW_OP_piece operations to represent
395       // a super-register by splicing together sub-registers, subtract the size
396       // of the pieces that was already emitted.
397       SizeInBits -= OffsetInBits - FragmentOffset;
398 
399       // If addMachineReg requested a DW_OP_bit_piece to stencil out a
400       // sub-register that is smaller than the current fragment's size, use it.
401       if (SubRegisterSizeInBits)
402         SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
403 
404       // Emit a DW_OP_stack_value for implicit location descriptions.
405       if (isImplicitLocation())
406         addStackValue();
407 
408       // Emit the DW_OP_piece.
409       addOpPiece(SizeInBits, SubRegisterOffsetInBits);
410       setSubRegisterPiece(0, 0);
411       // Reset the location description kind.
412       LocationKind = Unknown;
413       return;
414     }
415     case dwarf::DW_OP_plus_uconst:
416       assert(!isRegisterLocation());
417       emitOp(dwarf::DW_OP_plus_uconst);
418       emitUnsigned(Op->getArg(0));
419       break;
420     case dwarf::DW_OP_plus:
421     case dwarf::DW_OP_minus:
422     case dwarf::DW_OP_mul:
423     case dwarf::DW_OP_div:
424     case dwarf::DW_OP_mod:
425     case dwarf::DW_OP_or:
426     case dwarf::DW_OP_and:
427     case dwarf::DW_OP_xor:
428     case dwarf::DW_OP_shl:
429     case dwarf::DW_OP_shr:
430     case dwarf::DW_OP_shra:
431     case dwarf::DW_OP_lit0:
432     case dwarf::DW_OP_not:
433     case dwarf::DW_OP_dup:
434       emitOp(OpNum);
435       break;
436     case dwarf::DW_OP_deref:
437       assert(!isRegisterLocation());
438       if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
439         // Turning this into a memory location description makes the deref
440         // implicit.
441         LocationKind = Memory;
442       else
443         emitOp(dwarf::DW_OP_deref);
444       break;
445     case dwarf::DW_OP_constu:
446       assert(!isRegisterLocation());
447       emitConstu(Op->getArg(0));
448       break;
449     case dwarf::DW_OP_LLVM_convert: {
450       unsigned BitSize = Op->getArg(0);
451       dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
452       if (DwarfVersion >= 5) {
453         emitOp(dwarf::DW_OP_convert);
454         // Reuse the base_type if we already have one in this CU otherwise we
455         // create a new one.
456         unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
457         for (; I != E; ++I)
458           if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
459               CU.ExprRefedBaseTypes[I].Encoding == Encoding)
460             break;
461 
462         if (I == E)
463           CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
464 
465         // If targeting a location-list; simply emit the index into the raw
466         // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
467         // fitted with means to extract it later.
468         // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
469         // (containing the index and a resolve mechanism during emit) into the
470         // DIE value list.
471         emitBaseTypeRef(I);
472       } else {
473         if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
474           if (Encoding == dwarf::DW_ATE_signed)
475             emitLegacySExt(PrevConvertOp->getArg(0));
476           else if (Encoding == dwarf::DW_ATE_unsigned)
477             emitLegacyZExt(PrevConvertOp->getArg(0));
478           PrevConvertOp = None;
479         } else {
480           PrevConvertOp = Op;
481         }
482       }
483       break;
484     }
485     case dwarf::DW_OP_stack_value:
486       LocationKind = Implicit;
487       break;
488     case dwarf::DW_OP_swap:
489       assert(!isRegisterLocation());
490       emitOp(dwarf::DW_OP_swap);
491       break;
492     case dwarf::DW_OP_xderef:
493       assert(!isRegisterLocation());
494       emitOp(dwarf::DW_OP_xderef);
495       break;
496     case dwarf::DW_OP_deref_size:
497       emitOp(dwarf::DW_OP_deref_size);
498       emitData1(Op->getArg(0));
499       break;
500     case dwarf::DW_OP_LLVM_tag_offset:
501       TagOffset = Op->getArg(0);
502       break;
503     case dwarf::DW_OP_regx:
504       emitOp(dwarf::DW_OP_regx);
505       emitUnsigned(Op->getArg(0));
506       break;
507     case dwarf::DW_OP_bregx:
508       emitOp(dwarf::DW_OP_bregx);
509       emitUnsigned(Op->getArg(0));
510       emitSigned(Op->getArg(1));
511       break;
512     default:
513       llvm_unreachable("unhandled opcode found in expression");
514     }
515   }
516 
517   if (isImplicitLocation() && !isParameterValue())
518     // Turn this into an implicit location description.
519     addStackValue();
520 }
521 
522 /// add masking operations to stencil out a subregister.
523 void DwarfExpression::maskSubRegister() {
524   assert(SubRegisterSizeInBits && "no subregister was registered");
525   if (SubRegisterOffsetInBits > 0)
526     addShr(SubRegisterOffsetInBits);
527   uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
528   addAnd(Mask);
529 }
530 
531 void DwarfExpression::finalize() {
532   assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
533   // Emit any outstanding DW_OP_piece operations to mask out subregisters.
534   if (SubRegisterSizeInBits == 0)
535     return;
536   // Don't emit a DW_OP_piece for a subregister at offset 0.
537   if (SubRegisterOffsetInBits == 0)
538     return;
539   addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
540 }
541 
542 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
543   if (!Expr || !Expr->isFragment())
544     return;
545 
546   uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
547   assert(FragmentOffset >= OffsetInBits &&
548          "overlapping or duplicate fragments");
549   if (FragmentOffset > OffsetInBits)
550     addOpPiece(FragmentOffset - OffsetInBits);
551   OffsetInBits = FragmentOffset;
552 }
553 
554 void DwarfExpression::emitLegacySExt(unsigned FromBits) {
555   // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
556   emitOp(dwarf::DW_OP_dup);
557   emitOp(dwarf::DW_OP_constu);
558   emitUnsigned(FromBits - 1);
559   emitOp(dwarf::DW_OP_shr);
560   emitOp(dwarf::DW_OP_lit0);
561   emitOp(dwarf::DW_OP_not);
562   emitOp(dwarf::DW_OP_mul);
563   emitOp(dwarf::DW_OP_constu);
564   emitUnsigned(FromBits);
565   emitOp(dwarf::DW_OP_shl);
566   emitOp(dwarf::DW_OP_or);
567 }
568 
569 void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
570   // (X & (1 << FromBits - 1))
571   emitOp(dwarf::DW_OP_constu);
572   emitUnsigned((1ULL << FromBits) - 1);
573   emitOp(dwarf::DW_OP_and);
574 }
575 
576 void DwarfExpression::addWasmLocation(unsigned Index, int64_t Offset) {
577   assert(LocationKind == Implicit || LocationKind == Unknown);
578   LocationKind = Implicit;
579   emitOp(dwarf::DW_OP_WASM_location);
580   emitUnsigned(Index);
581   emitSigned(Offset);
582 }
583