1 //===-- CodeGenCommonISel.cpp ---------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines common utilies that are shared between SelectionDAG and
10 // GlobalISel frameworks.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/CodeGenCommonISel.h"
15 #include "llvm/Analysis/BranchProbabilityInfo.h"
16 #include "llvm/CodeGen/MachineBasicBlock.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/TargetInstrInfo.h"
19 #include "llvm/CodeGen/TargetOpcodes.h"
20 
21 using namespace llvm;
22 
23 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
24 /// is 0.
25 MachineBasicBlock *
26 StackProtectorDescriptor::addSuccessorMBB(
27     const BasicBlock *BB, MachineBasicBlock *ParentMBB, bool IsLikely,
28     MachineBasicBlock *SuccMBB) {
29   // If SuccBB has not been created yet, create it.
30   if (!SuccMBB) {
31     MachineFunction *MF = ParentMBB->getParent();
32     MachineFunction::iterator BBI(ParentMBB);
33     SuccMBB = MF->CreateMachineBasicBlock(BB);
34     MF->insert(++BBI, SuccMBB);
35   }
36   // Add it as a successor of ParentMBB.
37   ParentMBB->addSuccessor(
38       SuccMBB, BranchProbabilityInfo::getBranchProbStackProtector(IsLikely));
39   return SuccMBB;
40 }
41 
42 /// Given that the input MI is before a partial terminator sequence TSeq, return
43 /// true if M + TSeq also a partial terminator sequence.
44 ///
45 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
46 /// lowering copy vregs into physical registers, which are then passed into
47 /// terminator instructors so we can satisfy ABI constraints. A partial
48 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
49 /// may be the whole terminator sequence).
50 static bool MIIsInTerminatorSequence(const MachineInstr &MI) {
51   // If we do not have a copy or an implicit def, we return true if and only if
52   // MI is a debug value.
53   if (!MI.isCopy() && !MI.isImplicitDef()) {
54     // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
55     // physical registers if there is debug info associated with the terminator
56     // of our mbb. We want to include said debug info in our terminator
57     // sequence, so we return true in that case.
58     if (MI.isDebugInstr())
59       return true;
60 
61     // For GlobalISel, we may have extension instructions for arguments within
62     // copy sequences. Allow these.
63     switch (MI.getOpcode()) {
64     case TargetOpcode::G_TRUNC:
65     case TargetOpcode::G_ZEXT:
66     case TargetOpcode::G_ANYEXT:
67     case TargetOpcode::G_SEXT:
68     case TargetOpcode::G_MERGE_VALUES:
69     case TargetOpcode::G_UNMERGE_VALUES:
70     case TargetOpcode::G_CONCAT_VECTORS:
71     case TargetOpcode::G_BUILD_VECTOR:
72     case TargetOpcode::G_EXTRACT:
73       return true;
74     default:
75       return false;
76     }
77   }
78 
79   // We have left the terminator sequence if we are not doing one of the
80   // following:
81   //
82   // 1. Copying a vreg into a physical register.
83   // 2. Copying a vreg into a vreg.
84   // 3. Defining a register via an implicit def.
85 
86   // OPI should always be a register definition...
87   MachineInstr::const_mop_iterator OPI = MI.operands_begin();
88   if (!OPI->isReg() || !OPI->isDef())
89     return false;
90 
91   // Defining any register via an implicit def is always ok.
92   if (MI.isImplicitDef())
93     return true;
94 
95   // Grab the copy source...
96   MachineInstr::const_mop_iterator OPI2 = OPI;
97   ++OPI2;
98   assert(OPI2 != MI.operands_end()
99          && "Should have a copy implying we should have 2 arguments.");
100 
101   // Make sure that the copy dest is not a vreg when the copy source is a
102   // physical register.
103   if (!OPI2->isReg() || (!Register::isPhysicalRegister(OPI->getReg()) &&
104                          Register::isPhysicalRegister(OPI2->getReg())))
105     return false;
106 
107   return true;
108 }
109 
110 /// Find the split point at which to splice the end of BB into its success stack
111 /// protector check machine basic block.
112 ///
113 /// On many platforms, due to ABI constraints, terminators, even before register
114 /// allocation, use physical registers. This creates an issue for us since
115 /// physical registers at this point can not travel across basic
116 /// blocks. Luckily, selectiondag always moves physical registers into vregs
117 /// when they enter functions and moves them through a sequence of copies back
118 /// into the physical registers right before the terminator creating a
119 /// ``Terminator Sequence''. This function is searching for the beginning of the
120 /// terminator sequence so that we can ensure that we splice off not just the
121 /// terminator, but additionally the copies that move the vregs into the
122 /// physical registers.
123 MachineBasicBlock::iterator
124 llvm::findSplitPointForStackProtector(MachineBasicBlock *BB,
125                                       const TargetInstrInfo &TII) {
126   MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
127   if (SplitPoint == BB->begin())
128     return SplitPoint;
129 
130   MachineBasicBlock::iterator Start = BB->begin();
131   MachineBasicBlock::iterator Previous = SplitPoint;
132   do {
133     --Previous;
134   } while (Previous != Start && Previous->isDebugInstr());
135 
136   if (TII.isTailCall(*SplitPoint) &&
137       Previous->getOpcode() == TII.getCallFrameDestroyOpcode()) {
138     // Call frames cannot be nested, so if this frame is describing the tail
139     // call itself, then we must insert before the sequence even starts. For
140     // example:
141     //     <split point>
142     //     ADJCALLSTACKDOWN ...
143     //     <Moves>
144     //     ADJCALLSTACKUP ...
145     //     TAILJMP somewhere
146     // On the other hand, it could be an unrelated call in which case this tail
147     // call has no register moves of its own and should be the split point. For
148     // example:
149     //     ADJCALLSTACKDOWN
150     //     CALL something_else
151     //     ADJCALLSTACKUP
152     //     <split point>
153     //     TAILJMP somewhere
154     do {
155       --Previous;
156       if (Previous->isCall())
157         return SplitPoint;
158     } while(Previous->getOpcode() != TII.getCallFrameSetupOpcode());
159 
160     return Previous;
161   }
162 
163   while (MIIsInTerminatorSequence(*Previous)) {
164     SplitPoint = Previous;
165     if (Previous == Start)
166       break;
167     --Previous;
168   }
169 
170   return SplitPoint;
171 }
172 
173 unsigned llvm::getInvertedFPClassTest(unsigned Test) {
174   unsigned InvertedTest = ~Test & fcAllFlags;
175   switch (InvertedTest) {
176   default:
177     break;
178   case fcNan:
179   case fcSNan:
180   case fcQNan:
181   case fcInf:
182   case fcPosInf:
183   case fcNegInf:
184   case fcNormal:
185   case fcPosNormal:
186   case fcNegNormal:
187   case fcSubnormal:
188   case fcPosSubnormal:
189   case fcNegSubnormal:
190   case fcZero:
191   case fcPosZero:
192   case fcNegZero:
193   case fcFinite:
194   case fcPosFinite:
195   case fcNegFinite:
196     return InvertedTest;
197   }
198   return 0;
199 }
200