1 //===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This is an extremely simple MachineInstr-level dead-code-elimination pass.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/PostOrderIterator.h"
14 #include "llvm/ADT/Statistic.h"
15 #include "llvm/CodeGen/MachineFunctionPass.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetSubtargetInfo.h"
19 #include "llvm/InitializePasses.h"
20 #include "llvm/Pass.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "dead-mi-elimination"
27 
28 STATISTIC(NumDeletes,          "Number of dead instructions deleted");
29 
30 namespace {
31   class DeadMachineInstructionElim : public MachineFunctionPass {
32     bool runOnMachineFunction(MachineFunction &MF) override;
33 
34     const TargetRegisterInfo *TRI;
35     const MachineRegisterInfo *MRI;
36     const TargetInstrInfo *TII;
37     BitVector LivePhysRegs;
38 
39   public:
40     static char ID; // Pass identification, replacement for typeid
41     DeadMachineInstructionElim() : MachineFunctionPass(ID) {
42      initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry());
43     }
44 
45     void getAnalysisUsage(AnalysisUsage &AU) const override {
46       AU.setPreservesCFG();
47       MachineFunctionPass::getAnalysisUsage(AU);
48     }
49 
50   private:
51     bool isDead(const MachineInstr *MI) const;
52 
53     bool eliminateDeadMI(MachineFunction &MF);
54   };
55 }
56 char DeadMachineInstructionElim::ID = 0;
57 char &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID;
58 
59 INITIALIZE_PASS(DeadMachineInstructionElim, DEBUG_TYPE,
60                 "Remove dead machine instructions", false, false)
61 
62 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
63   // Technically speaking inline asm without side effects and no defs can still
64   // be deleted. But there is so much bad inline asm code out there, we should
65   // let them be.
66   if (MI->isInlineAsm())
67     return false;
68 
69   // Don't delete frame allocation labels.
70   if (MI->getOpcode() == TargetOpcode::LOCAL_ESCAPE)
71     return false;
72 
73   // Don't delete instructions with side effects.
74   bool SawStore = false;
75   if (!MI->isSafeToMove(nullptr, SawStore) && !MI->isPHI())
76     return false;
77 
78   // Examine each operand.
79   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
80     const MachineOperand &MO = MI->getOperand(i);
81     if (MO.isReg() && MO.isDef()) {
82       Register Reg = MO.getReg();
83       if (Register::isPhysicalRegister(Reg)) {
84         // Don't delete live physreg defs, or any reserved register defs.
85         if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
86           return false;
87       } else {
88         if (MO.isDead()) {
89 #ifndef NDEBUG
90           // Sanity check on uses of this dead register. All of them should be
91           // 'undef'.
92           for (auto &U : MRI->use_nodbg_operands(Reg))
93             assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
94 #endif
95           continue;
96         }
97         for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
98           if (&Use != MI)
99             // This def has a non-debug use. Don't delete the instruction!
100             return false;
101         }
102       }
103     }
104   }
105 
106   // If there are no defs with uses, the instruction is dead.
107   return true;
108 }
109 
110 bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
111   if (skipFunction(MF.getFunction()))
112     return false;
113   bool AnyChanges = eliminateDeadMI(MF);
114   while (AnyChanges && eliminateDeadMI(MF))
115     ;
116   return AnyChanges;
117 }
118 
119 bool DeadMachineInstructionElim::eliminateDeadMI(MachineFunction &MF) {
120   bool AnyChanges = false;
121   MRI = &MF.getRegInfo();
122   TRI = MF.getSubtarget().getRegisterInfo();
123   TII = MF.getSubtarget().getInstrInfo();
124 
125   // Loop over all instructions in all blocks, from bottom to top, so that it's
126   // more likely that chains of dependent but ultimately dead instructions will
127   // be cleaned up.
128   for (MachineBasicBlock *MBB : post_order(&MF)) {
129     // Start out assuming that reserved registers are live out of this block.
130     LivePhysRegs = MRI->getReservedRegs();
131 
132     // Add live-ins from successors to LivePhysRegs. Normally, physregs are not
133     // live across blocks, but some targets (x86) can have flags live out of a
134     // block.
135     for (const MachineBasicBlock *Succ : MBB->successors())
136       for (const auto &LI : Succ->liveins())
137         LivePhysRegs.set(LI.PhysReg);
138 
139     // Now scan the instructions and delete dead ones, tracking physreg
140     // liveness as we go.
141     for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
142                                              MIE = MBB->rend();
143          MII != MIE;) {
144       MachineInstr *MI = &*MII++;
145 
146       // If the instruction is dead, delete it!
147       if (isDead(MI)) {
148         LLVM_DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
149         // It is possible that some DBG_VALUE instructions refer to this
150         // instruction.  They get marked as undef and will be deleted
151         // in the live debug variable analysis.
152         MI->eraseFromParentAndMarkDBGValuesForRemoval();
153         AnyChanges = true;
154         ++NumDeletes;
155         continue;
156       }
157 
158       // Record the physreg defs.
159       for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
160         const MachineOperand &MO = MI->getOperand(i);
161         if (MO.isReg() && MO.isDef()) {
162           Register Reg = MO.getReg();
163           if (Register::isPhysicalRegister(Reg)) {
164             // Check the subreg set, not the alias set, because a def
165             // of a super-register may still be partially live after
166             // this def.
167             for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true);
168                  SR.isValid(); ++SR)
169               LivePhysRegs.reset(*SR);
170           }
171         } else if (MO.isRegMask()) {
172           // Register mask of preserved registers. All clobbers are dead.
173           LivePhysRegs.clearBitsNotInMask(MO.getRegMask());
174         }
175       }
176       // Record the physreg uses, after the defs, in case a physreg is
177       // both defined and used in the same instruction.
178       for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
179         const MachineOperand &MO = MI->getOperand(i);
180         if (MO.isReg() && MO.isUse()) {
181           Register Reg = MO.getReg();
182           if (Register::isPhysicalRegister(Reg)) {
183             for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
184               LivePhysRegs.set(*AI);
185           }
186         }
187       }
188     }
189   }
190 
191   LivePhysRegs.clear();
192   return AnyChanges;
193 }
194