1 //===- InlineSpiller.cpp - Insert spills and restores inline --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The inline spiller modifies the machine function directly instead of
10 // inserting spills and restores in VirtRegMap.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Spiller.h"
15 #include "SplitKit.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/MapVector.h"
19 #include "llvm/ADT/None.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/CodeGen/LiveInterval.h"
27 #include "llvm/CodeGen/LiveIntervals.h"
28 #include "llvm/CodeGen/LiveRangeCalc.h"
29 #include "llvm/CodeGen/LiveRangeEdit.h"
30 #include "llvm/CodeGen/LiveStacks.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
33 #include "llvm/CodeGen/MachineDominators.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstr.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineInstrBundle.h"
39 #include "llvm/CodeGen/MachineLoopInfo.h"
40 #include "llvm/CodeGen/MachineOperand.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/SlotIndexes.h"
43 #include "llvm/CodeGen/TargetInstrInfo.h"
44 #include "llvm/CodeGen/TargetOpcodes.h"
45 #include "llvm/CodeGen/TargetRegisterInfo.h"
46 #include "llvm/CodeGen/TargetSubtargetInfo.h"
47 #include "llvm/CodeGen/VirtRegMap.h"
48 #include "llvm/Config/llvm-config.h"
49 #include "llvm/Support/BlockFrequency.h"
50 #include "llvm/Support/BranchProbability.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Compiler.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/raw_ostream.h"
56 #include <cassert>
57 #include <iterator>
58 #include <tuple>
59 #include <utility>
60 #include <vector>
61 
62 using namespace llvm;
63 
64 #define DEBUG_TYPE "regalloc"
65 
66 STATISTIC(NumSpilledRanges,   "Number of spilled live ranges");
67 STATISTIC(NumSnippets,        "Number of spilled snippets");
68 STATISTIC(NumSpills,          "Number of spills inserted");
69 STATISTIC(NumSpillsRemoved,   "Number of spills removed");
70 STATISTIC(NumReloads,         "Number of reloads inserted");
71 STATISTIC(NumReloadsRemoved,  "Number of reloads removed");
72 STATISTIC(NumFolded,          "Number of folded stack accesses");
73 STATISTIC(NumFoldedLoads,     "Number of folded loads");
74 STATISTIC(NumRemats,          "Number of rematerialized defs for spilling");
75 
76 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
77                                      cl::desc("Disable inline spill hoisting"));
78 static cl::opt<bool>
79 RestrictStatepointRemat("restrict-statepoint-remat",
80                        cl::init(false), cl::Hidden,
81                        cl::desc("Restrict remat for statepoint operands"));
82 
83 namespace {
84 
85 class HoistSpillHelper : private LiveRangeEdit::Delegate {
86   MachineFunction &MF;
87   LiveIntervals &LIS;
88   LiveStacks &LSS;
89   AliasAnalysis *AA;
90   MachineDominatorTree &MDT;
91   MachineLoopInfo &Loops;
92   VirtRegMap &VRM;
93   MachineRegisterInfo &MRI;
94   const TargetInstrInfo &TII;
95   const TargetRegisterInfo &TRI;
96   const MachineBlockFrequencyInfo &MBFI;
97 
98   InsertPointAnalysis IPA;
99 
100   // Map from StackSlot to the LiveInterval of the original register.
101   // Note the LiveInterval of the original register may have been deleted
102   // after it is spilled. We keep a copy here to track the range where
103   // spills can be moved.
104   DenseMap<int, std::unique_ptr<LiveInterval>> StackSlotToOrigLI;
105 
106   // Map from pair of (StackSlot and Original VNI) to a set of spills which
107   // have the same stackslot and have equal values defined by Original VNI.
108   // These spills are mergeable and are hoist candiates.
109   using MergeableSpillsMap =
110       MapVector<std::pair<int, VNInfo *>, SmallPtrSet<MachineInstr *, 16>>;
111   MergeableSpillsMap MergeableSpills;
112 
113   /// This is the map from original register to a set containing all its
114   /// siblings. To hoist a spill to another BB, we need to find out a live
115   /// sibling there and use it as the source of the new spill.
116   DenseMap<unsigned, SmallSetVector<unsigned, 16>> Virt2SiblingsMap;
117 
118   bool isSpillCandBB(LiveInterval &OrigLI, VNInfo &OrigVNI,
119                      MachineBasicBlock &BB, unsigned &LiveReg);
120 
121   void rmRedundantSpills(
122       SmallPtrSet<MachineInstr *, 16> &Spills,
123       SmallVectorImpl<MachineInstr *> &SpillsToRm,
124       DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
125 
126   void getVisitOrders(
127       MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
128       SmallVectorImpl<MachineDomTreeNode *> &Orders,
129       SmallVectorImpl<MachineInstr *> &SpillsToRm,
130       DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
131       DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
132 
133   void runHoistSpills(LiveInterval &OrigLI, VNInfo &OrigVNI,
134                       SmallPtrSet<MachineInstr *, 16> &Spills,
135                       SmallVectorImpl<MachineInstr *> &SpillsToRm,
136                       DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns);
137 
138 public:
139   HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf,
140                    VirtRegMap &vrm)
141       : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
142         LSS(pass.getAnalysis<LiveStacks>()),
143         AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()),
144         MDT(pass.getAnalysis<MachineDominatorTree>()),
145         Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm),
146         MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
147         TRI(*mf.getSubtarget().getRegisterInfo()),
148         MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()),
149         IPA(LIS, mf.getNumBlockIDs()) {}
150 
151   void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
152                             unsigned Original);
153   bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
154   void hoistAllSpills();
155   void LRE_DidCloneVirtReg(unsigned, unsigned) override;
156 };
157 
158 class InlineSpiller : public Spiller {
159   MachineFunction &MF;
160   LiveIntervals &LIS;
161   LiveStacks &LSS;
162   AliasAnalysis *AA;
163   MachineDominatorTree &MDT;
164   MachineLoopInfo &Loops;
165   VirtRegMap &VRM;
166   MachineRegisterInfo &MRI;
167   const TargetInstrInfo &TII;
168   const TargetRegisterInfo &TRI;
169   const MachineBlockFrequencyInfo &MBFI;
170 
171   // Variables that are valid during spill(), but used by multiple methods.
172   LiveRangeEdit *Edit;
173   LiveInterval *StackInt;
174   int StackSlot;
175   unsigned Original;
176 
177   // All registers to spill to StackSlot, including the main register.
178   SmallVector<unsigned, 8> RegsToSpill;
179 
180   // All COPY instructions to/from snippets.
181   // They are ignored since both operands refer to the same stack slot.
182   SmallPtrSet<MachineInstr*, 8> SnippetCopies;
183 
184   // Values that failed to remat at some point.
185   SmallPtrSet<VNInfo*, 8> UsedValues;
186 
187   // Dead defs generated during spilling.
188   SmallVector<MachineInstr*, 8> DeadDefs;
189 
190   // Object records spills information and does the hoisting.
191   HoistSpillHelper HSpiller;
192 
193   ~InlineSpiller() override = default;
194 
195 public:
196   InlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
197       : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
198         LSS(pass.getAnalysis<LiveStacks>()),
199         AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()),
200         MDT(pass.getAnalysis<MachineDominatorTree>()),
201         Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm),
202         MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
203         TRI(*mf.getSubtarget().getRegisterInfo()),
204         MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()),
205         HSpiller(pass, mf, vrm) {}
206 
207   void spill(LiveRangeEdit &) override;
208   void postOptimization() override;
209 
210 private:
211   bool isSnippet(const LiveInterval &SnipLI);
212   void collectRegsToSpill();
213 
214   bool isRegToSpill(unsigned Reg) { return is_contained(RegsToSpill, Reg); }
215 
216   bool isSibling(unsigned Reg);
217   bool hoistSpillInsideBB(LiveInterval &SpillLI, MachineInstr &CopyMI);
218   void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
219 
220   void markValueUsed(LiveInterval*, VNInfo*);
221   bool canGuaranteeAssignmentAfterRemat(unsigned VReg, MachineInstr &MI);
222   bool reMaterializeFor(LiveInterval &, MachineInstr &MI);
223   void reMaterializeAll();
224 
225   bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
226   bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>>,
227                          MachineInstr *LoadMI = nullptr);
228   void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI);
229   void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI);
230 
231   void spillAroundUses(unsigned Reg);
232   void spillAll();
233 };
234 
235 } // end anonymous namespace
236 
237 Spiller::~Spiller() = default;
238 
239 void Spiller::anchor() {}
240 
241 Spiller *llvm::createInlineSpiller(MachineFunctionPass &pass,
242                                    MachineFunction &mf,
243                                    VirtRegMap &vrm) {
244   return new InlineSpiller(pass, mf, vrm);
245 }
246 
247 //===----------------------------------------------------------------------===//
248 //                                Snippets
249 //===----------------------------------------------------------------------===//
250 
251 // When spilling a virtual register, we also spill any snippets it is connected
252 // to. The snippets are small live ranges that only have a single real use,
253 // leftovers from live range splitting. Spilling them enables memory operand
254 // folding or tightens the live range around the single use.
255 //
256 // This minimizes register pressure and maximizes the store-to-load distance for
257 // spill slots which can be important in tight loops.
258 
259 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
260 /// otherwise return 0.
261 static unsigned isFullCopyOf(const MachineInstr &MI, unsigned Reg) {
262   if (!MI.isFullCopy())
263     return 0;
264   if (MI.getOperand(0).getReg() == Reg)
265     return MI.getOperand(1).getReg();
266   if (MI.getOperand(1).getReg() == Reg)
267     return MI.getOperand(0).getReg();
268   return 0;
269 }
270 
271 /// isSnippet - Identify if a live interval is a snippet that should be spilled.
272 /// It is assumed that SnipLI is a virtual register with the same original as
273 /// Edit->getReg().
274 bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
275   unsigned Reg = Edit->getReg();
276 
277   // A snippet is a tiny live range with only a single instruction using it
278   // besides copies to/from Reg or spills/fills. We accept:
279   //
280   //   %snip = COPY %Reg / FILL fi#
281   //   %snip = USE %snip
282   //   %Reg = COPY %snip / SPILL %snip, fi#
283   //
284   if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
285     return false;
286 
287   MachineInstr *UseMI = nullptr;
288 
289   // Check that all uses satisfy our criteria.
290   for (MachineRegisterInfo::reg_instr_nodbg_iterator
291        RI = MRI.reg_instr_nodbg_begin(SnipLI.reg),
292        E = MRI.reg_instr_nodbg_end(); RI != E; ) {
293     MachineInstr &MI = *RI++;
294 
295     // Allow copies to/from Reg.
296     if (isFullCopyOf(MI, Reg))
297       continue;
298 
299     // Allow stack slot loads.
300     int FI;
301     if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
302       continue;
303 
304     // Allow stack slot stores.
305     if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
306       continue;
307 
308     // Allow a single additional instruction.
309     if (UseMI && &MI != UseMI)
310       return false;
311     UseMI = &MI;
312   }
313   return true;
314 }
315 
316 /// collectRegsToSpill - Collect live range snippets that only have a single
317 /// real use.
318 void InlineSpiller::collectRegsToSpill() {
319   unsigned Reg = Edit->getReg();
320 
321   // Main register always spills.
322   RegsToSpill.assign(1, Reg);
323   SnippetCopies.clear();
324 
325   // Snippets all have the same original, so there can't be any for an original
326   // register.
327   if (Original == Reg)
328     return;
329 
330   for (MachineRegisterInfo::reg_instr_iterator
331        RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) {
332     MachineInstr &MI = *RI++;
333     unsigned SnipReg = isFullCopyOf(MI, Reg);
334     if (!isSibling(SnipReg))
335       continue;
336     LiveInterval &SnipLI = LIS.getInterval(SnipReg);
337     if (!isSnippet(SnipLI))
338       continue;
339     SnippetCopies.insert(&MI);
340     if (isRegToSpill(SnipReg))
341       continue;
342     RegsToSpill.push_back(SnipReg);
343     LLVM_DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
344     ++NumSnippets;
345   }
346 }
347 
348 bool InlineSpiller::isSibling(unsigned Reg) {
349   return Register::isVirtualRegister(Reg) && VRM.getOriginal(Reg) == Original;
350 }
351 
352 /// It is beneficial to spill to earlier place in the same BB in case
353 /// as follows:
354 /// There is an alternative def earlier in the same MBB.
355 /// Hoist the spill as far as possible in SpillMBB. This can ease
356 /// register pressure:
357 ///
358 ///   x = def
359 ///   y = use x
360 ///   s = copy x
361 ///
362 /// Hoisting the spill of s to immediately after the def removes the
363 /// interference between x and y:
364 ///
365 ///   x = def
366 ///   spill x
367 ///   y = use killed x
368 ///
369 /// This hoist only helps when the copy kills its source.
370 ///
371 bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
372                                        MachineInstr &CopyMI) {
373   SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
374 #ifndef NDEBUG
375   VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
376   assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
377 #endif
378 
379   Register SrcReg = CopyMI.getOperand(1).getReg();
380   LiveInterval &SrcLI = LIS.getInterval(SrcReg);
381   VNInfo *SrcVNI = SrcLI.getVNInfoAt(Idx);
382   LiveQueryResult SrcQ = SrcLI.Query(Idx);
383   MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(SrcVNI->def);
384   if (DefMBB != CopyMI.getParent() || !SrcQ.isKill())
385     return false;
386 
387   // Conservatively extend the stack slot range to the range of the original
388   // value. We may be able to do better with stack slot coloring by being more
389   // careful here.
390   assert(StackInt && "No stack slot assigned yet.");
391   LiveInterval &OrigLI = LIS.getInterval(Original);
392   VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
393   StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
394   LLVM_DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
395                     << *StackInt << '\n');
396 
397   // We are going to spill SrcVNI immediately after its def, so clear out
398   // any later spills of the same value.
399   eliminateRedundantSpills(SrcLI, SrcVNI);
400 
401   MachineBasicBlock *MBB = LIS.getMBBFromIndex(SrcVNI->def);
402   MachineBasicBlock::iterator MII;
403   if (SrcVNI->isPHIDef())
404     MII = MBB->SkipPHIsLabelsAndDebug(MBB->begin());
405   else {
406     MachineInstr *DefMI = LIS.getInstructionFromIndex(SrcVNI->def);
407     assert(DefMI && "Defining instruction disappeared");
408     MII = DefMI;
409     ++MII;
410   }
411   // Insert spill without kill flag immediately after def.
412   TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
413                           MRI.getRegClass(SrcReg), &TRI);
414   --MII; // Point to store instruction.
415   LIS.InsertMachineInstrInMaps(*MII);
416   LLVM_DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII);
417 
418   HSpiller.addToMergeableSpills(*MII, StackSlot, Original);
419   ++NumSpills;
420   return true;
421 }
422 
423 /// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
424 /// redundant spills of this value in SLI.reg and sibling copies.
425 void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
426   assert(VNI && "Missing value");
427   SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
428   WorkList.push_back(std::make_pair(&SLI, VNI));
429   assert(StackInt && "No stack slot assigned yet.");
430 
431   do {
432     LiveInterval *LI;
433     std::tie(LI, VNI) = WorkList.pop_back_val();
434     unsigned Reg = LI->reg;
435     LLVM_DEBUG(dbgs() << "Checking redundant spills for " << VNI->id << '@'
436                       << VNI->def << " in " << *LI << '\n');
437 
438     // Regs to spill are taken care of.
439     if (isRegToSpill(Reg))
440       continue;
441 
442     // Add all of VNI's live range to StackInt.
443     StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
444     LLVM_DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
445 
446     // Find all spills and copies of VNI.
447     for (MachineRegisterInfo::use_instr_nodbg_iterator
448          UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
449          UI != E; ) {
450       MachineInstr &MI = *UI++;
451       if (!MI.isCopy() && !MI.mayStore())
452         continue;
453       SlotIndex Idx = LIS.getInstructionIndex(MI);
454       if (LI->getVNInfoAt(Idx) != VNI)
455         continue;
456 
457       // Follow sibling copies down the dominator tree.
458       if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
459         if (isSibling(DstReg)) {
460            LiveInterval &DstLI = LIS.getInterval(DstReg);
461            VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
462            assert(DstVNI && "Missing defined value");
463            assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
464            WorkList.push_back(std::make_pair(&DstLI, DstVNI));
465         }
466         continue;
467       }
468 
469       // Erase spills.
470       int FI;
471       if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
472         LLVM_DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI);
473         // eliminateDeadDefs won't normally remove stores, so switch opcode.
474         MI.setDesc(TII.get(TargetOpcode::KILL));
475         DeadDefs.push_back(&MI);
476         ++NumSpillsRemoved;
477         if (HSpiller.rmFromMergeableSpills(MI, StackSlot))
478           --NumSpills;
479       }
480     }
481   } while (!WorkList.empty());
482 }
483 
484 //===----------------------------------------------------------------------===//
485 //                            Rematerialization
486 //===----------------------------------------------------------------------===//
487 
488 /// markValueUsed - Remember that VNI failed to rematerialize, so its defining
489 /// instruction cannot be eliminated. See through snippet copies
490 void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
491   SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
492   WorkList.push_back(std::make_pair(LI, VNI));
493   do {
494     std::tie(LI, VNI) = WorkList.pop_back_val();
495     if (!UsedValues.insert(VNI).second)
496       continue;
497 
498     if (VNI->isPHIDef()) {
499       MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
500       for (MachineBasicBlock *P : MBB->predecessors()) {
501         VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(P));
502         if (PVNI)
503           WorkList.push_back(std::make_pair(LI, PVNI));
504       }
505       continue;
506     }
507 
508     // Follow snippet copies.
509     MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
510     if (!SnippetCopies.count(MI))
511       continue;
512     LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
513     assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
514     VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
515     assert(SnipVNI && "Snippet undefined before copy");
516     WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
517   } while (!WorkList.empty());
518 }
519 
520 bool InlineSpiller::canGuaranteeAssignmentAfterRemat(unsigned VReg,
521                                                      MachineInstr &MI) {
522   if (!RestrictStatepointRemat)
523     return true;
524   // Here's a quick explanation of the problem we're trying to handle here:
525   // * There are some pseudo instructions with more vreg uses than there are
526   //   physical registers on the machine.
527   // * This is normally handled by spilling the vreg, and folding the reload
528   //   into the user instruction.  (Thus decreasing the number of used vregs
529   //   until the remainder can be assigned to physregs.)
530   // * However, since we may try to spill vregs in any order, we can end up
531   //   trying to spill each operand to the instruction, and then rematting it
532   //   instead.  When that happens, the new live intervals (for the remats) are
533   //   expected to be trivially assignable (i.e. RS_Done).  However, since we
534   //   may have more remats than physregs, we're guaranteed to fail to assign
535   //   one.
536   // At the moment, we only handle this for STATEPOINTs since they're the only
537   // pseudo op where we've seen this.  If we start seeing other instructions
538   // with the same problem, we need to revisit this.
539   return (MI.getOpcode() != TargetOpcode::STATEPOINT);
540 }
541 
542 /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
543 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
544   // Analyze instruction
545   SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops;
546   VirtRegInfo RI = AnalyzeVirtRegInBundle(MI, VirtReg.reg, &Ops);
547 
548   if (!RI.Reads)
549     return false;
550 
551   SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
552   VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
553 
554   if (!ParentVNI) {
555     LLVM_DEBUG(dbgs() << "\tadding <undef> flags: ");
556     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
557       MachineOperand &MO = MI.getOperand(i);
558       if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
559         MO.setIsUndef();
560     }
561     LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI);
562     return true;
563   }
564 
565   if (SnippetCopies.count(&MI))
566     return false;
567 
568   LiveInterval &OrigLI = LIS.getInterval(Original);
569   VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx);
570   LiveRangeEdit::Remat RM(ParentVNI);
571   RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def);
572 
573   if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx, false)) {
574     markValueUsed(&VirtReg, ParentVNI);
575     LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI);
576     return false;
577   }
578 
579   // If the instruction also writes VirtReg.reg, it had better not require the
580   // same register for uses and defs.
581   if (RI.Tied) {
582     markValueUsed(&VirtReg, ParentVNI);
583     LLVM_DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI);
584     return false;
585   }
586 
587   // Before rematerializing into a register for a single instruction, try to
588   // fold a load into the instruction. That avoids allocating a new register.
589   if (RM.OrigMI->canFoldAsLoad() &&
590       foldMemoryOperand(Ops, RM.OrigMI)) {
591     Edit->markRematerialized(RM.ParentVNI);
592     ++NumFoldedLoads;
593     return true;
594   }
595 
596   // If we can't guarantee that we'll be able to actually assign the new vreg,
597   // we can't remat.
598   if (!canGuaranteeAssignmentAfterRemat(VirtReg.reg, MI)) {
599     markValueUsed(&VirtReg, ParentVNI);
600     LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI);
601     return false;
602   }
603 
604   // Allocate a new register for the remat.
605   unsigned NewVReg = Edit->createFrom(Original);
606 
607   // Finally we can rematerialize OrigMI before MI.
608   SlotIndex DefIdx =
609       Edit->rematerializeAt(*MI.getParent(), MI, NewVReg, RM, TRI);
610 
611   // We take the DebugLoc from MI, since OrigMI may be attributed to a
612   // different source location.
613   auto *NewMI = LIS.getInstructionFromIndex(DefIdx);
614   NewMI->setDebugLoc(MI.getDebugLoc());
615 
616   (void)DefIdx;
617   LLVM_DEBUG(dbgs() << "\tremat:  " << DefIdx << '\t'
618                     << *LIS.getInstructionFromIndex(DefIdx));
619 
620   // Replace operands
621   for (const auto &OpPair : Ops) {
622     MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
623     if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
624       MO.setReg(NewVReg);
625       MO.setIsKill();
626     }
627   }
628   LLVM_DEBUG(dbgs() << "\t        " << UseIdx << '\t' << MI << '\n');
629 
630   ++NumRemats;
631   return true;
632 }
633 
634 /// reMaterializeAll - Try to rematerialize as many uses as possible,
635 /// and trim the live ranges after.
636 void InlineSpiller::reMaterializeAll() {
637   if (!Edit->anyRematerializable(AA))
638     return;
639 
640   UsedValues.clear();
641 
642   // Try to remat before all uses of snippets.
643   bool anyRemat = false;
644   for (unsigned Reg : RegsToSpill) {
645     LiveInterval &LI = LIS.getInterval(Reg);
646     for (MachineRegisterInfo::reg_bundle_iterator
647            RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
648          RegI != E; ) {
649       MachineInstr &MI = *RegI++;
650 
651       // Debug values are not allowed to affect codegen.
652       if (MI.isDebugValue())
653         continue;
654 
655       assert(!MI.isDebugInstr() && "Did not expect to find a use in debug "
656              "instruction that isn't a DBG_VALUE");
657 
658       anyRemat |= reMaterializeFor(LI, MI);
659     }
660   }
661   if (!anyRemat)
662     return;
663 
664   // Remove any values that were completely rematted.
665   for (unsigned Reg : RegsToSpill) {
666     LiveInterval &LI = LIS.getInterval(Reg);
667     for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
668          I != E; ++I) {
669       VNInfo *VNI = *I;
670       if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
671         continue;
672       MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
673       MI->addRegisterDead(Reg, &TRI);
674       if (!MI->allDefsAreDead())
675         continue;
676       LLVM_DEBUG(dbgs() << "All defs dead: " << *MI);
677       DeadDefs.push_back(MI);
678     }
679   }
680 
681   // Eliminate dead code after remat. Note that some snippet copies may be
682   // deleted here.
683   if (DeadDefs.empty())
684     return;
685   LLVM_DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
686   Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
687 
688   // LiveRangeEdit::eliminateDeadDef is used to remove dead define instructions
689   // after rematerialization.  To remove a VNI for a vreg from its LiveInterval,
690   // LiveIntervals::removeVRegDefAt is used. However, after non-PHI VNIs are all
691   // removed, PHI VNI are still left in the LiveInterval.
692   // So to get rid of unused reg, we need to check whether it has non-dbg
693   // reference instead of whether it has non-empty interval.
694   unsigned ResultPos = 0;
695   for (unsigned Reg : RegsToSpill) {
696     if (MRI.reg_nodbg_empty(Reg)) {
697       Edit->eraseVirtReg(Reg);
698       continue;
699     }
700 
701     assert(LIS.hasInterval(Reg) &&
702            (!LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) &&
703            "Empty and not used live-range?!");
704 
705     RegsToSpill[ResultPos++] = Reg;
706   }
707   RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());
708   LLVM_DEBUG(dbgs() << RegsToSpill.size()
709                     << " registers to spill after remat.\n");
710 }
711 
712 //===----------------------------------------------------------------------===//
713 //                                 Spilling
714 //===----------------------------------------------------------------------===//
715 
716 /// If MI is a load or store of StackSlot, it can be removed.
717 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
718   int FI = 0;
719   unsigned InstrReg = TII.isLoadFromStackSlot(*MI, FI);
720   bool IsLoad = InstrReg;
721   if (!IsLoad)
722     InstrReg = TII.isStoreToStackSlot(*MI, FI);
723 
724   // We have a stack access. Is it the right register and slot?
725   if (InstrReg != Reg || FI != StackSlot)
726     return false;
727 
728   if (!IsLoad)
729     HSpiller.rmFromMergeableSpills(*MI, StackSlot);
730 
731   LLVM_DEBUG(dbgs() << "Coalescing stack access: " << *MI);
732   LIS.RemoveMachineInstrFromMaps(*MI);
733   MI->eraseFromParent();
734 
735   if (IsLoad) {
736     ++NumReloadsRemoved;
737     --NumReloads;
738   } else {
739     ++NumSpillsRemoved;
740     --NumSpills;
741   }
742 
743   return true;
744 }
745 
746 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
747 LLVM_DUMP_METHOD
748 // Dump the range of instructions from B to E with their slot indexes.
749 static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
750                                                MachineBasicBlock::iterator E,
751                                                LiveIntervals const &LIS,
752                                                const char *const header,
753                                                unsigned VReg =0) {
754   char NextLine = '\n';
755   char SlotIndent = '\t';
756 
757   if (std::next(B) == E) {
758     NextLine = ' ';
759     SlotIndent = ' ';
760   }
761 
762   dbgs() << '\t' << header << ": " << NextLine;
763 
764   for (MachineBasicBlock::iterator I = B; I != E; ++I) {
765     SlotIndex Idx = LIS.getInstructionIndex(*I).getRegSlot();
766 
767     // If a register was passed in and this instruction has it as a
768     // destination that is marked as an early clobber, print the
769     // early-clobber slot index.
770     if (VReg) {
771       MachineOperand *MO = I->findRegisterDefOperand(VReg);
772       if (MO && MO->isEarlyClobber())
773         Idx = Idx.getRegSlot(true);
774     }
775 
776     dbgs() << SlotIndent << Idx << '\t' << *I;
777   }
778 }
779 #endif
780 
781 /// foldMemoryOperand - Try folding stack slot references in Ops into their
782 /// instructions.
783 ///
784 /// @param Ops    Operand indices from AnalyzeVirtRegInBundle().
785 /// @param LoadMI Load instruction to use instead of stack slot when non-null.
786 /// @return       True on success.
787 bool InlineSpiller::
788 foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
789                   MachineInstr *LoadMI) {
790   if (Ops.empty())
791     return false;
792   // Don't attempt folding in bundles.
793   MachineInstr *MI = Ops.front().first;
794   if (Ops.back().first != MI || MI->isBundled())
795     return false;
796 
797   bool WasCopy = MI->isCopy();
798   unsigned ImpReg = 0;
799 
800   // Spill subregs if the target allows it.
801   // We always want to spill subregs for stackmap/patchpoint pseudos.
802   bool SpillSubRegs = TII.isSubregFoldable() ||
803                       MI->getOpcode() == TargetOpcode::STATEPOINT ||
804                       MI->getOpcode() == TargetOpcode::PATCHPOINT ||
805                       MI->getOpcode() == TargetOpcode::STACKMAP;
806 
807   // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
808   // operands.
809   SmallVector<unsigned, 8> FoldOps;
810   for (const auto &OpPair : Ops) {
811     unsigned Idx = OpPair.second;
812     assert(MI == OpPair.first && "Instruction conflict during operand folding");
813     MachineOperand &MO = MI->getOperand(Idx);
814     if (MO.isImplicit()) {
815       ImpReg = MO.getReg();
816       continue;
817     }
818 
819     if (!SpillSubRegs && MO.getSubReg())
820       return false;
821     // We cannot fold a load instruction into a def.
822     if (LoadMI && MO.isDef())
823       return false;
824     // Tied use operands should not be passed to foldMemoryOperand.
825     if (!MI->isRegTiedToDefOperand(Idx))
826       FoldOps.push_back(Idx);
827   }
828 
829   // If we only have implicit uses, we won't be able to fold that.
830   // Moreover, TargetInstrInfo::foldMemoryOperand will assert if we try!
831   if (FoldOps.empty())
832     return false;
833 
834   MachineInstrSpan MIS(MI, MI->getParent());
835 
836   MachineInstr *FoldMI =
837       LoadMI ? TII.foldMemoryOperand(*MI, FoldOps, *LoadMI, &LIS)
838              : TII.foldMemoryOperand(*MI, FoldOps, StackSlot, &LIS, &VRM);
839   if (!FoldMI)
840     return false;
841 
842   // Remove LIS for any dead defs in the original MI not in FoldMI.
843   for (MIBundleOperands MO(*MI); MO.isValid(); ++MO) {
844     if (!MO->isReg())
845       continue;
846     Register Reg = MO->getReg();
847     if (!Reg || Register::isVirtualRegister(Reg) || MRI.isReserved(Reg)) {
848       continue;
849     }
850     // Skip non-Defs, including undef uses and internal reads.
851     if (MO->isUse())
852       continue;
853     PhysRegInfo RI = AnalyzePhysRegInBundle(*FoldMI, Reg, &TRI);
854     if (RI.FullyDefined)
855       continue;
856     // FoldMI does not define this physreg. Remove the LI segment.
857     assert(MO->isDead() && "Cannot fold physreg def");
858     SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
859     LIS.removePhysRegDefAt(Reg, Idx);
860   }
861 
862   int FI;
863   if (TII.isStoreToStackSlot(*MI, FI) &&
864       HSpiller.rmFromMergeableSpills(*MI, FI))
865     --NumSpills;
866   LIS.ReplaceMachineInstrInMaps(*MI, *FoldMI);
867   if (MI->isCall())
868     MI->getMF()->moveCallSiteInfo(MI, FoldMI);
869   MI->eraseFromParent();
870 
871   // Insert any new instructions other than FoldMI into the LIS maps.
872   assert(!MIS.empty() && "Unexpected empty span of instructions!");
873   for (MachineInstr &MI : MIS)
874     if (&MI != FoldMI)
875       LIS.InsertMachineInstrInMaps(MI);
876 
877   // TII.foldMemoryOperand may have left some implicit operands on the
878   // instruction.  Strip them.
879   if (ImpReg)
880     for (unsigned i = FoldMI->getNumOperands(); i; --i) {
881       MachineOperand &MO = FoldMI->getOperand(i - 1);
882       if (!MO.isReg() || !MO.isImplicit())
883         break;
884       if (MO.getReg() == ImpReg)
885         FoldMI->RemoveOperand(i - 1);
886     }
887 
888   LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,
889                                                 "folded"));
890 
891   if (!WasCopy)
892     ++NumFolded;
893   else if (Ops.front().second == 0) {
894     ++NumSpills;
895     HSpiller.addToMergeableSpills(*FoldMI, StackSlot, Original);
896   } else
897     ++NumReloads;
898   return true;
899 }
900 
901 void InlineSpiller::insertReload(unsigned NewVReg,
902                                  SlotIndex Idx,
903                                  MachineBasicBlock::iterator MI) {
904   MachineBasicBlock &MBB = *MI->getParent();
905 
906   MachineInstrSpan MIS(MI, &MBB);
907   TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
908                            MRI.getRegClass(NewVReg), &TRI);
909 
910   LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
911 
912   LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",
913                                                 NewVReg));
914   ++NumReloads;
915 }
916 
917 /// Check if \p Def fully defines a VReg with an undefined value.
918 /// If that's the case, that means the value of VReg is actually
919 /// not relevant.
920 static bool isFullUndefDef(const MachineInstr &Def) {
921   if (!Def.isImplicitDef())
922     return false;
923   assert(Def.getNumOperands() == 1 &&
924          "Implicit def with more than one definition");
925   // We can say that the VReg defined by Def is undef, only if it is
926   // fully defined by Def. Otherwise, some of the lanes may not be
927   // undef and the value of the VReg matters.
928   return !Def.getOperand(0).getSubReg();
929 }
930 
931 /// insertSpill - Insert a spill of NewVReg after MI.
932 void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
933                                  MachineBasicBlock::iterator MI) {
934   MachineBasicBlock &MBB = *MI->getParent();
935 
936   MachineInstrSpan MIS(MI, &MBB);
937   bool IsRealSpill = true;
938   if (isFullUndefDef(*MI)) {
939     // Don't spill undef value.
940     // Anything works for undef, in particular keeping the memory
941     // uninitialized is a viable option and it saves code size and
942     // run time.
943     BuildMI(MBB, std::next(MI), MI->getDebugLoc(), TII.get(TargetOpcode::KILL))
944         .addReg(NewVReg, getKillRegState(isKill));
945     IsRealSpill = false;
946   } else
947     TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot,
948                             MRI.getRegClass(NewVReg), &TRI);
949 
950   LIS.InsertMachineInstrRangeInMaps(std::next(MI), MIS.end());
951 
952   LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,
953                                                 "spill"));
954   ++NumSpills;
955   if (IsRealSpill)
956     HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original);
957 }
958 
959 /// spillAroundUses - insert spill code around each use of Reg.
960 void InlineSpiller::spillAroundUses(unsigned Reg) {
961   LLVM_DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n');
962   LiveInterval &OldLI = LIS.getInterval(Reg);
963 
964   // Iterate over instructions using Reg.
965   for (MachineRegisterInfo::reg_bundle_iterator
966        RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
967        RegI != E; ) {
968     MachineInstr *MI = &*(RegI++);
969 
970     // Debug values are not allowed to affect codegen.
971     if (MI->isDebugValue()) {
972       // Modify DBG_VALUE now that the value is in a spill slot.
973       MachineBasicBlock *MBB = MI->getParent();
974       LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI);
975       buildDbgValueForSpill(*MBB, MI, *MI, StackSlot);
976       MBB->erase(MI);
977       continue;
978     }
979 
980     assert(!MI->isDebugInstr() && "Did not expect to find a use in debug "
981            "instruction that isn't a DBG_VALUE");
982 
983     // Ignore copies to/from snippets. We'll delete them.
984     if (SnippetCopies.count(MI))
985       continue;
986 
987     // Stack slot accesses may coalesce away.
988     if (coalesceStackAccess(MI, Reg))
989       continue;
990 
991     // Analyze instruction.
992     SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
993     VirtRegInfo RI = AnalyzeVirtRegInBundle(*MI, Reg, &Ops);
994 
995     // Find the slot index where this instruction reads and writes OldLI.
996     // This is usually the def slot, except for tied early clobbers.
997     SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
998     if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
999       if (SlotIndex::isSameInstr(Idx, VNI->def))
1000         Idx = VNI->def;
1001 
1002     // Check for a sibling copy.
1003     unsigned SibReg = isFullCopyOf(*MI, Reg);
1004     if (SibReg && isSibling(SibReg)) {
1005       // This may actually be a copy between snippets.
1006       if (isRegToSpill(SibReg)) {
1007         LLVM_DEBUG(dbgs() << "Found new snippet copy: " << *MI);
1008         SnippetCopies.insert(MI);
1009         continue;
1010       }
1011       if (RI.Writes) {
1012         if (hoistSpillInsideBB(OldLI, *MI)) {
1013           // This COPY is now dead, the value is already in the stack slot.
1014           MI->getOperand(0).setIsDead();
1015           DeadDefs.push_back(MI);
1016           continue;
1017         }
1018       } else {
1019         // This is a reload for a sib-reg copy. Drop spills downstream.
1020         LiveInterval &SibLI = LIS.getInterval(SibReg);
1021         eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
1022         // The COPY will fold to a reload below.
1023       }
1024     }
1025 
1026     // Attempt to fold memory ops.
1027     if (foldMemoryOperand(Ops))
1028       continue;
1029 
1030     // Create a new virtual register for spill/fill.
1031     // FIXME: Infer regclass from instruction alone.
1032     unsigned NewVReg = Edit->createFrom(Reg);
1033 
1034     if (RI.Reads)
1035       insertReload(NewVReg, Idx, MI);
1036 
1037     // Rewrite instruction operands.
1038     bool hasLiveDef = false;
1039     for (const auto &OpPair : Ops) {
1040       MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
1041       MO.setReg(NewVReg);
1042       if (MO.isUse()) {
1043         if (!OpPair.first->isRegTiedToDefOperand(OpPair.second))
1044           MO.setIsKill();
1045       } else {
1046         if (!MO.isDead())
1047           hasLiveDef = true;
1048       }
1049     }
1050     LLVM_DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n');
1051 
1052     // FIXME: Use a second vreg if instruction has no tied ops.
1053     if (RI.Writes)
1054       if (hasLiveDef)
1055         insertSpill(NewVReg, true, MI);
1056   }
1057 }
1058 
1059 /// spillAll - Spill all registers remaining after rematerialization.
1060 void InlineSpiller::spillAll() {
1061   // Update LiveStacks now that we are committed to spilling.
1062   if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
1063     StackSlot = VRM.assignVirt2StackSlot(Original);
1064     StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
1065     StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator());
1066   } else
1067     StackInt = &LSS.getInterval(StackSlot);
1068 
1069   if (Original != Edit->getReg())
1070     VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
1071 
1072   assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
1073   for (unsigned Reg : RegsToSpill)
1074     StackInt->MergeSegmentsInAsValue(LIS.getInterval(Reg),
1075                                      StackInt->getValNumInfo(0));
1076   LLVM_DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
1077 
1078   // Spill around uses of all RegsToSpill.
1079   for (unsigned Reg : RegsToSpill)
1080     spillAroundUses(Reg);
1081 
1082   // Hoisted spills may cause dead code.
1083   if (!DeadDefs.empty()) {
1084     LLVM_DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
1085     Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
1086   }
1087 
1088   // Finally delete the SnippetCopies.
1089   for (unsigned Reg : RegsToSpill) {
1090     for (MachineRegisterInfo::reg_instr_iterator
1091          RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end();
1092          RI != E; ) {
1093       MachineInstr &MI = *(RI++);
1094       assert(SnippetCopies.count(&MI) && "Remaining use wasn't a snippet copy");
1095       // FIXME: Do this with a LiveRangeEdit callback.
1096       LIS.RemoveMachineInstrFromMaps(MI);
1097       MI.eraseFromParent();
1098     }
1099   }
1100 
1101   // Delete all spilled registers.
1102   for (unsigned Reg : RegsToSpill)
1103     Edit->eraseVirtReg(Reg);
1104 }
1105 
1106 void InlineSpiller::spill(LiveRangeEdit &edit) {
1107   ++NumSpilledRanges;
1108   Edit = &edit;
1109   assert(!Register::isStackSlot(edit.getReg()) &&
1110          "Trying to spill a stack slot.");
1111   // Share a stack slot among all descendants of Original.
1112   Original = VRM.getOriginal(edit.getReg());
1113   StackSlot = VRM.getStackSlot(Original);
1114   StackInt = nullptr;
1115 
1116   LLVM_DEBUG(dbgs() << "Inline spilling "
1117                     << TRI.getRegClassName(MRI.getRegClass(edit.getReg()))
1118                     << ':' << edit.getParent() << "\nFrom original "
1119                     << printReg(Original) << '\n');
1120   assert(edit.getParent().isSpillable() &&
1121          "Attempting to spill already spilled value.");
1122   assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
1123 
1124   collectRegsToSpill();
1125   reMaterializeAll();
1126 
1127   // Remat may handle everything.
1128   if (!RegsToSpill.empty())
1129     spillAll();
1130 
1131   Edit->calculateRegClassAndHint(MF, Loops, MBFI);
1132 }
1133 
1134 /// Optimizations after all the reg selections and spills are done.
1135 void InlineSpiller::postOptimization() { HSpiller.hoistAllSpills(); }
1136 
1137 /// When a spill is inserted, add the spill to MergeableSpills map.
1138 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot,
1139                                             unsigned Original) {
1140   BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
1141   LiveInterval &OrigLI = LIS.getInterval(Original);
1142   // save a copy of LiveInterval in StackSlotToOrigLI because the original
1143   // LiveInterval may be cleared after all its references are spilled.
1144   if (StackSlotToOrigLI.find(StackSlot) == StackSlotToOrigLI.end()) {
1145     auto LI = std::make_unique<LiveInterval>(OrigLI.reg, OrigLI.weight);
1146     LI->assign(OrigLI, Allocator);
1147     StackSlotToOrigLI[StackSlot] = std::move(LI);
1148   }
1149   SlotIndex Idx = LIS.getInstructionIndex(Spill);
1150   VNInfo *OrigVNI = StackSlotToOrigLI[StackSlot]->getVNInfoAt(Idx.getRegSlot());
1151   std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
1152   MergeableSpills[MIdx].insert(&Spill);
1153 }
1154 
1155 /// When a spill is removed, remove the spill from MergeableSpills map.
1156 /// Return true if the spill is removed successfully.
1157 bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill,
1158                                              int StackSlot) {
1159   auto It = StackSlotToOrigLI.find(StackSlot);
1160   if (It == StackSlotToOrigLI.end())
1161     return false;
1162   SlotIndex Idx = LIS.getInstructionIndex(Spill);
1163   VNInfo *OrigVNI = It->second->getVNInfoAt(Idx.getRegSlot());
1164   std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
1165   return MergeableSpills[MIdx].erase(&Spill);
1166 }
1167 
1168 /// Check BB to see if it is a possible target BB to place a hoisted spill,
1169 /// i.e., there should be a living sibling of OrigReg at the insert point.
1170 bool HoistSpillHelper::isSpillCandBB(LiveInterval &OrigLI, VNInfo &OrigVNI,
1171                                      MachineBasicBlock &BB, unsigned &LiveReg) {
1172   SlotIndex Idx;
1173   unsigned OrigReg = OrigLI.reg;
1174   MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, BB);
1175   if (MI != BB.end())
1176     Idx = LIS.getInstructionIndex(*MI);
1177   else
1178     Idx = LIS.getMBBEndIdx(&BB).getPrevSlot();
1179   SmallSetVector<unsigned, 16> &Siblings = Virt2SiblingsMap[OrigReg];
1180   assert(OrigLI.getVNInfoAt(Idx) == &OrigVNI && "Unexpected VNI");
1181 
1182   for (auto const SibReg : Siblings) {
1183     LiveInterval &LI = LIS.getInterval(SibReg);
1184     VNInfo *VNI = LI.getVNInfoAt(Idx);
1185     if (VNI) {
1186       LiveReg = SibReg;
1187       return true;
1188     }
1189   }
1190   return false;
1191 }
1192 
1193 /// Remove redundant spills in the same BB. Save those redundant spills in
1194 /// SpillsToRm, and save the spill to keep and its BB in SpillBBToSpill map.
1195 void HoistSpillHelper::rmRedundantSpills(
1196     SmallPtrSet<MachineInstr *, 16> &Spills,
1197     SmallVectorImpl<MachineInstr *> &SpillsToRm,
1198     DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
1199   // For each spill saw, check SpillBBToSpill[] and see if its BB already has
1200   // another spill inside. If a BB contains more than one spill, only keep the
1201   // earlier spill with smaller SlotIndex.
1202   for (const auto CurrentSpill : Spills) {
1203     MachineBasicBlock *Block = CurrentSpill->getParent();
1204     MachineDomTreeNode *Node = MDT.getBase().getNode(Block);
1205     MachineInstr *PrevSpill = SpillBBToSpill[Node];
1206     if (PrevSpill) {
1207       SlotIndex PIdx = LIS.getInstructionIndex(*PrevSpill);
1208       SlotIndex CIdx = LIS.getInstructionIndex(*CurrentSpill);
1209       MachineInstr *SpillToRm = (CIdx > PIdx) ? CurrentSpill : PrevSpill;
1210       MachineInstr *SpillToKeep = (CIdx > PIdx) ? PrevSpill : CurrentSpill;
1211       SpillsToRm.push_back(SpillToRm);
1212       SpillBBToSpill[MDT.getBase().getNode(Block)] = SpillToKeep;
1213     } else {
1214       SpillBBToSpill[MDT.getBase().getNode(Block)] = CurrentSpill;
1215     }
1216   }
1217   for (const auto SpillToRm : SpillsToRm)
1218     Spills.erase(SpillToRm);
1219 }
1220 
1221 /// Starting from \p Root find a top-down traversal order of the dominator
1222 /// tree to visit all basic blocks containing the elements of \p Spills.
1223 /// Redundant spills will be found and put into \p SpillsToRm at the same
1224 /// time. \p SpillBBToSpill will be populated as part of the process and
1225 /// maps a basic block to the first store occurring in the basic block.
1226 /// \post SpillsToRm.union(Spills\@post) == Spills\@pre
1227 void HoistSpillHelper::getVisitOrders(
1228     MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
1229     SmallVectorImpl<MachineDomTreeNode *> &Orders,
1230     SmallVectorImpl<MachineInstr *> &SpillsToRm,
1231     DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
1232     DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
1233   // The set contains all the possible BB nodes to which we may hoist
1234   // original spills.
1235   SmallPtrSet<MachineDomTreeNode *, 8> WorkSet;
1236   // Save the BB nodes on the path from the first BB node containing
1237   // non-redundant spill to the Root node.
1238   SmallPtrSet<MachineDomTreeNode *, 8> NodesOnPath;
1239   // All the spills to be hoisted must originate from a single def instruction
1240   // to the OrigReg. It means the def instruction should dominate all the spills
1241   // to be hoisted. We choose the BB where the def instruction is located as
1242   // the Root.
1243   MachineDomTreeNode *RootIDomNode = MDT[Root]->getIDom();
1244   // For every node on the dominator tree with spill, walk up on the dominator
1245   // tree towards the Root node until it is reached. If there is other node
1246   // containing spill in the middle of the path, the previous spill saw will
1247   // be redundant and the node containing it will be removed. All the nodes on
1248   // the path starting from the first node with non-redundant spill to the Root
1249   // node will be added to the WorkSet, which will contain all the possible
1250   // locations where spills may be hoisted to after the loop below is done.
1251   for (const auto Spill : Spills) {
1252     MachineBasicBlock *Block = Spill->getParent();
1253     MachineDomTreeNode *Node = MDT[Block];
1254     MachineInstr *SpillToRm = nullptr;
1255     while (Node != RootIDomNode) {
1256       // If Node dominates Block, and it already contains a spill, the spill in
1257       // Block will be redundant.
1258       if (Node != MDT[Block] && SpillBBToSpill[Node]) {
1259         SpillToRm = SpillBBToSpill[MDT[Block]];
1260         break;
1261         /// If we see the Node already in WorkSet, the path from the Node to
1262         /// the Root node must already be traversed by another spill.
1263         /// Then no need to repeat.
1264       } else if (WorkSet.count(Node)) {
1265         break;
1266       } else {
1267         NodesOnPath.insert(Node);
1268       }
1269       Node = Node->getIDom();
1270     }
1271     if (SpillToRm) {
1272       SpillsToRm.push_back(SpillToRm);
1273     } else {
1274       // Add a BB containing the original spills to SpillsToKeep -- i.e.,
1275       // set the initial status before hoisting start. The value of BBs
1276       // containing original spills is set to 0, in order to descriminate
1277       // with BBs containing hoisted spills which will be inserted to
1278       // SpillsToKeep later during hoisting.
1279       SpillsToKeep[MDT[Block]] = 0;
1280       WorkSet.insert(NodesOnPath.begin(), NodesOnPath.end());
1281     }
1282     NodesOnPath.clear();
1283   }
1284 
1285   // Sort the nodes in WorkSet in top-down order and save the nodes
1286   // in Orders. Orders will be used for hoisting in runHoistSpills.
1287   unsigned idx = 0;
1288   Orders.push_back(MDT.getBase().getNode(Root));
1289   do {
1290     MachineDomTreeNode *Node = Orders[idx++];
1291     const std::vector<MachineDomTreeNode *> &Children = Node->getChildren();
1292     unsigned NumChildren = Children.size();
1293     for (unsigned i = 0; i != NumChildren; ++i) {
1294       MachineDomTreeNode *Child = Children[i];
1295       if (WorkSet.count(Child))
1296         Orders.push_back(Child);
1297     }
1298   } while (idx != Orders.size());
1299   assert(Orders.size() == WorkSet.size() &&
1300          "Orders have different size with WorkSet");
1301 
1302 #ifndef NDEBUG
1303   LLVM_DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n");
1304   SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
1305   for (; RIt != Orders.rend(); RIt++)
1306     LLVM_DEBUG(dbgs() << "BB" << (*RIt)->getBlock()->getNumber() << ",");
1307   LLVM_DEBUG(dbgs() << "\n");
1308 #endif
1309 }
1310 
1311 /// Try to hoist spills according to BB hotness. The spills to removed will
1312 /// be saved in \p SpillsToRm. The spills to be inserted will be saved in
1313 /// \p SpillsToIns.
1314 void HoistSpillHelper::runHoistSpills(
1315     LiveInterval &OrigLI, VNInfo &OrigVNI,
1316     SmallPtrSet<MachineInstr *, 16> &Spills,
1317     SmallVectorImpl<MachineInstr *> &SpillsToRm,
1318     DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns) {
1319   // Visit order of dominator tree nodes.
1320   SmallVector<MachineDomTreeNode *, 32> Orders;
1321   // SpillsToKeep contains all the nodes where spills are to be inserted
1322   // during hoisting. If the spill to be inserted is an original spill
1323   // (not a hoisted one), the value of the map entry is 0. If the spill
1324   // is a hoisted spill, the value of the map entry is the VReg to be used
1325   // as the source of the spill.
1326   DenseMap<MachineDomTreeNode *, unsigned> SpillsToKeep;
1327   // Map from BB to the first spill inside of it.
1328   DenseMap<MachineDomTreeNode *, MachineInstr *> SpillBBToSpill;
1329 
1330   rmRedundantSpills(Spills, SpillsToRm, SpillBBToSpill);
1331 
1332   MachineBasicBlock *Root = LIS.getMBBFromIndex(OrigVNI.def);
1333   getVisitOrders(Root, Spills, Orders, SpillsToRm, SpillsToKeep,
1334                  SpillBBToSpill);
1335 
1336   // SpillsInSubTreeMap keeps the map from a dom tree node to a pair of
1337   // nodes set and the cost of all the spills inside those nodes.
1338   // The nodes set are the locations where spills are to be inserted
1339   // in the subtree of current node.
1340   using NodesCostPair =
1341       std::pair<SmallPtrSet<MachineDomTreeNode *, 16>, BlockFrequency>;
1342   DenseMap<MachineDomTreeNode *, NodesCostPair> SpillsInSubTreeMap;
1343 
1344   // Iterate Orders set in reverse order, which will be a bottom-up order
1345   // in the dominator tree. Once we visit a dom tree node, we know its
1346   // children have already been visited and the spill locations in the
1347   // subtrees of all the children have been determined.
1348   SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
1349   for (; RIt != Orders.rend(); RIt++) {
1350     MachineBasicBlock *Block = (*RIt)->getBlock();
1351 
1352     // If Block contains an original spill, simply continue.
1353     if (SpillsToKeep.find(*RIt) != SpillsToKeep.end() && !SpillsToKeep[*RIt]) {
1354       SpillsInSubTreeMap[*RIt].first.insert(*RIt);
1355       // SpillsInSubTreeMap[*RIt].second contains the cost of spill.
1356       SpillsInSubTreeMap[*RIt].second = MBFI.getBlockFreq(Block);
1357       continue;
1358     }
1359 
1360     // Collect spills in subtree of current node (*RIt) to
1361     // SpillsInSubTreeMap[*RIt].first.
1362     const std::vector<MachineDomTreeNode *> &Children = (*RIt)->getChildren();
1363     unsigned NumChildren = Children.size();
1364     for (unsigned i = 0; i != NumChildren; ++i) {
1365       MachineDomTreeNode *Child = Children[i];
1366       if (SpillsInSubTreeMap.find(Child) == SpillsInSubTreeMap.end())
1367         continue;
1368       // The stmt "SpillsInSubTree = SpillsInSubTreeMap[*RIt].first" below
1369       // should be placed before getting the begin and end iterators of
1370       // SpillsInSubTreeMap[Child].first, or else the iterators may be
1371       // invalidated when SpillsInSubTreeMap[*RIt] is seen the first time
1372       // and the map grows and then the original buckets in the map are moved.
1373       SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree =
1374           SpillsInSubTreeMap[*RIt].first;
1375       BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second;
1376       SubTreeCost += SpillsInSubTreeMap[Child].second;
1377       auto BI = SpillsInSubTreeMap[Child].first.begin();
1378       auto EI = SpillsInSubTreeMap[Child].first.end();
1379       SpillsInSubTree.insert(BI, EI);
1380       SpillsInSubTreeMap.erase(Child);
1381     }
1382 
1383     SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree =
1384           SpillsInSubTreeMap[*RIt].first;
1385     BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second;
1386     // No spills in subtree, simply continue.
1387     if (SpillsInSubTree.empty())
1388       continue;
1389 
1390     // Check whether Block is a possible candidate to insert spill.
1391     unsigned LiveReg = 0;
1392     if (!isSpillCandBB(OrigLI, OrigVNI, *Block, LiveReg))
1393       continue;
1394 
1395     // If there are multiple spills that could be merged, bias a little
1396     // to hoist the spill.
1397     BranchProbability MarginProb = (SpillsInSubTree.size() > 1)
1398                                        ? BranchProbability(9, 10)
1399                                        : BranchProbability(1, 1);
1400     if (SubTreeCost > MBFI.getBlockFreq(Block) * MarginProb) {
1401       // Hoist: Move spills to current Block.
1402       for (const auto SpillBB : SpillsInSubTree) {
1403         // When SpillBB is a BB contains original spill, insert the spill
1404         // to SpillsToRm.
1405         if (SpillsToKeep.find(SpillBB) != SpillsToKeep.end() &&
1406             !SpillsToKeep[SpillBB]) {
1407           MachineInstr *SpillToRm = SpillBBToSpill[SpillBB];
1408           SpillsToRm.push_back(SpillToRm);
1409         }
1410         // SpillBB will not contain spill anymore, remove it from SpillsToKeep.
1411         SpillsToKeep.erase(SpillBB);
1412       }
1413       // Current Block is the BB containing the new hoisted spill. Add it to
1414       // SpillsToKeep. LiveReg is the source of the new spill.
1415       SpillsToKeep[*RIt] = LiveReg;
1416       LLVM_DEBUG({
1417         dbgs() << "spills in BB: ";
1418         for (const auto Rspill : SpillsInSubTree)
1419           dbgs() << Rspill->getBlock()->getNumber() << " ";
1420         dbgs() << "were promoted to BB" << (*RIt)->getBlock()->getNumber()
1421                << "\n";
1422       });
1423       SpillsInSubTree.clear();
1424       SpillsInSubTree.insert(*RIt);
1425       SubTreeCost = MBFI.getBlockFreq(Block);
1426     }
1427   }
1428   // For spills in SpillsToKeep with LiveReg set (i.e., not original spill),
1429   // save them to SpillsToIns.
1430   for (const auto &Ent : SpillsToKeep) {
1431     if (Ent.second)
1432       SpillsToIns[Ent.first->getBlock()] = Ent.second;
1433   }
1434 }
1435 
1436 /// For spills with equal values, remove redundant spills and hoist those left
1437 /// to less hot spots.
1438 ///
1439 /// Spills with equal values will be collected into the same set in
1440 /// MergeableSpills when spill is inserted. These equal spills are originated
1441 /// from the same defining instruction and are dominated by the instruction.
1442 /// Before hoisting all the equal spills, redundant spills inside in the same
1443 /// BB are first marked to be deleted. Then starting from the spills left, walk
1444 /// up on the dominator tree towards the Root node where the define instruction
1445 /// is located, mark the dominated spills to be deleted along the way and
1446 /// collect the BB nodes on the path from non-dominated spills to the define
1447 /// instruction into a WorkSet. The nodes in WorkSet are the candidate places
1448 /// where we are considering to hoist the spills. We iterate the WorkSet in
1449 /// bottom-up order, and for each node, we will decide whether to hoist spills
1450 /// inside its subtree to that node. In this way, we can get benefit locally
1451 /// even if hoisting all the equal spills to one cold place is impossible.
1452 void HoistSpillHelper::hoistAllSpills() {
1453   SmallVector<unsigned, 4> NewVRegs;
1454   LiveRangeEdit Edit(nullptr, NewVRegs, MF, LIS, &VRM, this);
1455 
1456   for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
1457     unsigned Reg = Register::index2VirtReg(i);
1458     unsigned Original = VRM.getPreSplitReg(Reg);
1459     if (!MRI.def_empty(Reg))
1460       Virt2SiblingsMap[Original].insert(Reg);
1461   }
1462 
1463   // Each entry in MergeableSpills contains a spill set with equal values.
1464   for (auto &Ent : MergeableSpills) {
1465     int Slot = Ent.first.first;
1466     LiveInterval &OrigLI = *StackSlotToOrigLI[Slot];
1467     VNInfo *OrigVNI = Ent.first.second;
1468     SmallPtrSet<MachineInstr *, 16> &EqValSpills = Ent.second;
1469     if (Ent.second.empty())
1470       continue;
1471 
1472     LLVM_DEBUG({
1473       dbgs() << "\nFor Slot" << Slot << " and VN" << OrigVNI->id << ":\n"
1474              << "Equal spills in BB: ";
1475       for (const auto spill : EqValSpills)
1476         dbgs() << spill->getParent()->getNumber() << " ";
1477       dbgs() << "\n";
1478     });
1479 
1480     // SpillsToRm is the spill set to be removed from EqValSpills.
1481     SmallVector<MachineInstr *, 16> SpillsToRm;
1482     // SpillsToIns is the spill set to be newly inserted after hoisting.
1483     DenseMap<MachineBasicBlock *, unsigned> SpillsToIns;
1484 
1485     runHoistSpills(OrigLI, *OrigVNI, EqValSpills, SpillsToRm, SpillsToIns);
1486 
1487     LLVM_DEBUG({
1488       dbgs() << "Finally inserted spills in BB: ";
1489       for (const auto &Ispill : SpillsToIns)
1490         dbgs() << Ispill.first->getNumber() << " ";
1491       dbgs() << "\nFinally removed spills in BB: ";
1492       for (const auto Rspill : SpillsToRm)
1493         dbgs() << Rspill->getParent()->getNumber() << " ";
1494       dbgs() << "\n";
1495     });
1496 
1497     // Stack live range update.
1498     LiveInterval &StackIntvl = LSS.getInterval(Slot);
1499     if (!SpillsToIns.empty() || !SpillsToRm.empty())
1500       StackIntvl.MergeValueInAsValue(OrigLI, OrigVNI,
1501                                      StackIntvl.getValNumInfo(0));
1502 
1503     // Insert hoisted spills.
1504     for (auto const &Insert : SpillsToIns) {
1505       MachineBasicBlock *BB = Insert.first;
1506       unsigned LiveReg = Insert.second;
1507       MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, *BB);
1508       TII.storeRegToStackSlot(*BB, MI, LiveReg, false, Slot,
1509                               MRI.getRegClass(LiveReg), &TRI);
1510       LIS.InsertMachineInstrRangeInMaps(std::prev(MI), MI);
1511       ++NumSpills;
1512     }
1513 
1514     // Remove redundant spills or change them to dead instructions.
1515     NumSpills -= SpillsToRm.size();
1516     for (auto const RMEnt : SpillsToRm) {
1517       RMEnt->setDesc(TII.get(TargetOpcode::KILL));
1518       for (unsigned i = RMEnt->getNumOperands(); i; --i) {
1519         MachineOperand &MO = RMEnt->getOperand(i - 1);
1520         if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())
1521           RMEnt->RemoveOperand(i - 1);
1522       }
1523     }
1524     Edit.eliminateDeadDefs(SpillsToRm, None, AA);
1525   }
1526 }
1527 
1528 /// For VirtReg clone, the \p New register should have the same physreg or
1529 /// stackslot as the \p old register.
1530 void HoistSpillHelper::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
1531   if (VRM.hasPhys(Old))
1532     VRM.assignVirt2Phys(New, VRM.getPhys(Old));
1533   else if (VRM.getStackSlot(Old) != VirtRegMap::NO_STACK_SLOT)
1534     VRM.assignVirt2StackSlot(New, VRM.getStackSlot(Old));
1535   else
1536     llvm_unreachable("VReg should be assigned either physreg or stackslot");
1537 }
1538