1 //===- LiveIntervalUnion.cpp - Live interval union data structure ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // LiveIntervalUnion represents a coalesced set of live intervals. This may be
10 // used during coalescing to represent a congruence class, or during register
11 // allocation to model liveness of a physical register.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/LiveIntervalUnion.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SparseBitVector.h"
18 #include "llvm/CodeGen/LiveInterval.h"
19 #include "llvm/CodeGen/TargetRegisterInfo.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include <cassert>
22 #include <cstdlib>
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "regalloc"
27 
28 // Merge a LiveInterval's segments. Guarantee no overlaps.
29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) {
30   if (Range.empty())
31     return;
32   ++Tag;
33 
34   // Insert each of the virtual register's live segments into the map.
35   LiveRange::const_iterator RegPos = Range.begin();
36   LiveRange::const_iterator RegEnd = Range.end();
37   SegmentIter SegPos = Segments.find(RegPos->start);
38 
39   while (SegPos.valid()) {
40     SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
41     if (++RegPos == RegEnd)
42       return;
43     SegPos.advanceTo(RegPos->start);
44   }
45 
46   // We have reached the end of Segments, so it is no longer necessary to search
47   // for the insertion position.
48   // It is faster to insert the end first.
49   --RegEnd;
50   SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
51   for (; RegPos != RegEnd; ++RegPos, ++SegPos)
52     SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
53 }
54 
55 // Remove a live virtual register's segments from this union.
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) {
57   if (Range.empty())
58     return;
59   ++Tag;
60 
61   // Remove each of the virtual register's live segments from the map.
62   LiveRange::const_iterator RegPos = Range.begin();
63   LiveRange::const_iterator RegEnd = Range.end();
64   SegmentIter SegPos = Segments.find(RegPos->start);
65 
66   while (true) {
67     assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
68     SegPos.erase();
69     if (!SegPos.valid())
70       return;
71 
72     // Skip all segments that may have been coalesced.
73     RegPos = Range.advanceTo(RegPos, SegPos.start());
74     if (RegPos == RegEnd)
75       return;
76 
77     SegPos.advanceTo(RegPos->start);
78   }
79 }
80 
81 void
82 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
83   if (empty()) {
84     OS << " empty\n";
85     return;
86   }
87   for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
88     OS << " [" << SI.start() << ' ' << SI.stop()
89        << "):" << printReg(SI.value()->reg(), TRI);
90   }
91   OS << '\n';
92 }
93 
94 #ifndef NDEBUG
95 // Verify the live intervals in this union and add them to the visited set.
96 void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
97   for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
98     VisitedVRegs.set(SI.value()->reg());
99 }
100 #endif //!NDEBUG
101 
102 LiveInterval *LiveIntervalUnion::getOneVReg() const {
103   if (empty())
104     return nullptr;
105   for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
106     // return the first valid live interval
107     return SI.value();
108   }
109   return nullptr;
110 }
111 
112 // Scan the vector of interfering virtual registers in this union. Assume it's
113 // quite small.
114 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
115   return is_contained(*InterferingVRegs, VirtReg);
116 }
117 
118 // Collect virtual registers in this union that interfere with this
119 // query's live virtual register.
120 //
121 // The query state is one of:
122 //
123 // 1. CheckedFirstInterference == false: Iterators are uninitialized.
124 // 2. SeenAllInterferences == true: InterferingVRegs complete, iterators unused.
125 // 3. Iterators left at the last seen intersection.
126 //
127 unsigned LiveIntervalUnion::Query::
128 collectInterferingVRegs(unsigned MaxInterferingRegs) {
129   if (!InterferingVRegs)
130     InterferingVRegs.emplace();
131 
132   // Fast path return if we already have the desired information.
133   if (SeenAllInterferences || InterferingVRegs->size() >= MaxInterferingRegs)
134     return InterferingVRegs->size();
135 
136   // Set up iterators on the first call.
137   if (!CheckedFirstInterference) {
138     CheckedFirstInterference = true;
139 
140     // Quickly skip interference check for empty sets.
141     if (LR->empty() || LiveUnion->empty()) {
142       SeenAllInterferences = true;
143       return 0;
144     }
145 
146     // In most cases, the union will start before LR.
147     LRI = LR->begin();
148     LiveUnionI.setMap(LiveUnion->getMap());
149     LiveUnionI.find(LRI->start);
150   }
151 
152   LiveRange::const_iterator LREnd = LR->end();
153   LiveInterval *RecentReg = nullptr;
154   while (LiveUnionI.valid()) {
155     assert(LRI != LREnd && "Reached end of LR");
156 
157     // Check for overlapping interference.
158     while (LRI->start < LiveUnionI.stop() && LRI->end > LiveUnionI.start()) {
159       // This is an overlap, record the interfering register.
160       LiveInterval *VReg = LiveUnionI.value();
161       if (VReg != RecentReg && !isSeenInterference(VReg)) {
162         RecentReg = VReg;
163         InterferingVRegs->push_back(VReg);
164         if (InterferingVRegs->size() >= MaxInterferingRegs)
165           return InterferingVRegs->size();
166       }
167       // This LiveUnion segment is no longer interesting.
168       if (!(++LiveUnionI).valid()) {
169         SeenAllInterferences = true;
170         return InterferingVRegs->size();
171       }
172     }
173 
174     // The iterators are now not overlapping, LiveUnionI has been advanced
175     // beyond LRI.
176     assert(LRI->end <= LiveUnionI.start() && "Expected non-overlap");
177 
178     // Advance the iterator that ends first.
179     LRI = LR->advanceTo(LRI, LiveUnionI.start());
180     if (LRI == LREnd)
181       break;
182 
183     // Detect overlap, handle above.
184     if (LRI->start < LiveUnionI.stop())
185       continue;
186 
187     // Still not overlapping. Catch up LiveUnionI.
188     LiveUnionI.advanceTo(LRI->start);
189   }
190   SeenAllInterferences = true;
191   return InterferingVRegs->size();
192 }
193 
194 void LiveIntervalUnion::Array::init(LiveIntervalUnion::Allocator &Alloc,
195                                     unsigned NSize) {
196   // Reuse existing allocation.
197   if (NSize == Size)
198     return;
199   clear();
200   Size = NSize;
201   LIUs = static_cast<LiveIntervalUnion*>(
202       safe_malloc(sizeof(LiveIntervalUnion)*NSize));
203   for (unsigned i = 0; i != Size; ++i)
204     new(LIUs + i) LiveIntervalUnion(Alloc);
205 }
206 
207 void LiveIntervalUnion::Array::clear() {
208   if (!LIUs)
209     return;
210   for (unsigned i = 0; i != Size; ++i)
211     LIUs[i].~LiveIntervalUnion();
212   free(LIUs);
213   Size =  0;
214   LIUs = nullptr;
215 }
216