1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the class that prints out the LLVM IR and machine
10 // functions using the MIR serialization format.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/MIRPrinter.h"
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/None.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallBitVector.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
24 #include "llvm/CodeGen/MIRYamlMapping.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/TargetInstrInfo.h"
36 #include "llvm/CodeGen/TargetRegisterInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/CodeGen/TargetFrameLowering.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/IRPrintingPasses.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/IR/ModuleSlotTracker.h"
51 #include "llvm/IR/Value.h"
52 #include "llvm/MC/LaneBitmask.h"
53 #include "llvm/MC/MCContext.h"
54 #include "llvm/MC/MCDwarf.h"
55 #include "llvm/MC/MCSymbol.h"
56 #include "llvm/Support/AtomicOrdering.h"
57 #include "llvm/Support/BranchProbability.h"
58 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/CommandLine.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/Format.h"
62 #include "llvm/Support/LowLevelTypeImpl.h"
63 #include "llvm/Support/YAMLTraits.h"
64 #include "llvm/Support/raw_ostream.h"
65 #include "llvm/Target/TargetIntrinsicInfo.h"
66 #include "llvm/Target/TargetMachine.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cinttypes>
70 #include <cstdint>
71 #include <iterator>
72 #include <string>
73 #include <utility>
74 #include <vector>
75 
76 using namespace llvm;
77 
78 static cl::opt<bool> SimplifyMIR(
79     "simplify-mir", cl::Hidden,
80     cl::desc("Leave out unnecessary information when printing MIR"));
81 
82 namespace {
83 
84 /// This structure describes how to print out stack object references.
85 struct FrameIndexOperand {
86   std::string Name;
87   unsigned ID;
88   bool IsFixed;
89 
90   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
91       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
92 
93   /// Return an ordinary stack object reference.
94   static FrameIndexOperand create(StringRef Name, unsigned ID) {
95     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
96   }
97 
98   /// Return a fixed stack object reference.
99   static FrameIndexOperand createFixed(unsigned ID) {
100     return FrameIndexOperand("", ID, /*IsFixed=*/true);
101   }
102 };
103 
104 } // end anonymous namespace
105 
106 namespace llvm {
107 
108 /// This class prints out the machine functions using the MIR serialization
109 /// format.
110 class MIRPrinter {
111   raw_ostream &OS;
112   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
113   /// Maps from stack object indices to operand indices which will be used when
114   /// printing frame index machine operands.
115   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
116 
117 public:
118   MIRPrinter(raw_ostream &OS) : OS(OS) {}
119 
120   void print(const MachineFunction &MF);
121 
122   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
123                const TargetRegisterInfo *TRI);
124   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
125                const MachineFrameInfo &MFI);
126   void convert(yaml::MachineFunction &MF,
127                const MachineConstantPool &ConstantPool);
128   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
129                const MachineJumpTableInfo &JTI);
130   void convertStackObjects(yaml::MachineFunction &YMF,
131                            const MachineFunction &MF, ModuleSlotTracker &MST);
132   void convertCallSiteObjects(yaml::MachineFunction &YMF,
133                               const MachineFunction &MF,
134                               ModuleSlotTracker &MST);
135 
136 private:
137   void initRegisterMaskIds(const MachineFunction &MF);
138 };
139 
140 /// This class prints out the machine instructions using the MIR serialization
141 /// format.
142 class MIPrinter {
143   raw_ostream &OS;
144   ModuleSlotTracker &MST;
145   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
146   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
147   /// Synchronization scope names registered with LLVMContext.
148   SmallVector<StringRef, 8> SSNs;
149 
150   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
151   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
152 
153 public:
154   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
155             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
156             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
157       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
158         StackObjectOperandMapping(StackObjectOperandMapping) {}
159 
160   void print(const MachineBasicBlock &MBB);
161 
162   void print(const MachineInstr &MI);
163   void printStackObjectReference(int FrameIndex);
164   void print(const MachineInstr &MI, unsigned OpIdx,
165              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
166              LLT TypeToPrint, bool PrintDef = true);
167 };
168 
169 } // end namespace llvm
170 
171 namespace llvm {
172 namespace yaml {
173 
174 /// This struct serializes the LLVM IR module.
175 template <> struct BlockScalarTraits<Module> {
176   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
177     Mod.print(OS, nullptr);
178   }
179 
180   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
181     llvm_unreachable("LLVM Module is supposed to be parsed separately");
182     return "";
183   }
184 };
185 
186 } // end namespace yaml
187 } // end namespace llvm
188 
189 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
190                         const TargetRegisterInfo *TRI) {
191   raw_string_ostream OS(Dest.Value);
192   OS << printReg(Reg, TRI);
193 }
194 
195 void MIRPrinter::print(const MachineFunction &MF) {
196   initRegisterMaskIds(MF);
197 
198   yaml::MachineFunction YamlMF;
199   YamlMF.Name = MF.getName();
200   YamlMF.Alignment = MF.getAlignment().value();
201   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
202   YamlMF.HasWinCFI = MF.hasWinCFI();
203 
204   YamlMF.Legalized = MF.getProperties().hasProperty(
205       MachineFunctionProperties::Property::Legalized);
206   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
207       MachineFunctionProperties::Property::RegBankSelected);
208   YamlMF.Selected = MF.getProperties().hasProperty(
209       MachineFunctionProperties::Property::Selected);
210   YamlMF.FailedISel = MF.getProperties().hasProperty(
211       MachineFunctionProperties::Property::FailedISel);
212 
213   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
214   ModuleSlotTracker MST(MF.getFunction().getParent());
215   MST.incorporateFunction(MF.getFunction());
216   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
217   convertStackObjects(YamlMF, MF, MST);
218   convertCallSiteObjects(YamlMF, MF, MST);
219   if (const auto *ConstantPool = MF.getConstantPool())
220     convert(YamlMF, *ConstantPool);
221   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
222     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
223 
224   const TargetMachine &TM = MF.getTarget();
225   YamlMF.MachineFuncInfo =
226       std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF));
227 
228   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
229   bool IsNewlineNeeded = false;
230   for (const auto &MBB : MF) {
231     if (IsNewlineNeeded)
232       StrOS << "\n";
233     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
234         .print(MBB);
235     IsNewlineNeeded = true;
236   }
237   StrOS.flush();
238   yaml::Output Out(OS);
239   if (!SimplifyMIR)
240       Out.setWriteDefaultValues(true);
241   Out << YamlMF;
242 }
243 
244 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
245                                const TargetRegisterInfo *TRI) {
246   assert(RegMask && "Can't print an empty register mask");
247   OS << StringRef("CustomRegMask(");
248 
249   bool IsRegInRegMaskFound = false;
250   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
251     // Check whether the register is asserted in regmask.
252     if (RegMask[I / 32] & (1u << (I % 32))) {
253       if (IsRegInRegMaskFound)
254         OS << ',';
255       OS << printReg(I, TRI);
256       IsRegInRegMaskFound = true;
257     }
258   }
259 
260   OS << ')';
261 }
262 
263 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
264                                 const MachineRegisterInfo &RegInfo,
265                                 const TargetRegisterInfo *TRI) {
266   raw_string_ostream OS(Dest.Value);
267   OS << printRegClassOrBank(Reg, RegInfo, TRI);
268 }
269 
270 template <typename T>
271 static void
272 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
273                         T &Object, ModuleSlotTracker &MST) {
274   std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
275                                         &Object.DebugExpr.Value,
276                                         &Object.DebugLoc.Value}};
277   std::array<const Metadata *, 3> Metas{{DebugVar.Var,
278                                         DebugVar.Expr,
279                                         DebugVar.Loc}};
280   for (unsigned i = 0; i < 3; ++i) {
281     raw_string_ostream StrOS(*Outputs[i]);
282     Metas[i]->printAsOperand(StrOS, MST);
283   }
284 }
285 
286 void MIRPrinter::convert(yaml::MachineFunction &MF,
287                          const MachineRegisterInfo &RegInfo,
288                          const TargetRegisterInfo *TRI) {
289   MF.TracksRegLiveness = RegInfo.tracksLiveness();
290 
291   // Print the virtual register definitions.
292   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
293     unsigned Reg = Register::index2VirtReg(I);
294     yaml::VirtualRegisterDefinition VReg;
295     VReg.ID = I;
296     if (RegInfo.getVRegName(Reg) != "")
297       continue;
298     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
299     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
300     if (PreferredReg)
301       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
302     MF.VirtualRegisters.push_back(VReg);
303   }
304 
305   // Print the live ins.
306   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
307     yaml::MachineFunctionLiveIn LiveIn;
308     printRegMIR(LI.first, LiveIn.Register, TRI);
309     if (LI.second)
310       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
311     MF.LiveIns.push_back(LiveIn);
312   }
313 
314   // Prints the callee saved registers.
315   if (RegInfo.isUpdatedCSRsInitialized()) {
316     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
317     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
318     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
319       yaml::FlowStringValue Reg;
320       printRegMIR(*I, Reg, TRI);
321       CalleeSavedRegisters.push_back(Reg);
322     }
323     MF.CalleeSavedRegisters = CalleeSavedRegisters;
324   }
325 }
326 
327 void MIRPrinter::convert(ModuleSlotTracker &MST,
328                          yaml::MachineFrameInfo &YamlMFI,
329                          const MachineFrameInfo &MFI) {
330   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
331   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
332   YamlMFI.HasStackMap = MFI.hasStackMap();
333   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
334   YamlMFI.StackSize = MFI.getStackSize();
335   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
336   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
337   YamlMFI.AdjustsStack = MFI.adjustsStack();
338   YamlMFI.HasCalls = MFI.hasCalls();
339   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
340     ? MFI.getMaxCallFrameSize() : ~0u;
341   YamlMFI.CVBytesOfCalleeSavedRegisters =
342       MFI.getCVBytesOfCalleeSavedRegisters();
343   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
344   YamlMFI.HasVAStart = MFI.hasVAStart();
345   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
346   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
347   if (MFI.getSavePoint()) {
348     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
349     StrOS << printMBBReference(*MFI.getSavePoint());
350   }
351   if (MFI.getRestorePoint()) {
352     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
353     StrOS << printMBBReference(*MFI.getRestorePoint());
354   }
355 }
356 
357 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
358                                      const MachineFunction &MF,
359                                      ModuleSlotTracker &MST) {
360   const MachineFrameInfo &MFI = MF.getFrameInfo();
361   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
362   // Process fixed stack objects.
363   unsigned ID = 0;
364   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I, ++ID) {
365     if (MFI.isDeadObjectIndex(I))
366       continue;
367 
368     yaml::FixedMachineStackObject YamlObject;
369     YamlObject.ID = ID;
370     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
371                           ? yaml::FixedMachineStackObject::SpillSlot
372                           : yaml::FixedMachineStackObject::DefaultType;
373     YamlObject.Offset = MFI.getObjectOffset(I);
374     YamlObject.Size = MFI.getObjectSize(I);
375     YamlObject.Alignment = MFI.getObjectAlignment(I);
376     YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
377     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
378     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
379     YMF.FixedStackObjects.push_back(YamlObject);
380     StackObjectOperandMapping.insert(
381         std::make_pair(I, FrameIndexOperand::createFixed(ID)));
382   }
383 
384   // Process ordinary stack objects.
385   ID = 0;
386   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I, ++ID) {
387     if (MFI.isDeadObjectIndex(I))
388       continue;
389 
390     yaml::MachineStackObject YamlObject;
391     YamlObject.ID = ID;
392     if (const auto *Alloca = MFI.getObjectAllocation(I))
393       YamlObject.Name.Value =
394           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
395     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
396                           ? yaml::MachineStackObject::SpillSlot
397                           : MFI.isVariableSizedObjectIndex(I)
398                                 ? yaml::MachineStackObject::VariableSized
399                                 : yaml::MachineStackObject::DefaultType;
400     YamlObject.Offset = MFI.getObjectOffset(I);
401     YamlObject.Size = MFI.getObjectSize(I);
402     YamlObject.Alignment = MFI.getObjectAlignment(I);
403     YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
404 
405     YMF.StackObjects.push_back(YamlObject);
406     StackObjectOperandMapping.insert(std::make_pair(
407         I, FrameIndexOperand::create(YamlObject.Name.Value, ID)));
408   }
409 
410   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
411     if (!CSInfo.isSpilledToReg() && MFI.isDeadObjectIndex(CSInfo.getFrameIdx()))
412       continue;
413 
414     yaml::StringValue Reg;
415     printRegMIR(CSInfo.getReg(), Reg, TRI);
416     if (!CSInfo.isSpilledToReg()) {
417       auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
418       assert(StackObjectInfo != StackObjectOperandMapping.end() &&
419              "Invalid stack object index");
420       const FrameIndexOperand &StackObject = StackObjectInfo->second;
421       if (StackObject.IsFixed) {
422         YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
423         YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
424           CSInfo.isRestored();
425       } else {
426         YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
427         YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
428           CSInfo.isRestored();
429       }
430     }
431   }
432   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
433     auto LocalObject = MFI.getLocalFrameObjectMap(I);
434     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
435     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
436            "Invalid stack object index");
437     const FrameIndexOperand &StackObject = StackObjectInfo->second;
438     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
439     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
440   }
441 
442   // Print the stack object references in the frame information class after
443   // converting the stack objects.
444   if (MFI.hasStackProtectorIndex()) {
445     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
446     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
447         .printStackObjectReference(MFI.getStackProtectorIndex());
448   }
449 
450   // Print the debug variable information.
451   for (const MachineFunction::VariableDbgInfo &DebugVar :
452        MF.getVariableDbgInfo()) {
453     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
454     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
455            "Invalid stack object index");
456     const FrameIndexOperand &StackObject = StackObjectInfo->second;
457     if (StackObject.IsFixed) {
458       auto &Object = YMF.FixedStackObjects[StackObject.ID];
459       printStackObjectDbgInfo(DebugVar, Object, MST);
460     } else {
461       auto &Object = YMF.StackObjects[StackObject.ID];
462       printStackObjectDbgInfo(DebugVar, Object, MST);
463     }
464   }
465 }
466 
467 void MIRPrinter::convertCallSiteObjects(yaml::MachineFunction &YMF,
468                                         const MachineFunction &MF,
469                                         ModuleSlotTracker &MST) {
470   const auto *TRI = MF.getSubtarget().getRegisterInfo();
471   for (auto CSInfo : MF.getCallSitesInfo()) {
472     yaml::CallSiteInfo YmlCS;
473     yaml::CallSiteInfo::MachineInstrLoc CallLocation;
474 
475     // Prepare instruction position.
476     MachineBasicBlock::const_instr_iterator CallI = CSInfo.first->getIterator();
477     CallLocation.BlockNum = CallI->getParent()->getNumber();
478     // Get call instruction offset from the beginning of block.
479     CallLocation.Offset =
480         std::distance(CallI->getParent()->instr_begin(), CallI);
481     YmlCS.CallLocation = CallLocation;
482     // Construct call arguments and theirs forwarding register info.
483     for (auto ArgReg : CSInfo.second) {
484       yaml::CallSiteInfo::ArgRegPair YmlArgReg;
485       YmlArgReg.ArgNo = ArgReg.ArgNo;
486       printRegMIR(ArgReg.Reg, YmlArgReg.Reg, TRI);
487       YmlCS.ArgForwardingRegs.emplace_back(YmlArgReg);
488     }
489     YMF.CallSitesInfo.push_back(YmlCS);
490   }
491 
492   // Sort call info by position of call instructions.
493   llvm::sort(YMF.CallSitesInfo.begin(), YMF.CallSitesInfo.end(),
494              [](yaml::CallSiteInfo A, yaml::CallSiteInfo B) {
495                if (A.CallLocation.BlockNum == B.CallLocation.BlockNum)
496                  return A.CallLocation.Offset < B.CallLocation.Offset;
497                return A.CallLocation.BlockNum < B.CallLocation.BlockNum;
498              });
499 }
500 
501 void MIRPrinter::convert(yaml::MachineFunction &MF,
502                          const MachineConstantPool &ConstantPool) {
503   unsigned ID = 0;
504   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
505     std::string Str;
506     raw_string_ostream StrOS(Str);
507     if (Constant.isMachineConstantPoolEntry()) {
508       Constant.Val.MachineCPVal->print(StrOS);
509     } else {
510       Constant.Val.ConstVal->printAsOperand(StrOS);
511     }
512 
513     yaml::MachineConstantPoolValue YamlConstant;
514     YamlConstant.ID = ID++;
515     YamlConstant.Value = StrOS.str();
516     YamlConstant.Alignment = Constant.getAlignment();
517     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
518 
519     MF.Constants.push_back(YamlConstant);
520   }
521 }
522 
523 void MIRPrinter::convert(ModuleSlotTracker &MST,
524                          yaml::MachineJumpTable &YamlJTI,
525                          const MachineJumpTableInfo &JTI) {
526   YamlJTI.Kind = JTI.getEntryKind();
527   unsigned ID = 0;
528   for (const auto &Table : JTI.getJumpTables()) {
529     std::string Str;
530     yaml::MachineJumpTable::Entry Entry;
531     Entry.ID = ID++;
532     for (const auto *MBB : Table.MBBs) {
533       raw_string_ostream StrOS(Str);
534       StrOS << printMBBReference(*MBB);
535       Entry.Blocks.push_back(StrOS.str());
536       Str.clear();
537     }
538     YamlJTI.Entries.push_back(Entry);
539   }
540 }
541 
542 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
543   const auto *TRI = MF.getSubtarget().getRegisterInfo();
544   unsigned I = 0;
545   for (const uint32_t *Mask : TRI->getRegMasks())
546     RegisterMaskIds.insert(std::make_pair(Mask, I++));
547 }
548 
549 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
550                            SmallVectorImpl<MachineBasicBlock*> &Result,
551                            bool &IsFallthrough) {
552   SmallPtrSet<MachineBasicBlock*,8> Seen;
553 
554   for (const MachineInstr &MI : MBB) {
555     if (MI.isPHI())
556       continue;
557     for (const MachineOperand &MO : MI.operands()) {
558       if (!MO.isMBB())
559         continue;
560       MachineBasicBlock *Succ = MO.getMBB();
561       auto RP = Seen.insert(Succ);
562       if (RP.second)
563         Result.push_back(Succ);
564     }
565   }
566   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
567   IsFallthrough = I == MBB.end() || !I->isBarrier();
568 }
569 
570 bool
571 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
572   if (MBB.succ_size() <= 1)
573     return true;
574   if (!MBB.hasSuccessorProbabilities())
575     return true;
576 
577   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
578                                               MBB.Probs.end());
579   BranchProbability::normalizeProbabilities(Normalized.begin(),
580                                             Normalized.end());
581   SmallVector<BranchProbability,8> Equal(Normalized.size());
582   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
583 
584   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
585 }
586 
587 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
588   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
589   bool GuessedFallthrough;
590   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
591   if (GuessedFallthrough) {
592     const MachineFunction &MF = *MBB.getParent();
593     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
594     if (NextI != MF.end()) {
595       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
596       if (!is_contained(GuessedSuccs, Next))
597         GuessedSuccs.push_back(Next);
598     }
599   }
600   if (GuessedSuccs.size() != MBB.succ_size())
601     return false;
602   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
603 }
604 
605 void MIPrinter::print(const MachineBasicBlock &MBB) {
606   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
607   OS << "bb." << MBB.getNumber();
608   bool HasAttributes = false;
609   if (const auto *BB = MBB.getBasicBlock()) {
610     if (BB->hasName()) {
611       OS << "." << BB->getName();
612     } else {
613       HasAttributes = true;
614       OS << " (";
615       int Slot = MST.getLocalSlot(BB);
616       if (Slot == -1)
617         OS << "<ir-block badref>";
618       else
619         OS << (Twine("%ir-block.") + Twine(Slot)).str();
620     }
621   }
622   if (MBB.hasAddressTaken()) {
623     OS << (HasAttributes ? ", " : " (");
624     OS << "address-taken";
625     HasAttributes = true;
626   }
627   if (MBB.isEHPad()) {
628     OS << (HasAttributes ? ", " : " (");
629     OS << "landing-pad";
630     HasAttributes = true;
631   }
632   if (MBB.getAlignment() != Align::None()) {
633     OS << (HasAttributes ? ", " : " (");
634     OS << "align " << MBB.getAlignment().value();
635     HasAttributes = true;
636   }
637   if (HasAttributes)
638     OS << ")";
639   OS << ":\n";
640 
641   bool HasLineAttributes = false;
642   // Print the successors
643   bool canPredictProbs = canPredictBranchProbabilities(MBB);
644   // Even if the list of successors is empty, if we cannot guess it,
645   // we need to print it to tell the parser that the list is empty.
646   // This is needed, because MI model unreachable as empty blocks
647   // with an empty successor list. If the parser would see that
648   // without the successor list, it would guess the code would
649   // fallthrough.
650   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
651       !canPredictSuccessors(MBB)) {
652     OS.indent(2) << "successors: ";
653     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
654       if (I != MBB.succ_begin())
655         OS << ", ";
656       OS << printMBBReference(**I);
657       if (!SimplifyMIR || !canPredictProbs)
658         OS << '('
659            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
660            << ')';
661     }
662     OS << "\n";
663     HasLineAttributes = true;
664   }
665 
666   // Print the live in registers.
667   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
668   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
669     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
670     OS.indent(2) << "liveins: ";
671     bool First = true;
672     for (const auto &LI : MBB.liveins()) {
673       if (!First)
674         OS << ", ";
675       First = false;
676       OS << printReg(LI.PhysReg, &TRI);
677       if (!LI.LaneMask.all())
678         OS << ":0x" << PrintLaneMask(LI.LaneMask);
679     }
680     OS << "\n";
681     HasLineAttributes = true;
682   }
683 
684   if (HasLineAttributes)
685     OS << "\n";
686   bool IsInBundle = false;
687   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
688     const MachineInstr &MI = *I;
689     if (IsInBundle && !MI.isInsideBundle()) {
690       OS.indent(2) << "}\n";
691       IsInBundle = false;
692     }
693     OS.indent(IsInBundle ? 4 : 2);
694     print(MI);
695     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
696       OS << " {";
697       IsInBundle = true;
698     }
699     OS << "\n";
700   }
701   if (IsInBundle)
702     OS.indent(2) << "}\n";
703 }
704 
705 void MIPrinter::print(const MachineInstr &MI) {
706   const auto *MF = MI.getMF();
707   const auto &MRI = MF->getRegInfo();
708   const auto &SubTarget = MF->getSubtarget();
709   const auto *TRI = SubTarget.getRegisterInfo();
710   assert(TRI && "Expected target register info");
711   const auto *TII = SubTarget.getInstrInfo();
712   assert(TII && "Expected target instruction info");
713   if (MI.isCFIInstruction())
714     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
715 
716   SmallBitVector PrintedTypes(8);
717   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
718   unsigned I = 0, E = MI.getNumOperands();
719   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
720          !MI.getOperand(I).isImplicit();
721        ++I) {
722     if (I)
723       OS << ", ";
724     print(MI, I, TRI, ShouldPrintRegisterTies,
725           MI.getTypeToPrint(I, PrintedTypes, MRI),
726           /*PrintDef=*/false);
727   }
728 
729   if (I)
730     OS << " = ";
731   if (MI.getFlag(MachineInstr::FrameSetup))
732     OS << "frame-setup ";
733   if (MI.getFlag(MachineInstr::FrameDestroy))
734     OS << "frame-destroy ";
735   if (MI.getFlag(MachineInstr::FmNoNans))
736     OS << "nnan ";
737   if (MI.getFlag(MachineInstr::FmNoInfs))
738     OS << "ninf ";
739   if (MI.getFlag(MachineInstr::FmNsz))
740     OS << "nsz ";
741   if (MI.getFlag(MachineInstr::FmArcp))
742     OS << "arcp ";
743   if (MI.getFlag(MachineInstr::FmContract))
744     OS << "contract ";
745   if (MI.getFlag(MachineInstr::FmAfn))
746     OS << "afn ";
747   if (MI.getFlag(MachineInstr::FmReassoc))
748     OS << "reassoc ";
749   if (MI.getFlag(MachineInstr::NoUWrap))
750     OS << "nuw ";
751   if (MI.getFlag(MachineInstr::NoSWrap))
752     OS << "nsw ";
753   if (MI.getFlag(MachineInstr::IsExact))
754     OS << "exact ";
755   if (MI.getFlag(MachineInstr::NoFPExcept))
756     OS << "nofpexcept ";
757 
758   OS << TII->getName(MI.getOpcode());
759   if (I < E)
760     OS << ' ';
761 
762   bool NeedComma = false;
763   for (; I < E; ++I) {
764     if (NeedComma)
765       OS << ", ";
766     print(MI, I, TRI, ShouldPrintRegisterTies,
767           MI.getTypeToPrint(I, PrintedTypes, MRI));
768     NeedComma = true;
769   }
770 
771   // Print any optional symbols attached to this instruction as-if they were
772   // operands.
773   if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
774     if (NeedComma)
775       OS << ',';
776     OS << " pre-instr-symbol ";
777     MachineOperand::printSymbol(OS, *PreInstrSymbol);
778     NeedComma = true;
779   }
780   if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
781     if (NeedComma)
782       OS << ',';
783     OS << " post-instr-symbol ";
784     MachineOperand::printSymbol(OS, *PostInstrSymbol);
785     NeedComma = true;
786   }
787   if (MDNode *HeapAllocMarker = MI.getHeapAllocMarker()) {
788     if (NeedComma)
789       OS << ',';
790     OS << " heap-alloc-marker ";
791     HeapAllocMarker->printAsOperand(OS, MST);
792     NeedComma = true;
793   }
794 
795   if (const DebugLoc &DL = MI.getDebugLoc()) {
796     if (NeedComma)
797       OS << ',';
798     OS << " debug-location ";
799     DL->printAsOperand(OS, MST);
800   }
801 
802   if (!MI.memoperands_empty()) {
803     OS << " :: ";
804     const LLVMContext &Context = MF->getFunction().getContext();
805     const MachineFrameInfo &MFI = MF->getFrameInfo();
806     bool NeedComma = false;
807     for (const auto *Op : MI.memoperands()) {
808       if (NeedComma)
809         OS << ", ";
810       Op->print(OS, MST, SSNs, Context, &MFI, TII);
811       NeedComma = true;
812     }
813   }
814 }
815 
816 void MIPrinter::printStackObjectReference(int FrameIndex) {
817   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
818   assert(ObjectInfo != StackObjectOperandMapping.end() &&
819          "Invalid frame index");
820   const FrameIndexOperand &Operand = ObjectInfo->second;
821   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
822                                             Operand.Name);
823 }
824 
825 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
826                       const TargetRegisterInfo *TRI,
827                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
828                       bool PrintDef) {
829   const MachineOperand &Op = MI.getOperand(OpIdx);
830   switch (Op.getType()) {
831   case MachineOperand::MO_Immediate:
832     if (MI.isOperandSubregIdx(OpIdx)) {
833       MachineOperand::printTargetFlags(OS, Op);
834       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
835       break;
836     }
837     LLVM_FALLTHROUGH;
838   case MachineOperand::MO_Register:
839   case MachineOperand::MO_CImmediate:
840   case MachineOperand::MO_FPImmediate:
841   case MachineOperand::MO_MachineBasicBlock:
842   case MachineOperand::MO_ConstantPoolIndex:
843   case MachineOperand::MO_TargetIndex:
844   case MachineOperand::MO_JumpTableIndex:
845   case MachineOperand::MO_ExternalSymbol:
846   case MachineOperand::MO_GlobalAddress:
847   case MachineOperand::MO_RegisterLiveOut:
848   case MachineOperand::MO_Metadata:
849   case MachineOperand::MO_MCSymbol:
850   case MachineOperand::MO_CFIIndex:
851   case MachineOperand::MO_IntrinsicID:
852   case MachineOperand::MO_Predicate:
853   case MachineOperand::MO_BlockAddress:
854   case MachineOperand::MO_ShuffleMask: {
855     unsigned TiedOperandIdx = 0;
856     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
857       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
858     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
859     Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false,
860              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
861     break;
862   }
863   case MachineOperand::MO_FrameIndex:
864     printStackObjectReference(Op.getIndex());
865     break;
866   case MachineOperand::MO_RegisterMask: {
867     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
868     if (RegMaskInfo != RegisterMaskIds.end())
869       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
870     else
871       printCustomRegMask(Op.getRegMask(), OS, TRI);
872     break;
873   }
874   }
875 }
876 
877 void MIRFormatter::printIRValue(raw_ostream &OS, const Value &V,
878                                 ModuleSlotTracker &MST) {
879   if (isa<GlobalValue>(V)) {
880     V.printAsOperand(OS, /*PrintType=*/false, MST);
881     return;
882   }
883   if (isa<Constant>(V)) {
884     // Machine memory operands can load/store to/from constant value pointers.
885     OS << '`';
886     V.printAsOperand(OS, /*PrintType=*/true, MST);
887     OS << '`';
888     return;
889   }
890   OS << "%ir.";
891   if (V.hasName()) {
892     printLLVMNameWithoutPrefix(OS, V.getName());
893     return;
894   }
895   int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
896   MachineOperand::printIRSlotNumber(OS, Slot);
897 }
898 
899 void llvm::printMIR(raw_ostream &OS, const Module &M) {
900   yaml::Output Out(OS);
901   Out << const_cast<Module &>(M);
902 }
903 
904 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
905   MIRPrinter Printer(OS);
906   Printer.print(MF);
907 }
908