1 //===- MachineCycleAnalysis.cpp - Compute CycleInfo for Machine IR --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/CodeGen/MachineCycleAnalysis.h"
10 #include "llvm/ADT/GenericCycleImpl.h"
11 #include "llvm/CodeGen/MachineRegisterInfo.h"
12 #include "llvm/CodeGen/TargetInstrInfo.h"
13 #include "llvm/CodeGen/TargetSubtargetInfo.h"
14 
15 using namespace llvm;
16 
17 template class llvm::GenericCycleInfo<llvm::MachineSSAContext>;
18 template class llvm::GenericCycle<llvm::MachineSSAContext>;
19 
20 char MachineCycleInfoWrapperPass::ID = 0;
21 
22 MachineCycleInfoWrapperPass::MachineCycleInfoWrapperPass()
23     : MachineFunctionPass(ID) {
24   initializeMachineCycleInfoWrapperPassPass(*PassRegistry::getPassRegistry());
25 }
26 
27 INITIALIZE_PASS_BEGIN(MachineCycleInfoWrapperPass, "machine-cycles",
28                       "Machine Cycle Info Analysis", true, true)
29 INITIALIZE_PASS_END(MachineCycleInfoWrapperPass, "machine-cycles",
30                     "Machine Cycle Info Analysis", true, true)
31 
32 void MachineCycleInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
33   AU.setPreservesAll();
34   MachineFunctionPass::getAnalysisUsage(AU);
35 }
36 
37 bool MachineCycleInfoWrapperPass::runOnMachineFunction(MachineFunction &Func) {
38   CI.clear();
39 
40   F = &Func;
41   CI.compute(Func);
42   return false;
43 }
44 
45 void MachineCycleInfoWrapperPass::print(raw_ostream &OS, const Module *) const {
46   OS << "MachineCycleInfo for function: " << F->getName() << "\n";
47   CI.print(OS);
48 }
49 
50 void MachineCycleInfoWrapperPass::releaseMemory() {
51   CI.clear();
52   F = nullptr;
53 }
54 
55 class MachineCycleInfoPrinterPass : public MachineFunctionPass {
56 public:
57   static char ID;
58 
59   MachineCycleInfoPrinterPass();
60 
61   bool runOnMachineFunction(MachineFunction &F) override;
62   void getAnalysisUsage(AnalysisUsage &AU) const override;
63 };
64 
65 char MachineCycleInfoPrinterPass::ID = 0;
66 
67 MachineCycleInfoPrinterPass::MachineCycleInfoPrinterPass()
68     : MachineFunctionPass(ID) {
69   initializeMachineCycleInfoPrinterPassPass(*PassRegistry::getPassRegistry());
70 }
71 
72 INITIALIZE_PASS_BEGIN(MachineCycleInfoPrinterPass, "print-machine-cycles",
73                       "Print Machine Cycle Info Analysis", true, true)
74 INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
75 INITIALIZE_PASS_END(MachineCycleInfoPrinterPass, "print-machine-cycles",
76                     "Print Machine Cycle Info Analysis", true, true)
77 
78 void MachineCycleInfoPrinterPass::getAnalysisUsage(AnalysisUsage &AU) const {
79   AU.setPreservesAll();
80   AU.addRequired<MachineCycleInfoWrapperPass>();
81   MachineFunctionPass::getAnalysisUsage(AU);
82 }
83 
84 bool MachineCycleInfoPrinterPass::runOnMachineFunction(MachineFunction &F) {
85   auto &CI = getAnalysis<MachineCycleInfoWrapperPass>();
86   CI.print(errs());
87   return false;
88 }
89 
90 bool llvm::isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I) {
91   MachineFunction *MF = I.getParent()->getParent();
92   MachineRegisterInfo *MRI = &MF->getRegInfo();
93   const TargetSubtargetInfo &ST = MF->getSubtarget();
94   const TargetRegisterInfo *TRI = ST.getRegisterInfo();
95   const TargetInstrInfo *TII = ST.getInstrInfo();
96 
97   // The instruction is cycle invariant if all of its operands are.
98   for (const MachineOperand &MO : I.operands()) {
99     if (!MO.isReg())
100       continue;
101 
102     Register Reg = MO.getReg();
103     if (Reg == 0)
104       continue;
105 
106     // An instruction that uses or defines a physical register can't e.g. be
107     // hoisted, so mark this as not invariant.
108     if (Register::isPhysicalRegister(Reg)) {
109       if (MO.isUse()) {
110         // If the physreg has no defs anywhere, it's just an ambient register
111         // and we can freely move its uses. Alternatively, if it's allocatable,
112         // it could get allocated to something with a def during allocation.
113         // However, if the physreg is known to always be caller saved/restored
114         // then this use is safe to hoist.
115         if (!MRI->isConstantPhysReg(Reg) &&
116             !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) &&
117             !TII->isIgnorableUse(MO))
118           return false;
119         // Otherwise it's safe to move.
120         continue;
121       } else if (!MO.isDead()) {
122         // A def that isn't dead can't be moved.
123         return false;
124       } else if (any_of(Cycle->getEntries(),
125                         [&](const MachineBasicBlock *Block) {
126                           return Block->isLiveIn(Reg);
127                         })) {
128         // If the reg is live into any header of the cycle we can't hoist an
129         // instruction which would clobber it.
130         return false;
131       }
132     }
133 
134     if (!MO.isUse())
135       continue;
136 
137     assert(MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!");
138 
139     // If the cycle contains the definition of an operand, then the instruction
140     // isn't cycle invariant.
141     if (Cycle->contains(MRI->getVRegDef(Reg)->getParent()))
142       return false;
143   }
144 
145   // If we got this far, the instruction is cycle invariant!
146   return true;
147 }
148