1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Implementation of the MachineRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/CodeGen/MachineRegisterInfo.h" 14 #include "llvm/ADT/iterator_range.h" 15 #include "llvm/CodeGen/MachineBasicBlock.h" 16 #include "llvm/CodeGen/MachineFunction.h" 17 #include "llvm/CodeGen/MachineInstr.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineOperand.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 #include "llvm/CodeGen/TargetRegisterInfo.h" 22 #include "llvm/CodeGen/TargetSubtargetInfo.h" 23 #include "llvm/Config/llvm-config.h" 24 #include "llvm/IR/Attributes.h" 25 #include "llvm/IR/DebugLoc.h" 26 #include "llvm/IR/Function.h" 27 #include "llvm/MC/MCRegisterInfo.h" 28 #include "llvm/Support/Casting.h" 29 #include "llvm/Support/CommandLine.h" 30 #include "llvm/Support/Compiler.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/raw_ostream.h" 33 #include <cassert> 34 35 using namespace llvm; 36 37 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, 38 cl::init(true), cl::desc("Enable subregister liveness tracking.")); 39 40 // Pin the vtable to this file. 41 void MachineRegisterInfo::Delegate::anchor() {} 42 43 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) 44 : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() && 45 EnableSubRegLiveness) { 46 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs(); 47 VRegInfo.reserve(256); 48 RegAllocHints.reserve(256); 49 UsedPhysRegMask.resize(NumRegs); 50 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]()); 51 } 52 53 /// setRegClass - Set the register class of the specified virtual register. 54 /// 55 void 56 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { 57 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); 58 VRegInfo[Reg].first = RC; 59 } 60 61 void MachineRegisterInfo::setRegBank(Register Reg, 62 const RegisterBank &RegBank) { 63 VRegInfo[Reg].first = &RegBank; 64 } 65 66 static const TargetRegisterClass * 67 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, 68 const TargetRegisterClass *OldRC, 69 const TargetRegisterClass *RC, unsigned MinNumRegs) { 70 if (OldRC == RC) 71 return RC; 72 const TargetRegisterClass *NewRC = 73 MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); 74 if (!NewRC || NewRC == OldRC) 75 return NewRC; 76 if (NewRC->getNumRegs() < MinNumRegs) 77 return nullptr; 78 MRI.setRegClass(Reg, NewRC); 79 return NewRC; 80 } 81 82 const TargetRegisterClass * 83 MachineRegisterInfo::constrainRegClass(Register Reg, 84 const TargetRegisterClass *RC, 85 unsigned MinNumRegs) { 86 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); 87 } 88 89 bool 90 MachineRegisterInfo::constrainRegAttrs(Register Reg, 91 Register ConstrainingReg, 92 unsigned MinNumRegs) { 93 const LLT RegTy = getType(Reg); 94 const LLT ConstrainingRegTy = getType(ConstrainingReg); 95 if (RegTy.isValid() && ConstrainingRegTy.isValid() && 96 RegTy != ConstrainingRegTy) 97 return false; 98 const auto ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg); 99 if (!ConstrainingRegCB.isNull()) { 100 const auto RegCB = getRegClassOrRegBank(Reg); 101 if (RegCB.isNull()) 102 setRegClassOrRegBank(Reg, ConstrainingRegCB); 103 else if (RegCB.is<const TargetRegisterClass *>() != 104 ConstrainingRegCB.is<const TargetRegisterClass *>()) 105 return false; 106 else if (RegCB.is<const TargetRegisterClass *>()) { 107 if (!::constrainRegClass( 108 *this, Reg, RegCB.get<const TargetRegisterClass *>(), 109 ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs)) 110 return false; 111 } else if (RegCB != ConstrainingRegCB) 112 return false; 113 } 114 if (ConstrainingRegTy.isValid()) 115 setType(Reg, ConstrainingRegTy); 116 return true; 117 } 118 119 bool 120 MachineRegisterInfo::recomputeRegClass(Register Reg) { 121 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); 122 const TargetRegisterClass *OldRC = getRegClass(Reg); 123 const TargetRegisterClass *NewRC = 124 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF); 125 126 // Stop early if there is no room to grow. 127 if (NewRC == OldRC) 128 return false; 129 130 // Accumulate constraints from all uses. 131 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { 132 // Apply the effect of the given operand to NewRC. 133 MachineInstr *MI = MO.getParent(); 134 unsigned OpNo = &MO - &MI->getOperand(0); 135 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, 136 getTargetRegisterInfo()); 137 if (!NewRC || NewRC == OldRC) 138 return false; 139 } 140 setRegClass(Reg, NewRC); 141 return true; 142 } 143 144 Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) { 145 Register Reg = Register::index2VirtReg(getNumVirtRegs()); 146 VRegInfo.grow(Reg); 147 RegAllocHints.grow(Reg); 148 insertVRegByName(Name, Reg); 149 return Reg; 150 } 151 152 /// createVirtualRegister - Create and return a new virtual register in the 153 /// function with the specified register class. 154 /// 155 Register 156 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, 157 StringRef Name) { 158 assert(RegClass && "Cannot create register without RegClass!"); 159 assert(RegClass->isAllocatable() && 160 "Virtual register RegClass must be allocatable."); 161 162 // New virtual register number. 163 Register Reg = createIncompleteVirtualRegister(Name); 164 VRegInfo[Reg].first = RegClass; 165 if (TheDelegate) 166 TheDelegate->MRI_NoteNewVirtualRegister(Reg); 167 return Reg; 168 } 169 170 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, 171 StringRef Name) { 172 Register Reg = createIncompleteVirtualRegister(Name); 173 VRegInfo[Reg].first = VRegInfo[VReg].first; 174 setType(Reg, getType(VReg)); 175 if (TheDelegate) 176 TheDelegate->MRI_NoteNewVirtualRegister(Reg); 177 return Reg; 178 } 179 180 void MachineRegisterInfo::setType(Register VReg, LLT Ty) { 181 VRegToType.grow(VReg); 182 VRegToType[VReg] = Ty; 183 } 184 185 Register 186 MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) { 187 // New virtual register number. 188 Register Reg = createIncompleteVirtualRegister(Name); 189 // FIXME: Should we use a dummy register class? 190 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr); 191 setType(Reg, Ty); 192 if (TheDelegate) 193 TheDelegate->MRI_NoteNewVirtualRegister(Reg); 194 return Reg; 195 } 196 197 void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); } 198 199 /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 200 void MachineRegisterInfo::clearVirtRegs() { 201 #ifndef NDEBUG 202 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 203 Register Reg = Register::index2VirtReg(i); 204 if (!VRegInfo[Reg].second) 205 continue; 206 verifyUseList(Reg); 207 llvm_unreachable("Remaining virtual register operands"); 208 } 209 #endif 210 VRegInfo.clear(); 211 for (auto &I : LiveIns) 212 I.second = 0; 213 } 214 215 void MachineRegisterInfo::verifyUseList(Register Reg) const { 216 #ifndef NDEBUG 217 bool Valid = true; 218 for (MachineOperand &M : reg_operands(Reg)) { 219 MachineOperand *MO = &M; 220 MachineInstr *MI = MO->getParent(); 221 if (!MI) { 222 errs() << printReg(Reg, getTargetRegisterInfo()) 223 << " use list MachineOperand " << MO 224 << " has no parent instruction.\n"; 225 Valid = false; 226 continue; 227 } 228 MachineOperand *MO0 = &MI->getOperand(0); 229 unsigned NumOps = MI->getNumOperands(); 230 if (!(MO >= MO0 && MO < MO0+NumOps)) { 231 errs() << printReg(Reg, getTargetRegisterInfo()) 232 << " use list MachineOperand " << MO 233 << " doesn't belong to parent MI: " << *MI; 234 Valid = false; 235 } 236 if (!MO->isReg()) { 237 errs() << printReg(Reg, getTargetRegisterInfo()) 238 << " MachineOperand " << MO << ": " << *MO 239 << " is not a register\n"; 240 Valid = false; 241 } 242 if (MO->getReg() != Reg) { 243 errs() << printReg(Reg, getTargetRegisterInfo()) 244 << " use-list MachineOperand " << MO << ": " 245 << *MO << " is the wrong register\n"; 246 Valid = false; 247 } 248 } 249 assert(Valid && "Invalid use list"); 250 #endif 251 } 252 253 void MachineRegisterInfo::verifyUseLists() const { 254 #ifndef NDEBUG 255 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 256 verifyUseList(Register::index2VirtReg(i)); 257 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i) 258 verifyUseList(i); 259 #endif 260 } 261 262 /// Add MO to the linked list of operands for its register. 263 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { 264 assert(!MO->isOnRegUseList() && "Already on list"); 265 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 266 MachineOperand *const Head = HeadRef; 267 268 // Head points to the first list element. 269 // Next is NULL on the last list element. 270 // Prev pointers are circular, so Head->Prev == Last. 271 272 // Head is NULL for an empty list. 273 if (!Head) { 274 MO->Contents.Reg.Prev = MO; 275 MO->Contents.Reg.Next = nullptr; 276 HeadRef = MO; 277 return; 278 } 279 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); 280 281 // Insert MO between Last and Head in the circular Prev chain. 282 MachineOperand *Last = Head->Contents.Reg.Prev; 283 assert(Last && "Inconsistent use list"); 284 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); 285 Head->Contents.Reg.Prev = MO; 286 MO->Contents.Reg.Prev = Last; 287 288 // Def operands always precede uses. This allows def_iterator to stop early. 289 // Insert def operands at the front, and use operands at the back. 290 if (MO->isDef()) { 291 // Insert def at the front. 292 MO->Contents.Reg.Next = Head; 293 HeadRef = MO; 294 } else { 295 // Insert use at the end. 296 MO->Contents.Reg.Next = nullptr; 297 Last->Contents.Reg.Next = MO; 298 } 299 } 300 301 /// Remove MO from its use-def list. 302 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { 303 assert(MO->isOnRegUseList() && "Operand not on use list"); 304 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 305 MachineOperand *const Head = HeadRef; 306 assert(Head && "List already empty"); 307 308 // Unlink this from the doubly linked list of operands. 309 MachineOperand *Next = MO->Contents.Reg.Next; 310 MachineOperand *Prev = MO->Contents.Reg.Prev; 311 312 // Prev links are circular, next link is NULL instead of looping back to Head. 313 if (MO == Head) 314 HeadRef = Next; 315 else 316 Prev->Contents.Reg.Next = Next; 317 318 (Next ? Next : Head)->Contents.Reg.Prev = Prev; 319 320 MO->Contents.Reg.Prev = nullptr; 321 MO->Contents.Reg.Next = nullptr; 322 } 323 324 /// Move NumOps operands from Src to Dst, updating use-def lists as needed. 325 /// 326 /// The Dst range is assumed to be uninitialized memory. (Or it may contain 327 /// operands that won't be destroyed, which is OK because the MO destructor is 328 /// trivial anyway). 329 /// 330 /// The Src and Dst ranges may overlap. 331 void MachineRegisterInfo::moveOperands(MachineOperand *Dst, 332 MachineOperand *Src, 333 unsigned NumOps) { 334 assert(Src != Dst && NumOps && "Noop moveOperands"); 335 336 // Copy backwards if Dst is within the Src range. 337 int Stride = 1; 338 if (Dst >= Src && Dst < Src + NumOps) { 339 Stride = -1; 340 Dst += NumOps - 1; 341 Src += NumOps - 1; 342 } 343 344 // Copy one operand at a time. 345 do { 346 new (Dst) MachineOperand(*Src); 347 348 // Dst takes Src's place in the use-def chain. 349 if (Src->isReg()) { 350 MachineOperand *&Head = getRegUseDefListHead(Src->getReg()); 351 MachineOperand *Prev = Src->Contents.Reg.Prev; 352 MachineOperand *Next = Src->Contents.Reg.Next; 353 assert(Head && "List empty, but operand is chained"); 354 assert(Prev && "Operand was not on use-def list"); 355 356 // Prev links are circular, next link is NULL instead of looping back to 357 // Head. 358 if (Src == Head) 359 Head = Dst; 360 else 361 Prev->Contents.Reg.Next = Dst; 362 363 // Update Prev pointer. This also works when Src was pointing to itself 364 // in a 1-element list. In that case Head == Dst. 365 (Next ? Next : Head)->Contents.Reg.Prev = Dst; 366 } 367 368 Dst += Stride; 369 Src += Stride; 370 } while (--NumOps); 371 } 372 373 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 374 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 375 /// except that it also changes any definitions of the register as well. 376 /// If ToReg is a physical register we apply the sub register to obtain the 377 /// final/proper physical register. 378 void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) { 379 assert(FromReg != ToReg && "Cannot replace a reg with itself"); 380 381 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 382 383 // TODO: This could be more efficient by bulk changing the operands. 384 for (MachineOperand &O : llvm::make_early_inc_range(reg_operands(FromReg))) { 385 if (Register::isPhysicalRegister(ToReg)) { 386 O.substPhysReg(ToReg, *TRI); 387 } else { 388 O.setReg(ToReg); 389 } 390 } 391 } 392 393 /// getVRegDef - Return the machine instr that defines the specified virtual 394 /// register or null if none is found. This assumes that the code is in SSA 395 /// form, so there should only be one definition. 396 MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const { 397 // Since we are in SSA form, we can use the first definition. 398 def_instr_iterator I = def_instr_begin(Reg); 399 assert((I.atEnd() || std::next(I) == def_instr_end()) && 400 "getVRegDef assumes a single definition or no definition"); 401 return !I.atEnd() ? &*I : nullptr; 402 } 403 404 /// getUniqueVRegDef - Return the unique machine instr that defines the 405 /// specified virtual register or null if none is found. If there are 406 /// multiple definitions or no definition, return null. 407 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const { 408 if (def_empty(Reg)) return nullptr; 409 def_instr_iterator I = def_instr_begin(Reg); 410 if (std::next(I) != def_instr_end()) 411 return nullptr; 412 return &*I; 413 } 414 415 bool MachineRegisterInfo::hasOneNonDBGUse(Register RegNo) const { 416 return hasSingleElement(use_nodbg_operands(RegNo)); 417 } 418 419 bool MachineRegisterInfo::hasOneNonDBGUser(Register RegNo) const { 420 return hasSingleElement(use_nodbg_instructions(RegNo)); 421 } 422 423 /// clearKillFlags - Iterate over all the uses of the given register and 424 /// clear the kill flag from the MachineOperand. This function is used by 425 /// optimization passes which extend register lifetimes and need only 426 /// preserve conservative kill flag information. 427 void MachineRegisterInfo::clearKillFlags(Register Reg) const { 428 for (MachineOperand &MO : use_operands(Reg)) 429 MO.setIsKill(false); 430 } 431 432 bool MachineRegisterInfo::isLiveIn(Register Reg) const { 433 for (const std::pair<MCRegister, Register> &LI : liveins()) 434 if ((Register)LI.first == Reg || LI.second == Reg) 435 return true; 436 return false; 437 } 438 439 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 440 /// corresponding live-in physical register. 441 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const { 442 for (const std::pair<MCRegister, Register> &LI : liveins()) 443 if (LI.second == VReg) 444 return LI.first; 445 return MCRegister(); 446 } 447 448 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 449 /// corresponding live-in physical register. 450 Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const { 451 for (const std::pair<MCRegister, Register> &LI : liveins()) 452 if (LI.first == PReg) 453 return LI.second; 454 return Register(); 455 } 456 457 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 458 /// into the given entry block. 459 void 460 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 461 const TargetRegisterInfo &TRI, 462 const TargetInstrInfo &TII) { 463 // Emit the copies into the top of the block. 464 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 465 if (LiveIns[i].second) { 466 if (use_nodbg_empty(LiveIns[i].second)) { 467 // The livein has no non-dbg uses. Drop it. 468 // 469 // It would be preferable to have isel avoid creating live-in 470 // records for unused arguments in the first place, but it's 471 // complicated by the debug info code for arguments. 472 LiveIns.erase(LiveIns.begin() + i); 473 --i; --e; 474 } else { 475 // Emit a copy. 476 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 477 TII.get(TargetOpcode::COPY), LiveIns[i].second) 478 .addReg(LiveIns[i].first); 479 480 // Add the register to the entry block live-in set. 481 EntryMBB->addLiveIn(LiveIns[i].first); 482 } 483 } else { 484 // Add the register to the entry block live-in set. 485 EntryMBB->addLiveIn(LiveIns[i].first); 486 } 487 } 488 489 LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const { 490 // Lane masks are only defined for vregs. 491 assert(Register::isVirtualRegister(Reg)); 492 const TargetRegisterClass &TRC = *getRegClass(Reg); 493 return TRC.getLaneMask(); 494 } 495 496 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 497 LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const { 498 for (MachineInstr &I : use_instructions(Reg)) 499 I.dump(); 500 } 501 #endif 502 503 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 504 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF); 505 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && 506 "Invalid ReservedRegs vector from target"); 507 } 508 509 bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { 510 assert(Register::isPhysicalRegister(PhysReg)); 511 512 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 513 if (TRI->isConstantPhysReg(PhysReg)) 514 return true; 515 516 // Check if any overlapping register is modified, or allocatable so it may be 517 // used later. 518 for (MCRegAliasIterator AI(PhysReg, TRI, true); 519 AI.isValid(); ++AI) 520 if (!def_empty(*AI) || isAllocatable(*AI)) 521 return false; 522 return true; 523 } 524 525 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the 526 /// specified register as undefined which causes the DBG_VALUE to be 527 /// deleted during LiveDebugVariables analysis. 528 void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const { 529 // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.) 530 // We use make_early_inc_range because setReg invalidates the iterator. 531 for (MachineInstr &UseMI : llvm::make_early_inc_range(use_instructions(Reg))) { 532 if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg)) 533 UseMI.setDebugValueUndef(); 534 } 535 } 536 537 static const Function *getCalledFunction(const MachineInstr &MI) { 538 for (const MachineOperand &MO : MI.operands()) { 539 if (!MO.isGlobal()) 540 continue; 541 const Function *Func = dyn_cast<Function>(MO.getGlobal()); 542 if (Func != nullptr) 543 return Func; 544 } 545 return nullptr; 546 } 547 548 static bool isNoReturnDef(const MachineOperand &MO) { 549 // Anything which is not a noreturn function is a real def. 550 const MachineInstr &MI = *MO.getParent(); 551 if (!MI.isCall()) 552 return false; 553 const MachineBasicBlock &MBB = *MI.getParent(); 554 if (!MBB.succ_empty()) 555 return false; 556 const MachineFunction &MF = *MBB.getParent(); 557 // We need to keep correct unwind information even if the function will 558 // not return, since the runtime may need it. 559 if (MF.getFunction().hasFnAttribute(Attribute::UWTable)) 560 return false; 561 const Function *Called = getCalledFunction(MI); 562 return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) || 563 !Called->hasFnAttribute(Attribute::NoUnwind)); 564 } 565 566 bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg, 567 bool SkipNoReturnDef) const { 568 if (UsedPhysRegMask.test(PhysReg)) 569 return true; 570 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 571 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) { 572 for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) { 573 if (!SkipNoReturnDef && isNoReturnDef(MO)) 574 continue; 575 return true; 576 } 577 } 578 return false; 579 } 580 581 bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg, 582 bool SkipRegMaskTest) const { 583 if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg)) 584 return true; 585 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 586 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid(); 587 ++AliasReg) { 588 if (!reg_nodbg_empty(*AliasReg)) 589 return true; 590 } 591 return false; 592 } 593 594 void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) { 595 596 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 597 assert(Reg && (Reg < TRI->getNumRegs()) && 598 "Trying to disable an invalid register"); 599 600 if (!IsUpdatedCSRsInitialized) { 601 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); 602 for (const MCPhysReg *I = CSR; *I; ++I) 603 UpdatedCSRs.push_back(*I); 604 605 // Zero value represents the end of the register list 606 // (no more registers should be pushed). 607 UpdatedCSRs.push_back(0); 608 609 IsUpdatedCSRsInitialized = true; 610 } 611 612 // Remove the register (and its aliases from the list). 613 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 614 llvm::erase_value(UpdatedCSRs, *AI); 615 } 616 617 const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const { 618 if (IsUpdatedCSRsInitialized) 619 return UpdatedCSRs.data(); 620 621 return getTargetRegisterInfo()->getCalleeSavedRegs(MF); 622 } 623 624 void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) { 625 if (IsUpdatedCSRsInitialized) 626 UpdatedCSRs.clear(); 627 628 append_range(UpdatedCSRs, CSRs); 629 630 // Zero value represents the end of the register list 631 // (no more registers should be pushed). 632 UpdatedCSRs.push_back(0); 633 IsUpdatedCSRsInitialized = true; 634 } 635 636 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const { 637 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 638 for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) { 639 bool IsRootReserved = true; 640 for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true); 641 Super.isValid(); ++Super) { 642 MCRegister Reg = *Super; 643 if (!isReserved(Reg)) { 644 IsRootReserved = false; 645 break; 646 } 647 } 648 if (IsRootReserved) 649 return true; 650 } 651 return false; 652 } 653 654 bool MachineRegisterInfo::isArgumentRegister(const MachineFunction &MF, 655 MCRegister Reg) const { 656 return getTargetRegisterInfo()->isArgumentRegister(MF, Reg); 657 } 658 659 bool MachineRegisterInfo::isFixedRegister(const MachineFunction &MF, 660 MCRegister Reg) const { 661 return getTargetRegisterInfo()->isFixedRegister(MF, Reg); 662 } 663 664 bool MachineRegisterInfo::isGeneralPurposeRegister(const MachineFunction &MF, 665 MCRegister Reg) const { 666 return getTargetRegisterInfo()->isGeneralPurposeRegister(MF, Reg); 667 } 668