1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Implementation of the MachineRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/CodeGen/MachineRegisterInfo.h" 14 #include "llvm/ADT/iterator_range.h" 15 #include "llvm/CodeGen/LowLevelType.h" 16 #include "llvm/CodeGen/MachineBasicBlock.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineInstr.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineOperand.h" 21 #include "llvm/CodeGen/TargetInstrInfo.h" 22 #include "llvm/CodeGen/TargetRegisterInfo.h" 23 #include "llvm/CodeGen/TargetSubtargetInfo.h" 24 #include "llvm/Config/llvm-config.h" 25 #include "llvm/IR/Attributes.h" 26 #include "llvm/IR/DebugLoc.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/MC/MCRegisterInfo.h" 29 #include "llvm/Support/Casting.h" 30 #include "llvm/Support/CommandLine.h" 31 #include "llvm/Support/Compiler.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/raw_ostream.h" 34 #include <cassert> 35 36 using namespace llvm; 37 38 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, 39 cl::init(true), cl::desc("Enable subregister liveness tracking.")); 40 41 // Pin the vtable to this file. 42 void MachineRegisterInfo::Delegate::anchor() {} 43 44 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) 45 : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() && 46 EnableSubRegLiveness), 47 IsUpdatedCSRsInitialized(false) { 48 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs(); 49 VRegInfo.reserve(256); 50 RegAllocHints.reserve(256); 51 UsedPhysRegMask.resize(NumRegs); 52 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]()); 53 } 54 55 /// setRegClass - Set the register class of the specified virtual register. 56 /// 57 void 58 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 59 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); 60 VRegInfo[Reg].first = RC; 61 } 62 63 void MachineRegisterInfo::setRegBank(unsigned Reg, 64 const RegisterBank &RegBank) { 65 VRegInfo[Reg].first = &RegBank; 66 } 67 68 static const TargetRegisterClass * 69 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, 70 const TargetRegisterClass *OldRC, 71 const TargetRegisterClass *RC, unsigned MinNumRegs) { 72 if (OldRC == RC) 73 return RC; 74 const TargetRegisterClass *NewRC = 75 MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); 76 if (!NewRC || NewRC == OldRC) 77 return NewRC; 78 if (NewRC->getNumRegs() < MinNumRegs) 79 return nullptr; 80 MRI.setRegClass(Reg, NewRC); 81 return NewRC; 82 } 83 84 const TargetRegisterClass * 85 MachineRegisterInfo::constrainRegClass(unsigned Reg, 86 const TargetRegisterClass *RC, 87 unsigned MinNumRegs) { 88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); 89 } 90 91 bool 92 MachineRegisterInfo::constrainRegAttrs(unsigned Reg, 93 unsigned ConstrainingReg, 94 unsigned MinNumRegs) { 95 const LLT RegTy = getType(Reg); 96 const LLT ConstrainingRegTy = getType(ConstrainingReg); 97 if (RegTy.isValid() && ConstrainingRegTy.isValid() && 98 RegTy != ConstrainingRegTy) 99 return false; 100 const auto ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg); 101 if (!ConstrainingRegCB.isNull()) { 102 const auto RegCB = getRegClassOrRegBank(Reg); 103 if (RegCB.isNull()) 104 setRegClassOrRegBank(Reg, ConstrainingRegCB); 105 else if (RegCB.is<const TargetRegisterClass *>() != 106 ConstrainingRegCB.is<const TargetRegisterClass *>()) 107 return false; 108 else if (RegCB.is<const TargetRegisterClass *>()) { 109 if (!::constrainRegClass( 110 *this, Reg, RegCB.get<const TargetRegisterClass *>(), 111 ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs)) 112 return false; 113 } else if (RegCB != ConstrainingRegCB) 114 return false; 115 } 116 if (ConstrainingRegTy.isValid()) 117 setType(Reg, ConstrainingRegTy); 118 return true; 119 } 120 121 bool 122 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { 123 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); 124 const TargetRegisterClass *OldRC = getRegClass(Reg); 125 const TargetRegisterClass *NewRC = 126 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF); 127 128 // Stop early if there is no room to grow. 129 if (NewRC == OldRC) 130 return false; 131 132 // Accumulate constraints from all uses. 133 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { 134 // Apply the effect of the given operand to NewRC. 135 MachineInstr *MI = MO.getParent(); 136 unsigned OpNo = &MO - &MI->getOperand(0); 137 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, 138 getTargetRegisterInfo()); 139 if (!NewRC || NewRC == OldRC) 140 return false; 141 } 142 setRegClass(Reg, NewRC); 143 return true; 144 } 145 146 unsigned MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) { 147 unsigned Reg = Register::index2VirtReg(getNumVirtRegs()); 148 VRegInfo.grow(Reg); 149 RegAllocHints.grow(Reg); 150 insertVRegByName(Name, Reg); 151 return Reg; 152 } 153 154 /// createVirtualRegister - Create and return a new virtual register in the 155 /// function with the specified register class. 156 /// 157 Register 158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, 159 StringRef Name) { 160 assert(RegClass && "Cannot create register without RegClass!"); 161 assert(RegClass->isAllocatable() && 162 "Virtual register RegClass must be allocatable."); 163 164 // New virtual register number. 165 unsigned Reg = createIncompleteVirtualRegister(Name); 166 VRegInfo[Reg].first = RegClass; 167 if (TheDelegate) 168 TheDelegate->MRI_NoteNewVirtualRegister(Reg); 169 return Reg; 170 } 171 172 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, 173 StringRef Name) { 174 unsigned Reg = createIncompleteVirtualRegister(Name); 175 VRegInfo[Reg].first = VRegInfo[VReg].first; 176 setType(Reg, getType(VReg)); 177 if (TheDelegate) 178 TheDelegate->MRI_NoteNewVirtualRegister(Reg); 179 return Reg; 180 } 181 182 void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) { 183 VRegToType.grow(VReg); 184 VRegToType[VReg] = Ty; 185 } 186 187 Register 188 MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) { 189 // New virtual register number. 190 unsigned Reg = createIncompleteVirtualRegister(Name); 191 // FIXME: Should we use a dummy register class? 192 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr); 193 setType(Reg, Ty); 194 if (TheDelegate) 195 TheDelegate->MRI_NoteNewVirtualRegister(Reg); 196 return Reg; 197 } 198 199 void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); } 200 201 /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 202 void MachineRegisterInfo::clearVirtRegs() { 203 #ifndef NDEBUG 204 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 205 unsigned Reg = Register::index2VirtReg(i); 206 if (!VRegInfo[Reg].second) 207 continue; 208 verifyUseList(Reg); 209 llvm_unreachable("Remaining virtual register operands"); 210 } 211 #endif 212 VRegInfo.clear(); 213 for (auto &I : LiveIns) 214 I.second = 0; 215 } 216 217 void MachineRegisterInfo::verifyUseList(unsigned Reg) const { 218 #ifndef NDEBUG 219 bool Valid = true; 220 for (MachineOperand &M : reg_operands(Reg)) { 221 MachineOperand *MO = &M; 222 MachineInstr *MI = MO->getParent(); 223 if (!MI) { 224 errs() << printReg(Reg, getTargetRegisterInfo()) 225 << " use list MachineOperand " << MO 226 << " has no parent instruction.\n"; 227 Valid = false; 228 continue; 229 } 230 MachineOperand *MO0 = &MI->getOperand(0); 231 unsigned NumOps = MI->getNumOperands(); 232 if (!(MO >= MO0 && MO < MO0+NumOps)) { 233 errs() << printReg(Reg, getTargetRegisterInfo()) 234 << " use list MachineOperand " << MO 235 << " doesn't belong to parent MI: " << *MI; 236 Valid = false; 237 } 238 if (!MO->isReg()) { 239 errs() << printReg(Reg, getTargetRegisterInfo()) 240 << " MachineOperand " << MO << ": " << *MO 241 << " is not a register\n"; 242 Valid = false; 243 } 244 if (MO->getReg() != Reg) { 245 errs() << printReg(Reg, getTargetRegisterInfo()) 246 << " use-list MachineOperand " << MO << ": " 247 << *MO << " is the wrong register\n"; 248 Valid = false; 249 } 250 } 251 assert(Valid && "Invalid use list"); 252 #endif 253 } 254 255 void MachineRegisterInfo::verifyUseLists() const { 256 #ifndef NDEBUG 257 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 258 verifyUseList(Register::index2VirtReg(i)); 259 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i) 260 verifyUseList(i); 261 #endif 262 } 263 264 /// Add MO to the linked list of operands for its register. 265 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { 266 assert(!MO->isOnRegUseList() && "Already on list"); 267 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 268 MachineOperand *const Head = HeadRef; 269 270 // Head points to the first list element. 271 // Next is NULL on the last list element. 272 // Prev pointers are circular, so Head->Prev == Last. 273 274 // Head is NULL for an empty list. 275 if (!Head) { 276 MO->Contents.Reg.Prev = MO; 277 MO->Contents.Reg.Next = nullptr; 278 HeadRef = MO; 279 return; 280 } 281 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); 282 283 // Insert MO between Last and Head in the circular Prev chain. 284 MachineOperand *Last = Head->Contents.Reg.Prev; 285 assert(Last && "Inconsistent use list"); 286 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); 287 Head->Contents.Reg.Prev = MO; 288 MO->Contents.Reg.Prev = Last; 289 290 // Def operands always precede uses. This allows def_iterator to stop early. 291 // Insert def operands at the front, and use operands at the back. 292 if (MO->isDef()) { 293 // Insert def at the front. 294 MO->Contents.Reg.Next = Head; 295 HeadRef = MO; 296 } else { 297 // Insert use at the end. 298 MO->Contents.Reg.Next = nullptr; 299 Last->Contents.Reg.Next = MO; 300 } 301 } 302 303 /// Remove MO from its use-def list. 304 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { 305 assert(MO->isOnRegUseList() && "Operand not on use list"); 306 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 307 MachineOperand *const Head = HeadRef; 308 assert(Head && "List already empty"); 309 310 // Unlink this from the doubly linked list of operands. 311 MachineOperand *Next = MO->Contents.Reg.Next; 312 MachineOperand *Prev = MO->Contents.Reg.Prev; 313 314 // Prev links are circular, next link is NULL instead of looping back to Head. 315 if (MO == Head) 316 HeadRef = Next; 317 else 318 Prev->Contents.Reg.Next = Next; 319 320 (Next ? Next : Head)->Contents.Reg.Prev = Prev; 321 322 MO->Contents.Reg.Prev = nullptr; 323 MO->Contents.Reg.Next = nullptr; 324 } 325 326 /// Move NumOps operands from Src to Dst, updating use-def lists as needed. 327 /// 328 /// The Dst range is assumed to be uninitialized memory. (Or it may contain 329 /// operands that won't be destroyed, which is OK because the MO destructor is 330 /// trivial anyway). 331 /// 332 /// The Src and Dst ranges may overlap. 333 void MachineRegisterInfo::moveOperands(MachineOperand *Dst, 334 MachineOperand *Src, 335 unsigned NumOps) { 336 assert(Src != Dst && NumOps && "Noop moveOperands"); 337 338 // Copy backwards if Dst is within the Src range. 339 int Stride = 1; 340 if (Dst >= Src && Dst < Src + NumOps) { 341 Stride = -1; 342 Dst += NumOps - 1; 343 Src += NumOps - 1; 344 } 345 346 // Copy one operand at a time. 347 do { 348 new (Dst) MachineOperand(*Src); 349 350 // Dst takes Src's place in the use-def chain. 351 if (Src->isReg()) { 352 MachineOperand *&Head = getRegUseDefListHead(Src->getReg()); 353 MachineOperand *Prev = Src->Contents.Reg.Prev; 354 MachineOperand *Next = Src->Contents.Reg.Next; 355 assert(Head && "List empty, but operand is chained"); 356 assert(Prev && "Operand was not on use-def list"); 357 358 // Prev links are circular, next link is NULL instead of looping back to 359 // Head. 360 if (Src == Head) 361 Head = Dst; 362 else 363 Prev->Contents.Reg.Next = Dst; 364 365 // Update Prev pointer. This also works when Src was pointing to itself 366 // in a 1-element list. In that case Head == Dst. 367 (Next ? Next : Head)->Contents.Reg.Prev = Dst; 368 } 369 370 Dst += Stride; 371 Src += Stride; 372 } while (--NumOps); 373 } 374 375 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 376 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 377 /// except that it also changes any definitions of the register as well. 378 /// If ToReg is a physical register we apply the sub register to obtain the 379 /// final/proper physical register. 380 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 381 assert(FromReg != ToReg && "Cannot replace a reg with itself"); 382 383 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 384 385 // TODO: This could be more efficient by bulk changing the operands. 386 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 387 MachineOperand &O = *I; 388 ++I; 389 if (Register::isPhysicalRegister(ToReg)) { 390 O.substPhysReg(ToReg, *TRI); 391 } else { 392 O.setReg(ToReg); 393 } 394 } 395 } 396 397 /// getVRegDef - Return the machine instr that defines the specified virtual 398 /// register or null if none is found. This assumes that the code is in SSA 399 /// form, so there should only be one definition. 400 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 401 // Since we are in SSA form, we can use the first definition. 402 def_instr_iterator I = def_instr_begin(Reg); 403 assert((I.atEnd() || std::next(I) == def_instr_end()) && 404 "getVRegDef assumes a single definition or no definition"); 405 return !I.atEnd() ? &*I : nullptr; 406 } 407 408 /// getUniqueVRegDef - Return the unique machine instr that defines the 409 /// specified virtual register or null if none is found. If there are 410 /// multiple definitions or no definition, return null. 411 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { 412 if (def_empty(Reg)) return nullptr; 413 def_instr_iterator I = def_instr_begin(Reg); 414 if (std::next(I) != def_instr_end()) 415 return nullptr; 416 return &*I; 417 } 418 419 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 420 use_nodbg_iterator UI = use_nodbg_begin(RegNo); 421 if (UI == use_nodbg_end()) 422 return false; 423 return ++UI == use_nodbg_end(); 424 } 425 426 bool MachineRegisterInfo::hasOneNonDBGUser(unsigned RegNo) const { 427 use_instr_nodbg_iterator UI = use_instr_nodbg_begin(RegNo); 428 if (UI == use_instr_nodbg_end()) 429 return false; 430 return ++UI == use_instr_nodbg_end(); 431 } 432 433 /// clearKillFlags - Iterate over all the uses of the given register and 434 /// clear the kill flag from the MachineOperand. This function is used by 435 /// optimization passes which extend register lifetimes and need only 436 /// preserve conservative kill flag information. 437 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 438 for (MachineOperand &MO : use_operands(Reg)) 439 MO.setIsKill(false); 440 } 441 442 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 443 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 444 if (I->first == Reg || I->second == Reg) 445 return true; 446 return false; 447 } 448 449 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 450 /// corresponding live-in physical register. 451 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 452 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 453 if (I->second == VReg) 454 return I->first; 455 return 0; 456 } 457 458 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 459 /// corresponding live-in physical register. 460 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 461 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 462 if (I->first == PReg) 463 return I->second; 464 return 0; 465 } 466 467 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 468 /// into the given entry block. 469 void 470 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 471 const TargetRegisterInfo &TRI, 472 const TargetInstrInfo &TII) { 473 // Emit the copies into the top of the block. 474 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 475 if (LiveIns[i].second) { 476 if (use_nodbg_empty(LiveIns[i].second)) { 477 // The livein has no non-dbg uses. Drop it. 478 // 479 // It would be preferable to have isel avoid creating live-in 480 // records for unused arguments in the first place, but it's 481 // complicated by the debug info code for arguments. 482 LiveIns.erase(LiveIns.begin() + i); 483 --i; --e; 484 } else { 485 // Emit a copy. 486 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 487 TII.get(TargetOpcode::COPY), LiveIns[i].second) 488 .addReg(LiveIns[i].first); 489 490 // Add the register to the entry block live-in set. 491 EntryMBB->addLiveIn(LiveIns[i].first); 492 } 493 } else { 494 // Add the register to the entry block live-in set. 495 EntryMBB->addLiveIn(LiveIns[i].first); 496 } 497 } 498 499 LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const { 500 // Lane masks are only defined for vregs. 501 assert(Register::isVirtualRegister(Reg)); 502 const TargetRegisterClass &TRC = *getRegClass(Reg); 503 return TRC.getLaneMask(); 504 } 505 506 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 507 LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(unsigned Reg) const { 508 for (MachineInstr &I : use_instructions(Reg)) 509 I.dump(); 510 } 511 #endif 512 513 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 514 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF); 515 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && 516 "Invalid ReservedRegs vector from target"); 517 } 518 519 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const { 520 assert(Register::isPhysicalRegister(PhysReg)); 521 522 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 523 if (TRI->isConstantPhysReg(PhysReg)) 524 return true; 525 526 // Check if any overlapping register is modified, or allocatable so it may be 527 // used later. 528 for (MCRegAliasIterator AI(PhysReg, TRI, true); 529 AI.isValid(); ++AI) 530 if (!def_empty(*AI) || isAllocatable(*AI)) 531 return false; 532 return true; 533 } 534 535 bool 536 MachineRegisterInfo::isCallerPreservedOrConstPhysReg(unsigned PhysReg) const { 537 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 538 return isConstantPhysReg(PhysReg) || 539 TRI->isCallerPreservedPhysReg(PhysReg, *MF); 540 } 541 542 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the 543 /// specified register as undefined which causes the DBG_VALUE to be 544 /// deleted during LiveDebugVariables analysis. 545 void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const { 546 // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.) 547 MachineRegisterInfo::use_instr_iterator nextI; 548 for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end(); 549 I != E; I = nextI) { 550 nextI = std::next(I); // I is invalidated by the setReg 551 MachineInstr *UseMI = &*I; 552 if (UseMI->isDebugValue()) 553 UseMI->getOperand(0).setReg(0U); 554 } 555 } 556 557 static const Function *getCalledFunction(const MachineInstr &MI) { 558 for (const MachineOperand &MO : MI.operands()) { 559 if (!MO.isGlobal()) 560 continue; 561 const Function *Func = dyn_cast<Function>(MO.getGlobal()); 562 if (Func != nullptr) 563 return Func; 564 } 565 return nullptr; 566 } 567 568 static bool isNoReturnDef(const MachineOperand &MO) { 569 // Anything which is not a noreturn function is a real def. 570 const MachineInstr &MI = *MO.getParent(); 571 if (!MI.isCall()) 572 return false; 573 const MachineBasicBlock &MBB = *MI.getParent(); 574 if (!MBB.succ_empty()) 575 return false; 576 const MachineFunction &MF = *MBB.getParent(); 577 // We need to keep correct unwind information even if the function will 578 // not return, since the runtime may need it. 579 if (MF.getFunction().hasFnAttribute(Attribute::UWTable)) 580 return false; 581 const Function *Called = getCalledFunction(MI); 582 return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) || 583 !Called->hasFnAttribute(Attribute::NoUnwind)); 584 } 585 586 bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg, 587 bool SkipNoReturnDef) const { 588 if (UsedPhysRegMask.test(PhysReg)) 589 return true; 590 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 591 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) { 592 for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) { 593 if (!SkipNoReturnDef && isNoReturnDef(MO)) 594 continue; 595 return true; 596 } 597 } 598 return false; 599 } 600 601 bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const { 602 if (UsedPhysRegMask.test(PhysReg)) 603 return true; 604 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 605 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid(); 606 ++AliasReg) { 607 if (!reg_nodbg_empty(*AliasReg)) 608 return true; 609 } 610 return false; 611 } 612 613 void MachineRegisterInfo::disableCalleeSavedRegister(unsigned Reg) { 614 615 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 616 assert(Reg && (Reg < TRI->getNumRegs()) && 617 "Trying to disable an invalid register"); 618 619 if (!IsUpdatedCSRsInitialized) { 620 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); 621 for (const MCPhysReg *I = CSR; *I; ++I) 622 UpdatedCSRs.push_back(*I); 623 624 // Zero value represents the end of the register list 625 // (no more registers should be pushed). 626 UpdatedCSRs.push_back(0); 627 628 IsUpdatedCSRsInitialized = true; 629 } 630 631 // Remove the register (and its aliases from the list). 632 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 633 UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI), 634 UpdatedCSRs.end()); 635 } 636 637 const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const { 638 if (IsUpdatedCSRsInitialized) 639 return UpdatedCSRs.data(); 640 641 return getTargetRegisterInfo()->getCalleeSavedRegs(MF); 642 } 643 644 void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) { 645 if (IsUpdatedCSRsInitialized) 646 UpdatedCSRs.clear(); 647 648 for (MCPhysReg Reg : CSRs) 649 UpdatedCSRs.push_back(Reg); 650 651 // Zero value represents the end of the register list 652 // (no more registers should be pushed). 653 UpdatedCSRs.push_back(0); 654 IsUpdatedCSRsInitialized = true; 655 } 656 657 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const { 658 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 659 for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) { 660 bool IsRootReserved = true; 661 for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true); 662 Super.isValid(); ++Super) { 663 unsigned Reg = *Super; 664 if (!isReserved(Reg)) { 665 IsRootReserved = false; 666 break; 667 } 668 } 669 if (IsRootReserved) 670 return true; 671 } 672 return false; 673 } 674