1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RegisterClassInfo class which provides dynamic
10 // information about target register classes. Callee-saved vs. caller-saved and
11 // reserved registers depend on calling conventions and other dynamic
12 // information, so some things cannot be determined statically.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/RegisterClassInfo.h"
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include <algorithm>
29 #include <cassert>
30 #include <cstdint>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "regalloc"
35 
36 static cl::opt<unsigned>
37 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
38          cl::desc("Limit all regclasses to N registers"));
39 
40 RegisterClassInfo::RegisterClassInfo() = default;
41 
42 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
43   bool Update = false;
44   MF = &mf;
45 
46   auto &STI = MF->getSubtarget();
47 
48   // Allocate new array the first time we see a new target.
49   if (STI.getRegisterInfo() != TRI) {
50     TRI = STI.getRegisterInfo();
51     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
52     Update = true;
53   }
54 
55   // Does this MF have different CSRs?
56   assert(TRI && "no register info set");
57 
58   // Get the callee saved registers.
59   const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
60   if (Update || CSR != CalleeSavedRegs) {
61     // Build a CSRAlias map. Every CSR alias saves the last
62     // overlapping CSR.
63     CalleeSavedAliases.assign(TRI->getNumRegs(), 0);
64     for (const MCPhysReg *I = CSR; *I; ++I)
65       for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
66         CalleeSavedAliases[*AI] = *I;
67 
68     Update = true;
69   }
70   CalleeSavedRegs = CSR;
71 
72   // Even if CSR list is same, we could have had a different allocation order
73   // if ignoreCSRForAllocationOrder is evaluated differently.
74   BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
75   for (const MCPhysReg *I = CSR; *I; ++I)
76     for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
77       CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
78   if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
79       IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
80     Update = true;
81     IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;
82   }
83 
84   RegCosts = TRI->getRegisterCosts(*MF);
85 
86   // Different reserved registers?
87   const BitVector &RR = MF->getRegInfo().getReservedRegs();
88   if (Reserved.size() != RR.size() || RR != Reserved) {
89     Update = true;
90     Reserved = RR;
91   }
92 
93   // Invalidate cached information from previous function.
94   if (Update) {
95     unsigned NumPSets = TRI->getNumRegPressureSets();
96     PSetLimits.reset(new unsigned[NumPSets]);
97     std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
98     ++Tag;
99   }
100 }
101 
102 /// compute - Compute the preferred allocation order for RC with reserved
103 /// registers filtered out. Volatile registers come first followed by CSR
104 /// aliases ordered according to the CSR order specified by the target.
105 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
106   assert(RC && "no register class given");
107   RCInfo &RCI = RegClass[RC->getID()];
108   auto &STI = MF->getSubtarget();
109 
110   // Raw register count, including all reserved regs.
111   unsigned NumRegs = RC->getNumRegs();
112 
113   if (!RCI.Order)
114     RCI.Order.reset(new MCPhysReg[NumRegs]);
115 
116   unsigned N = 0;
117   SmallVector<MCPhysReg, 16> CSRAlias;
118   uint8_t MinCost = uint8_t(~0u);
119   uint8_t LastCost = uint8_t(~0u);
120   unsigned LastCostChange = 0;
121 
122   // FIXME: Once targets reserve registers instead of removing them from the
123   // allocation order, we can simply use begin/end here.
124   ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
125   for (unsigned PhysReg : RawOrder) {
126     // Remove reserved registers from the allocation order.
127     if (Reserved.test(PhysReg))
128       continue;
129     uint8_t Cost = RegCosts[PhysReg];
130     MinCost = std::min(MinCost, Cost);
131 
132     if (CalleeSavedAliases[PhysReg] &&
133         !STI.ignoreCSRForAllocationOrder(*MF, PhysReg))
134       // PhysReg aliases a CSR, save it for later.
135       CSRAlias.push_back(PhysReg);
136     else {
137       if (Cost != LastCost)
138         LastCostChange = N;
139       RCI.Order[N++] = PhysReg;
140       LastCost = Cost;
141     }
142   }
143   RCI.NumRegs = N + CSRAlias.size();
144   assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
145 
146   // CSR aliases go after the volatile registers, preserve the target's order.
147   for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
148     unsigned PhysReg = CSRAlias[i];
149     uint8_t Cost = RegCosts[PhysReg];
150     if (Cost != LastCost)
151       LastCostChange = N;
152     RCI.Order[N++] = PhysReg;
153     LastCost = Cost;
154   }
155 
156   // Register allocator stress test.  Clip register class to N registers.
157   if (StressRA && RCI.NumRegs > StressRA)
158     RCI.NumRegs = StressRA;
159 
160   // Check if RC is a proper sub-class.
161   if (const TargetRegisterClass *Super =
162           TRI->getLargestLegalSuperClass(RC, *MF))
163     if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
164       RCI.ProperSubClass = true;
165 
166   RCI.MinCost = MinCost;
167   RCI.LastCostChange = LastCostChange;
168 
169   LLVM_DEBUG({
170     dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
171     for (unsigned I = 0; I != RCI.NumRegs; ++I)
172       dbgs() << ' ' << printReg(RCI.Order[I], TRI);
173     dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
174   });
175 
176   // RCI is now up-to-date.
177   RCI.Tag = Tag;
178 }
179 
180 /// This is not accurate because two overlapping register sets may have some
181 /// nonoverlapping reserved registers. However, computing the allocation order
182 /// for all register classes would be too expensive.
183 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
184   const TargetRegisterClass *RC = nullptr;
185   unsigned NumRCUnits = 0;
186   for (const TargetRegisterClass *C : TRI->regclasses()) {
187     const int *PSetID = TRI->getRegClassPressureSets(C);
188     for (; *PSetID != -1; ++PSetID) {
189       if ((unsigned)*PSetID == Idx)
190         break;
191     }
192     if (*PSetID == -1)
193       continue;
194 
195     // Found a register class that counts against this pressure set.
196     // For efficiency, only compute the set order for the largest set.
197     unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
198     if (!RC || NUnits > NumRCUnits) {
199       RC = C;
200       NumRCUnits = NUnits;
201     }
202   }
203   assert(RC && "Failed to find register class");
204   compute(RC);
205   unsigned NAllocatableRegs = getNumAllocatableRegs(RC);
206   unsigned RegPressureSetLimit = TRI->getRegPressureSetLimit(*MF, Idx);
207   // If all the regs are reserved, return raw RegPressureSetLimit.
208   // One example is VRSAVERC in PowerPC.
209   // Avoid returning zero, getRegPressureSetLimit(Idx) assumes computePSetLimit
210   // return non-zero value.
211   if (NAllocatableRegs == 0)
212     return RegPressureSetLimit;
213   unsigned NReserved = RC->getNumRegs() - NAllocatableRegs;
214   return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight * NReserved;
215 }
216