1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements routines for translating functions from LLVM IR into
10 // Machine IR.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/FunctionLoweringInfo.h"
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/Analysis/UniformityAnalysis.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetFrameLowering.h"
23 #include "llvm/CodeGen/TargetInstrInfo.h"
24 #include "llvm/CodeGen/TargetLowering.h"
25 #include "llvm/CodeGen/TargetRegisterInfo.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/CodeGen/WasmEHFuncInfo.h"
28 #include "llvm/CodeGen/WinEHFuncInfo.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Instructions.h"
33 #include "llvm/IR/IntrinsicInst.h"
34 #include "llvm/IR/Module.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include <algorithm>
39 using namespace llvm;
40 
41 #define DEBUG_TYPE "function-lowering-info"
42 
43 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
44 /// PHI nodes or outside of the basic block that defines it, or used by a
45 /// switch or atomic instruction, which may expand to multiple basic blocks.
46 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
47   if (I->use_empty()) return false;
48   if (isa<PHINode>(I)) return true;
49   const BasicBlock *BB = I->getParent();
50   for (const User *U : I->users())
51     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
52       return true;
53 
54   return false;
55 }
56 
57 static ISD::NodeType getPreferredExtendForValue(const Instruction *I) {
58   // For the users of the source value being used for compare instruction, if
59   // the number of signed predicate is greater than unsigned predicate, we
60   // prefer to use SIGN_EXTEND.
61   //
62   // With this optimization, we would be able to reduce some redundant sign or
63   // zero extension instruction, and eventually more machine CSE opportunities
64   // can be exposed.
65   ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
66   unsigned NumOfSigned = 0, NumOfUnsigned = 0;
67   for (const User *U : I->users()) {
68     if (const auto *CI = dyn_cast<CmpInst>(U)) {
69       NumOfSigned += CI->isSigned();
70       NumOfUnsigned += CI->isUnsigned();
71     }
72   }
73   if (NumOfSigned > NumOfUnsigned)
74     ExtendKind = ISD::SIGN_EXTEND;
75 
76   return ExtendKind;
77 }
78 
79 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
80                                SelectionDAG *DAG) {
81   Fn = &fn;
82   MF = &mf;
83   TLI = MF->getSubtarget().getTargetLowering();
84   RegInfo = &MF->getRegInfo();
85   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
86   UA = DAG->getUniformityInfo();
87 
88   // Check whether the function can return without sret-demotion.
89   SmallVector<ISD::OutputArg, 4> Outs;
90   CallingConv::ID CC = Fn->getCallingConv();
91 
92   GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
93                 mf.getDataLayout());
94   CanLowerReturn =
95       TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext());
96 
97   // If this personality uses funclets, we need to do a bit more work.
98   DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
99   EHPersonality Personality = classifyEHPersonality(
100       Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
101   if (isFuncletEHPersonality(Personality)) {
102     // Calculate state numbers if we haven't already.
103     WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
104     if (Personality == EHPersonality::MSVC_CXX)
105       calculateWinCXXEHStateNumbers(&fn, EHInfo);
106     else if (isAsynchronousEHPersonality(Personality))
107       calculateSEHStateNumbers(&fn, EHInfo);
108     else if (Personality == EHPersonality::CoreCLR)
109       calculateClrEHStateNumbers(&fn, EHInfo);
110 
111     // Map all BB references in the WinEH data to MBBs.
112     for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
113       for (WinEHHandlerType &H : TBME.HandlerArray) {
114         if (const AllocaInst *AI = H.CatchObj.Alloca)
115           CatchObjects.insert({AI, {}}).first->second.push_back(
116               &H.CatchObj.FrameIndex);
117         else
118           H.CatchObj.FrameIndex = INT_MAX;
119       }
120     }
121   }
122 
123   // Initialize the mapping of values to registers.  This is only set up for
124   // instruction values that are used outside of the block that defines
125   // them.
126   const Align StackAlign = TFI->getStackAlign();
127   for (const BasicBlock &BB : *Fn) {
128     for (const Instruction &I : BB) {
129       if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) {
130         Type *Ty = AI->getAllocatedType();
131         Align Alignment = AI->getAlign();
132 
133         // Static allocas can be folded into the initial stack frame
134         // adjustment. For targets that don't realign the stack, don't
135         // do this if there is an extra alignment requirement.
136         if (AI->isStaticAlloca() &&
137             (TFI->isStackRealignable() || (Alignment <= StackAlign))) {
138           const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
139           uint64_t TySize =
140               MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinValue();
141 
142           TySize *= CUI->getZExtValue();   // Get total allocated size.
143           if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
144           int FrameIndex = INT_MAX;
145           auto Iter = CatchObjects.find(AI);
146           if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
147             FrameIndex = MF->getFrameInfo().CreateFixedObject(
148                 TySize, 0, /*IsImmutable=*/false, /*isAliased=*/true);
149             MF->getFrameInfo().setObjectAlignment(FrameIndex, Alignment);
150           } else {
151             FrameIndex = MF->getFrameInfo().CreateStackObject(TySize, Alignment,
152                                                               false, AI);
153           }
154 
155           // Scalable vectors and structures that contain scalable vectors may
156           // need a special StackID to distinguish them from other (fixed size)
157           // stack objects.
158           if (Ty->isScalableTy())
159             MF->getFrameInfo().setStackID(FrameIndex,
160                                           TFI->getStackIDForScalableVectors());
161 
162           StaticAllocaMap[AI] = FrameIndex;
163           // Update the catch handler information.
164           if (Iter != CatchObjects.end()) {
165             for (int *CatchObjPtr : Iter->second)
166               *CatchObjPtr = FrameIndex;
167           }
168         } else {
169           // FIXME: Overaligned static allocas should be grouped into
170           // a single dynamic allocation instead of using a separate
171           // stack allocation for each one.
172           // Inform the Frame Information that we have variable-sized objects.
173           MF->getFrameInfo().CreateVariableSizedObject(
174               Alignment <= StackAlign ? Align(1) : Alignment, AI);
175         }
176       } else if (auto *Call = dyn_cast<CallBase>(&I)) {
177         // Look for inline asm that clobbers the SP register.
178         if (Call->isInlineAsm()) {
179           Register SP = TLI->getStackPointerRegisterToSaveRestore();
180           const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
181           std::vector<TargetLowering::AsmOperandInfo> Ops =
182               TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI,
183                                     *Call);
184           for (TargetLowering::AsmOperandInfo &Op : Ops) {
185             if (Op.Type == InlineAsm::isClobber) {
186               // Clobbers don't have SDValue operands, hence SDValue().
187               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
188               std::pair<unsigned, const TargetRegisterClass *> PhysReg =
189                   TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
190                                                     Op.ConstraintVT);
191               if (PhysReg.first == SP)
192                 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
193             }
194           }
195         }
196         // Look for calls to the @llvm.va_start intrinsic. We can omit some
197         // prologue boilerplate for variadic functions that don't examine their
198         // arguments.
199         if (const auto *II = dyn_cast<IntrinsicInst>(&I)) {
200           if (II->getIntrinsicID() == Intrinsic::vastart)
201             MF->getFrameInfo().setHasVAStart(true);
202         }
203 
204         // If we have a musttail call in a variadic function, we need to ensure
205         // we forward implicit register parameters.
206         if (const auto *CI = dyn_cast<CallInst>(&I)) {
207           if (CI->isMustTailCall() && Fn->isVarArg())
208             MF->getFrameInfo().setHasMustTailInVarArgFunc(true);
209         }
210       }
211 
212       // Mark values used outside their block as exported, by allocating
213       // a virtual register for them.
214       if (isUsedOutsideOfDefiningBlock(&I))
215         if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(&I)))
216           InitializeRegForValue(&I);
217 
218       // Decide the preferred extend type for a value.
219       PreferredExtendType[&I] = getPreferredExtendForValue(&I);
220     }
221   }
222 
223   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
224   // also creates the initial PHI MachineInstrs, though none of the input
225   // operands are populated.
226   for (const BasicBlock &BB : *Fn) {
227     // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
228     // are really data, and no instructions can live here.
229     if (BB.isEHPad()) {
230       const Instruction *PadInst = BB.getFirstNonPHI();
231       // If this is a non-landingpad EH pad, mark this function as using
232       // funclets.
233       // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid
234       // setting this in such cases in order to improve frame layout.
235       if (!isa<LandingPadInst>(PadInst)) {
236         MF->setHasEHScopes(true);
237         MF->setHasEHFunclets(true);
238         MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
239       }
240       if (isa<CatchSwitchInst>(PadInst)) {
241         assert(&*BB.begin() == PadInst &&
242                "WinEHPrepare failed to remove PHIs from imaginary BBs");
243         continue;
244       }
245       if (isa<FuncletPadInst>(PadInst))
246         assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
247     }
248 
249     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB);
250     MBBMap[&BB] = MBB;
251     MF->push_back(MBB);
252 
253     // Transfer the address-taken flag. This is necessary because there could
254     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
255     // the first one should be marked.
256     if (BB.hasAddressTaken())
257       MBB->setAddressTakenIRBlock(const_cast<BasicBlock *>(&BB));
258 
259     // Mark landing pad blocks.
260     if (BB.isEHPad())
261       MBB->setIsEHPad();
262 
263     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
264     // appropriate.
265     for (const PHINode &PN : BB.phis()) {
266       if (PN.use_empty())
267         continue;
268 
269       // Skip empty types
270       if (PN.getType()->isEmptyTy())
271         continue;
272 
273       DebugLoc DL = PN.getDebugLoc();
274       unsigned PHIReg = ValueMap[&PN];
275       assert(PHIReg && "PHI node does not have an assigned virtual register!");
276 
277       SmallVector<EVT, 4> ValueVTs;
278       ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs);
279       for (EVT VT : ValueVTs) {
280         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
281         const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
282         for (unsigned i = 0; i != NumRegisters; ++i)
283           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
284         PHIReg += NumRegisters;
285       }
286     }
287   }
288 
289   if (isFuncletEHPersonality(Personality)) {
290     WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
291 
292     // Map all BB references in the WinEH data to MBBs.
293     for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
294       for (WinEHHandlerType &H : TBME.HandlerArray) {
295         if (H.Handler)
296           H.Handler = MBBMap[cast<const BasicBlock *>(H.Handler)];
297       }
298     }
299     for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
300       if (UME.Cleanup)
301         UME.Cleanup = MBBMap[cast<const BasicBlock *>(UME.Cleanup)];
302     for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
303       const auto *BB = cast<const BasicBlock *>(UME.Handler);
304       UME.Handler = MBBMap[BB];
305     }
306     for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) {
307       const auto *BB = cast<const BasicBlock *>(CME.Handler);
308       CME.Handler = MBBMap[BB];
309     }
310   } else if (Personality == EHPersonality::Wasm_CXX) {
311     WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
312     calculateWasmEHInfo(&fn, EHInfo);
313 
314     // Map all BB references in the Wasm EH data to MBBs.
315     DenseMap<BBOrMBB, BBOrMBB> SrcToUnwindDest;
316     for (auto &KV : EHInfo.SrcToUnwindDest) {
317       const auto *Src = cast<const BasicBlock *>(KV.first);
318       const auto *Dest = cast<const BasicBlock *>(KV.second);
319       SrcToUnwindDest[MBBMap[Src]] = MBBMap[Dest];
320     }
321     EHInfo.SrcToUnwindDest = std::move(SrcToUnwindDest);
322     DenseMap<BBOrMBB, SmallPtrSet<BBOrMBB, 4>> UnwindDestToSrcs;
323     for (auto &KV : EHInfo.UnwindDestToSrcs) {
324       const auto *Dest = cast<const BasicBlock *>(KV.first);
325       UnwindDestToSrcs[MBBMap[Dest]] = SmallPtrSet<BBOrMBB, 4>();
326       for (const auto P : KV.second)
327         UnwindDestToSrcs[MBBMap[Dest]].insert(
328             MBBMap[cast<const BasicBlock *>(P)]);
329     }
330     EHInfo.UnwindDestToSrcs = std::move(UnwindDestToSrcs);
331   }
332 }
333 
334 /// clear - Clear out all the function-specific state. This returns this
335 /// FunctionLoweringInfo to an empty state, ready to be used for a
336 /// different function.
337 void FunctionLoweringInfo::clear() {
338   MBBMap.clear();
339   ValueMap.clear();
340   VirtReg2Value.clear();
341   StaticAllocaMap.clear();
342   LiveOutRegInfo.clear();
343   VisitedBBs.clear();
344   ArgDbgValues.clear();
345   DescribedArgs.clear();
346   ByValArgFrameIndexMap.clear();
347   RegFixups.clear();
348   RegsWithFixups.clear();
349   StatepointStackSlots.clear();
350   StatepointRelocationMaps.clear();
351   PreferredExtendType.clear();
352   PreprocessedDbgDeclares.clear();
353 }
354 
355 /// CreateReg - Allocate a single virtual register for the given type.
356 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) {
357   return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT, isDivergent));
358 }
359 
360 /// CreateRegs - Allocate the appropriate number of virtual registers of
361 /// the correctly promoted or expanded types.  Assign these registers
362 /// consecutive vreg numbers and return the first assigned number.
363 ///
364 /// In the case that the given value has struct or array type, this function
365 /// will assign registers for each member or element.
366 ///
367 Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) {
368   SmallVector<EVT, 4> ValueVTs;
369   ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
370 
371   Register FirstReg;
372   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
373     EVT ValueVT = ValueVTs[Value];
374     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
375 
376     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
377     for (unsigned i = 0; i != NumRegs; ++i) {
378       Register R = CreateReg(RegisterVT, isDivergent);
379       if (!FirstReg) FirstReg = R;
380     }
381   }
382   return FirstReg;
383 }
384 
385 Register FunctionLoweringInfo::CreateRegs(const Value *V) {
386   return CreateRegs(V->getType(), UA && UA->isDivergent(V) &&
387                                       !TLI->requiresUniformRegister(*MF, V));
388 }
389 
390 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
391 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
392 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
393 /// the larger bit width by zero extension. The bit width must be no smaller
394 /// than the LiveOutInfo's existing bit width.
395 const FunctionLoweringInfo::LiveOutInfo *
396 FunctionLoweringInfo::GetLiveOutRegInfo(Register Reg, unsigned BitWidth) {
397   if (!LiveOutRegInfo.inBounds(Reg))
398     return nullptr;
399 
400   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
401   if (!LOI->IsValid)
402     return nullptr;
403 
404   if (BitWidth > LOI->Known.getBitWidth()) {
405     LOI->NumSignBits = 1;
406     LOI->Known = LOI->Known.anyext(BitWidth);
407   }
408 
409   return LOI;
410 }
411 
412 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
413 /// register based on the LiveOutInfo of its operands.
414 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
415   Type *Ty = PN->getType();
416   if (!Ty->isIntegerTy() || Ty->isVectorTy())
417     return;
418 
419   SmallVector<EVT, 1> ValueVTs;
420   ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
421   assert(ValueVTs.size() == 1 &&
422          "PHIs with non-vector integer types should have a single VT.");
423   EVT IntVT = ValueVTs[0];
424 
425   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
426     return;
427   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
428   unsigned BitWidth = IntVT.getSizeInBits();
429 
430   auto It = ValueMap.find(PN);
431   if (It == ValueMap.end())
432     return;
433 
434   Register DestReg = It->second;
435   if (DestReg == 0)
436     return;
437   assert(DestReg.isVirtual() && "Expected a virtual reg");
438   LiveOutRegInfo.grow(DestReg);
439   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
440 
441   Value *V = PN->getIncomingValue(0);
442   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
443     DestLOI.NumSignBits = 1;
444     DestLOI.Known = KnownBits(BitWidth);
445     return;
446   }
447 
448   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
449     APInt Val;
450     if (TLI->signExtendConstant(CI))
451       Val = CI->getValue().sext(BitWidth);
452     else
453       Val = CI->getValue().zext(BitWidth);
454     DestLOI.NumSignBits = Val.getNumSignBits();
455     DestLOI.Known = KnownBits::makeConstant(Val);
456   } else {
457     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
458                                 "CopyToReg node was created.");
459     Register SrcReg = ValueMap[V];
460     if (!SrcReg.isVirtual()) {
461       DestLOI.IsValid = false;
462       return;
463     }
464     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
465     if (!SrcLOI) {
466       DestLOI.IsValid = false;
467       return;
468     }
469     DestLOI = *SrcLOI;
470   }
471 
472   assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
473          DestLOI.Known.One.getBitWidth() == BitWidth &&
474          "Masks should have the same bit width as the type.");
475 
476   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
477     Value *V = PN->getIncomingValue(i);
478     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
479       DestLOI.NumSignBits = 1;
480       DestLOI.Known = KnownBits(BitWidth);
481       return;
482     }
483 
484     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
485       APInt Val;
486       if (TLI->signExtendConstant(CI))
487         Val = CI->getValue().sext(BitWidth);
488       else
489         Val = CI->getValue().zext(BitWidth);
490       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
491       DestLOI.Known.Zero &= ~Val;
492       DestLOI.Known.One &= Val;
493       continue;
494     }
495 
496     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
497                                 "its CopyToReg node was created.");
498     Register SrcReg = ValueMap[V];
499     if (!SrcReg.isVirtual()) {
500       DestLOI.IsValid = false;
501       return;
502     }
503     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
504     if (!SrcLOI) {
505       DestLOI.IsValid = false;
506       return;
507     }
508     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
509     DestLOI.Known = DestLOI.Known.intersectWith(SrcLOI->Known);
510   }
511 }
512 
513 /// setArgumentFrameIndex - Record frame index for the byval
514 /// argument. This overrides previous frame index entry for this argument,
515 /// if any.
516 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
517                                                  int FI) {
518   ByValArgFrameIndexMap[A] = FI;
519 }
520 
521 /// getArgumentFrameIndex - Get frame index for the byval argument.
522 /// If the argument does not have any assigned frame index then 0 is
523 /// returned.
524 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
525   auto I = ByValArgFrameIndexMap.find(A);
526   if (I != ByValArgFrameIndexMap.end())
527     return I->second;
528   LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
529   return INT_MAX;
530 }
531 
532 Register FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
533     const Value *CPI, const TargetRegisterClass *RC) {
534   MachineRegisterInfo &MRI = MF->getRegInfo();
535   auto I = CatchPadExceptionPointers.insert({CPI, 0});
536   Register &VReg = I.first->second;
537   if (I.second)
538     VReg = MRI.createVirtualRegister(RC);
539   assert(VReg && "null vreg in exception pointer table!");
540   return VReg;
541 }
542 
543 const Value *
544 FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) {
545   if (VirtReg2Value.empty()) {
546     SmallVector<EVT, 4> ValueVTs;
547     for (auto &P : ValueMap) {
548       ValueVTs.clear();
549       ComputeValueVTs(*TLI, Fn->getParent()->getDataLayout(),
550                       P.first->getType(), ValueVTs);
551       unsigned Reg = P.second;
552       for (EVT VT : ValueVTs) {
553         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
554         for (unsigned i = 0, e = NumRegisters; i != e; ++i)
555           VirtReg2Value[Reg++] = P.first;
556       }
557     }
558   }
559   return VirtReg2Value.lookup(Vreg);
560 }
561